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pinctrl: rockchip: add support for rk1808 SoCs
Add support for pinctrl on RK1808 SoCs. Change-Id: I0688a61af139cc24363b7515036c80d25ff6a738 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This commit is contained in:
@@ -61,6 +61,7 @@
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enum rockchip_pinctrl_type {
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PX30,
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RV1108,
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RK1808,
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RK2928,
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RK3066B,
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RK3128,
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@@ -1648,6 +1649,86 @@ static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
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return 0;
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}
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#define RK1808_PULL_PMU_OFFSET 0x10
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#define RK1808_PULL_GRF_OFFSET 0x80
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#define RK1808_PULL_PINS_PER_REG 8
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#define RK1808_PULL_BITS_PER_PIN 2
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#define RK1808_PULL_BANK_STRIDE 16
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static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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if (bank->bank_num == 0) {
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*regmap = info->regmap_pmu;
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*reg = RK1808_PULL_PMU_OFFSET;
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} else {
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*reg = RK1808_PULL_GRF_OFFSET;
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*regmap = info->regmap_base;
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}
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*reg += ((pin_num / RK1808_PULL_PINS_PER_REG) * 4);
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*bit = (pin_num % RK1808_PULL_PINS_PER_REG);
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*bit *= RK1808_PULL_BITS_PER_PIN;
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}
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#define RK1808_DRV_PMU_OFFSET 0x20
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#define RK1808_DRV_GRF_OFFSET 0x140
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#define RK1808_DRV_BITS_PER_PIN 2
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#define RK1808_DRV_PINS_PER_REG 8
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#define RK1808_DRV_BANK_STRIDE 16
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static enum rockchip_pin_drv_type
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rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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if (bank->bank_num == 0) {
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*regmap = info->regmap_pmu;
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*reg = RK1808_DRV_PMU_OFFSET;
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} else {
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*regmap = info->regmap_base;
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*reg = RK1808_DRV_GRF_OFFSET;
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}
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*reg += ((pin_num / RK1808_DRV_PINS_PER_REG) * 4);
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*bit = pin_num % RK1808_DRV_PINS_PER_REG;
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*bit *= RK1808_DRV_BITS_PER_PIN;
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return DRV_TYPE_IO_DEFAULT;
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}
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#define RK1808_SCHMITT_PMU_OFFSET 0x0040
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#define RK1808_SCHMITT_GRF_OFFSET 0x0100
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#define RK1808_SCHMITT_BANK_STRIDE 16
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#define RK1808_SCHMITT_PINS_PER_REG 8
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static int rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num,
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struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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if (bank->bank_num == 0) {
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*regmap = info->regmap_pmu;
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*reg = RK1808_SCHMITT_PMU_OFFSET;
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} else {
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*regmap = info->regmap_base;
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*reg = RK1808_SCHMITT_GRF_OFFSET;
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}
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*reg += bank->bank_num * RK1808_SCHMITT_BANK_STRIDE;
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*reg += ((pin_num / RK1808_SCHMITT_PINS_PER_REG) * 4);
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*bit = pin_num % RK1808_SCHMITT_PINS_PER_REG;
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return 0;
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}
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#define RK2928_PULL_OFFSET 0x118
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#define RK2928_PULL_PINS_PER_REG 16
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#define RK2928_PULL_BANK_STRIDE 8
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@@ -2829,6 +2910,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
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return pull ? false : true;
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case PX30:
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case RV1108:
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case RK1808:
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case RK3188:
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case RK3288:
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case RK3308:
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@@ -4026,6 +4108,29 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
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.schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
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};
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static struct rockchip_pin_bank rk1808_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU),
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PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", 0, 0, 0, 0),
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};
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static struct rockchip_pin_ctrl rk1808_pin_ctrl = {
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.pin_banks = rk1808_pin_banks,
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.nr_banks = ARRAY_SIZE(rk1808_pin_banks),
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.label = "RK1808-GPIO",
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.type = RK1808,
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.grf_mux_offset = 0x10,
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.pmu_mux_offset = 0x0,
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.pull_calc_reg = rk1808_calc_pull_reg_and_bit,
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.drv_calc_reg = rk1808_calc_drv_reg_and_bit,
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.schmitt_calc_reg = rk1808_calc_schmitt_reg_and_bit,
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};
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static struct rockchip_pin_bank rk2928_pin_banks[] = {
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PIN_BANK(0, 32, "gpio0"),
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PIN_BANK(1, 32, "gpio1"),
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@@ -4414,6 +4519,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
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.data = &px30_pin_ctrl },
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{ .compatible = "rockchip,rv1108-pinctrl",
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.data = &rv1108_pin_ctrl },
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{ .compatible = "rockchip,rk1808-pinctrl",
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.data = &rk1808_pin_ctrl },
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{ .compatible = "rockchip,rk2928-pinctrl",
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.data = &rk2928_pin_ctrl },
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{ .compatible = "rockchip,rk3036-pinctrl",
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