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clk: rockchip: Add adaptive frequency scaling for pll_rk3399

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Change-Id: Id7be0fd4045f273052d69f49df1272922fb8f8dc
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Finley Xiao
2017-07-12 19:18:56 +08:00
committed by Tao Huang
parent d25e9e589c
commit b2ebd03a39
1 changed files with 12 additions and 3 deletions
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15
drivers/clk/rockchip/clk-pll.c
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@@ -876,6 +876,9 @@ static unsigned long rockchip_rk3399_pll_recalc_rate(struct clk_hw *hw,
struct rockchip_pll_rate_table cur;
u64 rate64 = prate;
if (pll->sel && pll->scaling)
return pll->scaling;
rockchip_rk3399_pll_get_params(pll, &cur);
rate64 *= cur.fbdiv;
@@ -971,9 +974,11 @@ static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate,
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
const struct rockchip_pll_rate_table *rate;
unsigned long old_rate = rockchip_rk3399_pll_recalc_rate(hw, prate);
int ret;
pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
__func__, __clk_get_name(hw->clk), drate, prate);
pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
__func__, __clk_get_name(hw->clk), old_rate, drate, prate);
/* Get required rate settings from table */
rate = rockchip_get_pll_settings(pll, drate);
@@ -983,7 +988,11 @@ static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate,
return -EINVAL;
}
return rockchip_rk3399_pll_set_params(pll, rate);
ret = rockchip_rk3399_pll_set_params(pll, rate);
if (ret)
pll->scaling = 0;
return ret;
}
static int rockchip_rk3399_pll_enable(struct clk_hw *hw)