shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-10 04:48:04 +09:00
Code Issues Packages Projects Releases Wiki Activity

rk29: clock: make aclk_lcdc as high as possible

Browse Source
This commit is contained in:
黄涛
2011-07-14 16:27:24 +08:00
parent 168894d423
commit b455d081e0
1 changed files with 3 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/mach-rk29/clock.c
View File

@@ -2536,7 +2536,6 @@ static void __init rk29_clock_common_init(unsigned long ppll_rate, unsigned long
clk_set_parent_nolock(&clk_uart01_src, &general_pll_clk);
clk_set_parent_nolock(&clk_uart23_src, &general_pll_clk);
clk_set_parent_nolock(&dclk_lcdc_div, &general_pll_clk);
clk_set_parent_nolock(&aclk_lcdc, &general_pll_clk);
clk_set_parent_nolock(&clk_mac_ref_div, &general_pll_clk);
clk_set_parent_nolock(&clk_hsadc_div, &general_pll_clk);
@@ -2544,6 +2543,8 @@ static void __init rk29_clock_common_init(unsigned long ppll_rate, unsigned long
clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
clk_set_parent_nolock(&clk_gpu, &codec_pll_clk);
clk_set_parent_nolock(&aclk_lcdc, cpll_rate > ppll_rate ? &codec_pll_clk : &general_pll_clk);
/* arm pll */
clk_set_rate_nolock(&arm_pll_clk, armclk);
@@ -2635,7 +2636,7 @@ void __init rk29_clock_init2(enum periph_pll ppll_rate, enum codec_pll cpll_rate
printk(KERN_INFO "Clocking rate (apll/dpll/cpll/gpll/core/aclk_cpu/hclk_cpu/pclk_cpu/aclk_periph/hclk_periph/pclk_periph): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz",
arm_pll_clk.rate / MHZ, ddr_pll_clk.rate / MHZ, codec_pll_clk.rate / MHZ, general_pll_clk.rate / MHZ, clk_core.rate / MHZ,
aclk_cpu.rate / MHZ, hclk_cpu.rate / MHZ, pclk_cpu.rate / MHZ, aclk_periph.rate / MHZ, hclk_periph.rate / MHZ, pclk_periph.rate / MHZ);
printk(KERN_CONT " (20110712)\n");
printk(KERN_CONT " (20110714)\n");
}
void __init rk29_clock_init(enum periph_pll ppll_rate)