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ARM: tegra: enable clk reset for non-peripheral clocks

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Add a new 'reset' clk op. This can be provided for any clock,
not just peripherals.

Change-Id: I0742cfad1587ddc006066c7fa9bc22f180c04e6f
Signed-off-by: Dima Zavin <dima@android.com>
This commit is contained in:
Dima Zavin
2010-09-02 19:11:11 -07:00
committed by Colin Cross
parent 33264d0f2c
commit b63adaa65d
2 changed files with 20 additions and 12 deletions
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1
arch/arm/mach-tegra/clock.h
View File

@@ -86,6 +86,7 @@ struct clk_ops {
int (*set_parent)(struct clk *, struct clk *);
int (*set_rate)(struct clk *, unsigned long);
long (*round_rate)(struct clk *, unsigned long);
void (*reset)(struct clk *, bool);
};
enum clk_state {

31
arch/arm/mach-tegra/tegra2_clocks.c
View File

@@ -262,6 +262,18 @@ static struct clk_ops tegra_clk_m_ops = {
.disable = tegra2_clk_m_disable,
};
void tegra2_periph_reset_assert(struct clk *c)
{
BUG_ON(!c->ops->reset);
c->ops->reset(c, true);
}
void tegra2_periph_reset_deassert(struct clk *c)
{
BUG_ON(!c->ops->reset);
c->ops->reset(c, false);
}
/* super clock functions */
/* "super clocks" on tegra have two-stage muxes and a clock skipping
* super divider. We will ignore the clock skipping divider, since we
@@ -869,23 +881,17 @@ static void tegra2_periph_clk_disable(struct clk *c)
CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
}
void tegra2_periph_reset_deassert(struct clk *c)
static void tegra2_periph_clk_reset(struct clk *c, bool assert)
{
pr_debug("%s on clock %s\n", __func__, c->name);
unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
pr_debug("%s %s on clock %s\n", __func__,
assert ? "assert" : "deassert", c->name);
if (!(c->flags & PERIPH_NO_RESET))
clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
base + PERIPH_CLK_TO_ENB_SET_REG(c));
}
void tegra2_periph_reset_assert(struct clk *c)
{
pr_debug("%s on clock %s\n", __func__, c->name);
if (!(c->flags & PERIPH_NO_RESET))
clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
RST_DEVICES_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
}
static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
{
u32 val;
@@ -976,6 +982,7 @@ static struct clk_ops tegra_periph_clk_ops = {
.set_parent = &tegra2_periph_clk_set_parent,
.set_rate = &tegra2_periph_clk_set_rate,
.round_rate = &tegra2_periph_clk_round_rate,
.reset = &tegra2_periph_clk_reset,
};
/* Clock doubler ops */