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RK3368 GPU: Update OPP users to put reference

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According to
commit 8a31d9d942 ("PM / OPP: Update OPP users to put reference")

Change-Id: Iece900f2814f84d14e1f67fb3d78d724b3ad9dc3
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This commit is contained in:
Tao Huang
2019-10-11 18:06:29 +08:00
parent 088f84bf55
commit b66185cc7e
2 changed files with 4 additions and 10 deletions
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11
drivers/staging/imgtec/rogue/pvr_dvfs_device.c
View File

@@ -103,17 +103,15 @@ static IMG_INT32 devfreq_target(struct device *dev, long unsigned *requested_fre
if (g_gpu_performance == 1)
*requested_freq = psDVFSDevice->psDevFreq->max_freq;
rcu_read_lock();
opp = devfreq_recommended_opp(dev, requested_freq, flags);
if (IS_ERR(opp)) {
rcu_read_unlock();
PVR_DPF((PVR_DBG_ERROR, "Invalid OPP"));
return PTR_ERR(opp);
}
ui32Freq = OPP_GET_FREQ(opp);
ui32Volt = OPP_GET_VOLTAGE(opp);
rcu_read_unlock();
dev_pm_opp_put(opp);
ui32CurFreq = psRGXTimingInfo->ui32CoreClockSpeed;
ui32CurVolt = psRGXTimingInfo->ui32CoreVoltage;
@@ -253,11 +251,9 @@ static int GetOPPValues(struct device *dev,
#endif
/* Start RCU read-side critical section to access device opp_list. */
rcu_read_lock();
count = OPP_GET_OPP_COUNT(dev);
if (count < 0) {
dev_err(dev, "Could not fetch OPP count, %d\n", count);
rcu_read_unlock();
return count;
}
@@ -268,7 +264,6 @@ static int GetOPPValues(struct device *dev,
#endif
if (!freq_table) {
rcu_read_unlock();
return -ENOMEM;
}
@@ -287,6 +282,7 @@ static int GetOPPValues(struct device *dev,
freq_table[0] = freq;
*min_freq = freq;
*min_volt = OPP_GET_VOLTAGE(opp);
dev_pm_opp_put(opp);
dev_info(dev, "opp[%d/%d]: (%lu Hz, %lu uV)\n", 1, count,
freq, *min_volt);
@@ -306,12 +302,11 @@ static int GetOPPValues(struct device *dev,
*max_freq = freq;
dev_info(dev, "opp[%d/%d]: (%lu Hz, %lu uV)\n", i + 1, count,
freq, OPP_GET_VOLTAGE(opp));
dev_pm_opp_put(opp);
}
exit:
rcu_read_unlock();
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
if (!err)
{

3
drivers/staging/imgtec/rogue/rk3368/rk_init.c
View File

@@ -1002,7 +1002,6 @@ static IMG_BOOL rk33_dvfs_get_freq_table(struct rk_context *platform)
RGX_DVFS_STEP = 0;
rcu_read_lock();
length = dev_pm_opp_get_opp_count(dev);
if (length <= 0) {
PVR_DPF((PVR_DBG_ERROR, "rgx freq table not assigned yet,use default\n"));
@@ -1018,11 +1017,11 @@ static IMG_BOOL rk33_dvfs_get_freq_table(struct rk_context *platform)
break;
}
rgx_dvfs_infotbl[i].voltage = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
rgx_dvfs_infotbl[i].clock = clk_round_rate(platform->sclk_gpu_core, rate) / ONE_MHZ;
PVR_DPF((PVR_DBG_WARNING, "%dM,%dMv", rgx_dvfs_infotbl[i].clock, rgx_dvfs_infotbl[i].voltage));
RGX_DVFS_STEP++;
}
rcu_read_unlock();
if (RGX_DVFS_STEP > 1)
div_dvfs = round_up(((levelf_threshold_max - level0_threshold_max) / (RGX_DVFS_STEP - 1)), 1);