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PCI: rockchip: dw-ep: Support link up status double check
Change-Id: I6b1807ea1dce5c05a040823717b50edf7a6109d9 Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
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@@ -744,7 +744,7 @@ static int rockchip_pcie_config_host(struct rockchip_pcie *rockchip)
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struct device *dev = rockchip->pci.dev;
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struct dw_pcie *pci = &rockchip->pci;
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u32 reg, val;
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int ret, retry, i;
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int ret, retries, i;
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/* Detecting ATU features to achieve DWC ATU interface development */
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dw_pcie_iatu_detect(&rockchip->pci);
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@@ -811,7 +811,8 @@ static int rockchip_pcie_config_host(struct rockchip_pcie *rockchip)
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}
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rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
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for (retry = 0; retry < 1000; retry++) {
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retries = 1000;
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for (i = 0; i < retries; i++) {
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if (dw_pcie_link_up(&rockchip->pci)) {
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/*
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* We may be here in case of L0 in Gen1. But if EP is capable
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@@ -820,10 +821,13 @@ static int rockchip_pcie_config_host(struct rockchip_pcie *rockchip)
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* that LTSSM max timeout is 24ms per period, we can wait a bit
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* more for Gen switch.
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*/
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msleep(2000);
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dev_info(dev, "PCIe Link up, LTSSM is 0x%x\n",
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rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS));
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break;
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msleep(50);
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/* In case link drop after linkup, double check it */
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if (dw_pcie_link_up(pci)) {
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dev_info(pci->dev, "PCIe Link up, LTSSM is 0x%x\n",
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rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS));
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break;
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}
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}
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dev_info_ratelimited(dev, "PCIe Linking... LTSSM is 0x%x\n",
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@@ -831,7 +835,7 @@ static int rockchip_pcie_config_host(struct rockchip_pcie *rockchip)
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msleep(20);
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}
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if (retry >= 10000) {
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if (i >= retries) {
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ret = -ENODEV;
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return ret;
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}
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