PCI: rockchip: dw-ep: Support link up status double check

Change-Id: I6b1807ea1dce5c05a040823717b50edf7a6109d9
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin
2024-09-18 18:22:22 +08:00
committed by Tao Huang
parent f3dd6b3cc4
commit b730a5ac78

View File

@@ -744,7 +744,7 @@ static int rockchip_pcie_config_host(struct rockchip_pcie *rockchip)
struct device *dev = rockchip->pci.dev;
struct dw_pcie *pci = &rockchip->pci;
u32 reg, val;
int ret, retry, i;
int ret, retries, i;
/* Detecting ATU features to achieve DWC ATU interface development */
dw_pcie_iatu_detect(&rockchip->pci);
@@ -811,7 +811,8 @@ static int rockchip_pcie_config_host(struct rockchip_pcie *rockchip)
}
rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
for (retry = 0; retry < 1000; retry++) {
retries = 1000;
for (i = 0; i < retries; i++) {
if (dw_pcie_link_up(&rockchip->pci)) {
/*
* We may be here in case of L0 in Gen1. But if EP is capable
@@ -820,10 +821,13 @@ static int rockchip_pcie_config_host(struct rockchip_pcie *rockchip)
* that LTSSM max timeout is 24ms per period, we can wait a bit
* more for Gen switch.
*/
msleep(2000);
dev_info(dev, "PCIe Link up, LTSSM is 0x%x\n",
rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS));
break;
msleep(50);
/* In case link drop after linkup, double check it */
if (dw_pcie_link_up(pci)) {
dev_info(pci->dev, "PCIe Link up, LTSSM is 0x%x\n",
rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS));
break;
}
}
dev_info_ratelimited(dev, "PCIe Linking... LTSSM is 0x%x\n",
@@ -831,7 +835,7 @@ static int rockchip_pcie_config_host(struct rockchip_pcie *rockchip)
msleep(20);
}
if (retry >= 10000) {
if (i >= retries) {
ret = -ENODEV;
return ret;
}