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rk3288-mipi-dsi: rk32 mipi dsi add label, and fix send commad.
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@@ -1,128 +1,19 @@
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/*
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drivers/video/rockchip/transmitter/rk616_mipi_dsi.h
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drivers/video/rockchip/transmitter/rk32_mipi_dsi.h
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*/
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#include <linux/rockchip/grf.h>
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#ifndef RK616_MIPI_DSI_H
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#define RK616_MIPI_DSI_H
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#define MIPI_DSI_PHY_OFFSET 0x0C00
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#define MIPI_DSI_PHY_SIZE 0x34c
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#define MIPI_DSI_HOST_OFFSET 0x1000
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#ifdef DWC_DSI_VERSION_0x3131302A
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#define MIPI_DSI_HOST_SIZE 0x74
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#else
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#define MIPI_DSI_HOST_SIZE 0xcc
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#endif
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//function bits definition register addr | bits | offest
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#define REG_ADDR(a) ((a) << 16)
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#define REG_BITS(a) ((a) << 8)
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#define BITS_OFFSET(a) (a)
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#define DSI_HOST_BITS(addr, bits, bit_offset) (REG_ADDR((addr)+MIPI_DSI_HOST_OFFSET) \
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| REG_BITS(bits) | BITS_OFFSET(bit_offset))
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#define DSI_DPHY_BITS(addr, bits, bit_offset) (REG_ADDR((addr)+MIPI_DSI_PHY_OFFSET) \
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| REG_BITS(bits) | BITS_OFFSET(bit_offset))
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#ifdef DWC_DSI_VERSION_0x3131302A
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#define VERSION DSI_HOST_BITS(0x00, 32, 0)
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#define GEN_HDR DSI_HOST_BITS(0x34, 32, 0)
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#define GEN_PLD_DATA DSI_HOST_BITS(0x38, 32, 0)
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#define ERROR_ST0 DSI_HOST_BITS(0x44, 21, 0)
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#define ERROR_ST1 DSI_HOST_BITS(0x48, 18, 0)
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#define ERROR_MSK0 DSI_HOST_BITS(0x4C, 21, 0)
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#define ERROR_MSK1 DSI_HOST_BITS(0x50, 18, 0)
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#define shutdownz DSI_HOST_BITS(0x04, 1, 0)
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#define en18_loosely DSI_HOST_BITS(0x0c, 1, 10)
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#define colorm_active_low DSI_HOST_BITS(0x0c, 1, 9)
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#define shutd_active_low DSI_HOST_BITS(0x0c, 1, 8)
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#define hsync_active_low DSI_HOST_BITS(0x0c, 1, 7)
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#define vsync_active_low DSI_HOST_BITS(0x0c, 1, 6)
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#define dataen_active_low DSI_HOST_BITS(0x0c, 1, 5)
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#define dpi_color_coding DSI_HOST_BITS(0x0c, 3, 2)
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#define dpi_vcid DSI_HOST_BITS(0x0c, 1, 0)
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#define vid_hline_time DSI_HOST_BITS(0x28, 14, 18)
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#define vid_hbp_time DSI_HOST_BITS(0x28, 9, 9)
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#define vid_hsa_time DSI_HOST_BITS(0x28, 9, 0)
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#define vid_active_lines DSI_HOST_BITS(0x2c, 11, 16)
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#define vid_vfp_lines DSI_HOST_BITS(0x2c, 6, 10)
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#define vid_vbp_lines DSI_HOST_BITS(0x2c, 6, 4)
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#define vid_vsa_lines DSI_HOST_BITS(0x2c, 4, 0)
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#define TO_CLK_DIVISION DSI_HOST_BITS(0x08, 8, 8)
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#define TX_ESC_CLK_DIVISION DSI_HOST_BITS(0x08, 8, 0)
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#define gen_vid_rx DSI_HOST_BITS(0x18, 2, 5)
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#define crc_rx_en DSI_HOST_BITS(0x18, 1, 4)
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#define ecc_rx_en DSI_HOST_BITS(0x18, 1, 3)
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#define bta_en DSI_HOST_BITS(0x18, 1, 2)
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#define eotp_rx_en DSI_HOST_BITS(0x18, 1, 1)
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#define eotp_tx_en DSI_HOST_BITS(0x18, 1, 0)
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#define lp_cmd_en DSI_HOST_BITS(0x1c, 1, 12)
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#define frame_bta_ack_en DSI_HOST_BITS(0x1c, 1, 11)
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#define en_null_pkt DSI_HOST_BITS(0x1c, 1, 10)
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#define en_multi_pkt DSI_HOST_BITS(0x1c, 1, 9)
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#define lp_hfp_en DSI_HOST_BITS(0x1c, 1, 8)
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#define lp_hbp_en DSI_HOST_BITS(0x1c, 1, 7)
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#define lp_vact_en DSI_HOST_BITS(0x1c, 1, 6)
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#define lp_vfp_en DSI_HOST_BITS(0x1c, 1, 5)
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#define lp_vbp_en DSI_HOST_BITS(0x1c, 1, 4)
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#define lp_vsa_en DSI_HOST_BITS(0x1c, 1, 3)
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#define vid_mode_type DSI_HOST_BITS(0x1c, 2, 1)
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#define en_video_mode DSI_HOST_BITS(0x1c, 1, 0)
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#define null_pkt_size DSI_HOST_BITS(0x20, 10, 21)
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#define num_chunks DSI_HOST_BITS(0x20, 10, 11)
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#define vid_pkt_size DSI_HOST_BITS(0x20, 11, 0)
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#define tear_fx_en DSI_HOST_BITS(0x24, 1, 14)
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#define ack_rqst_en DSI_HOST_BITS(0x24, 1, 13)
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#define dcs_lw_tx DSI_HOST_BITS(0x24, 1, 12)
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#define gen_lw_tx DSI_HOST_BITS(0x24, 1, 11)
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#define max_rd_pkt_size DSI_HOST_BITS(0x24, 1, 10)
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#define dcs_sr_0p_tx DSI_HOST_BITS(0x24, 1, 9)
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#define dcs_sw_1p_tx DSI_HOST_BITS(0x24, 1, 8)
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#define dcs_sw_0p_tx DSI_HOST_BITS(0x24, 1, 7)
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#define gen_sr_2p_tx DSI_HOST_BITS(0x24, 1, 6)
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#define gen_sr_1p_tx DSI_HOST_BITS(0x24, 1, 5)
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#define gen_sr_0p_tx DSI_HOST_BITS(0x24, 1, 4)
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#define gen_sw_2p_tx DSI_HOST_BITS(0x24, 1, 3)
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#define gen_sw_1p_tx DSI_HOST_BITS(0x24, 1, 2)
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#define gen_sw_0p_tx DSI_HOST_BITS(0x24, 1, 1)
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#define en_cmd_mode DSI_HOST_BITS(0x24, 1, 0)
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#define phy_hs2lp_time DSI_HOST_BITS(0x30, 8, 24)
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#define phy_lp2hs_time DSI_HOST_BITS(0x30, 8, 16)
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#define max_rd_time DSI_HOST_BITS(0x30, 15, 0)
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#define lprx_to_cnt DSI_HOST_BITS(0x40, 16, 16)
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#define hstx_to_cnt DSI_HOST_BITS(0x40, 16, 0)
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#define phy_enableclk DSI_HOST_BITS(0x54, 1, 2)
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//#define phy_rstz DSI_HOST_BITS(0x54, 1, 1)
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//#define phy_shutdownz DSI_HOST_BITS(0x54, 1, 0)
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#define phy_stop_wait_time DSI_HOST_BITS(0x58, 8, 2)
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#define n_lanes DSI_HOST_BITS(0x58, 2, 0)
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#define phy_tx_triggers DSI_HOST_BITS(0x5c, 4, 5)
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#define phy_txexitulpslan DSI_HOST_BITS(0x5c, 1, 4)
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#define phy_txrequlpslan DSI_HOST_BITS(0x5c, 1, 3)
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#define phy_txexitulpsclk DSI_HOST_BITS(0x5c, 1, 2)
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#define phy_txrequlpsclk DSI_HOST_BITS(0x5c, 1, 1)
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#define phy_txrequestclkhs DSI_HOST_BITS(0x5c, 1, 0)
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#define phy_testclk DSI_HOST_BITS(0x64, 1, 1)
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#define phy_testclr DSI_HOST_BITS(0x64, 1, 0)
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#define phy_testen DSI_HOST_BITS(0x68, 1, 16)
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#define phy_testdout DSI_HOST_BITS(0x68, 8, 8)
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#define phy_testdin DSI_HOST_BITS(0x68, 8, 0)
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#define outvact_lpcmd_time DSI_HOST_BITS(0x70, 8, 8)
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#define invact_lpcmd_time DSI_HOST_BITS(0x70, 8, 0)
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#define gen_rd_cmd_busy DSI_HOST_BITS(0x3c, 1, 6)
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#define gen_pld_r_full DSI_HOST_BITS(0x3c, 1, 5)
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#define gen_pld_r_empty DSI_HOST_BITS(0x3c, 1, 4)
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#define gen_pld_w_full DSI_HOST_BITS(0x3c, 1, 3) //800byte write GEN_PLD_DATA
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#define gen_pld_w_empty DSI_HOST_BITS(0x3c, 1, 2)
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#define gen_cmd_full DSI_HOST_BITS(0x3c, 1, 1) //20 write GEN_HDR
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#define gen_cmd_empty DSI_HOST_BITS(0x3c, 1, 0)
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#define phystopstateclklane DSI_HOST_BITS(0x60, 1, 2)
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#define phylock DSI_HOST_BITS(0x60, 1, 0)
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#else //***************************************************************//
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//DWC_DSI_VERSION_0x3133302A
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#define VERSION DSI_HOST_BITS(0x000, 32, 0)
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#define shutdownz DSI_HOST_BITS(0x004, 1, 0)
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@@ -256,98 +147,6 @@ drivers/video/rockchip/transmitter/rk616_mipi_dsi.h
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#define code_hstxdatalanehszerostatetime 0x72
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//#define en_null_pkt DSI_HOST_BITS(0x1c, 1, 13) //delete
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//#define en_multi_pkt DSI_HOST_BITS(0x1c, 1, 13) //delete
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#endif /* end of DWC_DSI_VERSION_0x3131302A */
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//MIPI DSI DPHY REGISTERS
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#define DPHY_REGISTER0 DSI_DPHY_BITS(0x00, 32, 0)
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#define DPHY_REGISTER1 DSI_DPHY_BITS(0x04, 32, 0)
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#define DPHY_REGISTER3 DSI_DPHY_BITS(0x0c, 32, 0)
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#define DPHY_REGISTER4 DSI_DPHY_BITS(0x10, 32, 0)
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#define DPHY_REGISTER20 DSI_DPHY_BITS(0X80, 32, 0)
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#define lane_en_ck DSI_DPHY_BITS(0x00, 1, 6)
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#define lane_en_3 DSI_DPHY_BITS(0x00, 1, 5)
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#define lane_en_2 DSI_DPHY_BITS(0x00, 1, 4)
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#define lane_en_1 DSI_DPHY_BITS(0x00, 1, 3)
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#define lane_en_0 DSI_DPHY_BITS(0x00, 1, 2)
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#define reg_da_ppfc DSI_DPHY_BITS(0x04, 1, 4)
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#define reg_da_syncrst DSI_DPHY_BITS(0x04, 1, 2)
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#define reg_da_ldopd DSI_DPHY_BITS(0x04, 1, 1)
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#define reg_da_pllpd DSI_DPHY_BITS(0x04, 1, 0)
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#define reg_fbdiv_8 DSI_DPHY_BITS(0x0c, 1, 5)
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#define reg_prediv DSI_DPHY_BITS(0x0c, 5, 0)
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#define reg_fbdiv DSI_DPHY_BITS(0x10, 8, 0)
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#define reg_dig_rstn DSI_DPHY_BITS(0X80, 1, 0)
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#define DPHY_CLOCK_OFFSET REG_ADDR(0X0100)
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#define DPHY_LANE0_OFFSET REG_ADDR(0X0180)
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#define DPHY_LANE1_OFFSET REG_ADDR(0X0200)
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#define DPHY_LANE2_OFFSET REG_ADDR(0X0280)
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#define DPHY_LANE3_OFFSET REG_ADDR(0X0300)
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#define reg_ths_settle DSI_DPHY_BITS(0x0000, 4, 0)
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#define reg_hs_tlpx DSI_DPHY_BITS(0x0014, 6, 0)
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#define reg_hs_ths_prepare DSI_DPHY_BITS(0x0018, 7, 0)
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#define reg_hs_the_zero DSI_DPHY_BITS(0x001c, 6, 0)
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#define reg_hs_ths_trail DSI_DPHY_BITS(0x0020, 7, 0)
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#define reg_hs_ths_exit DSI_DPHY_BITS(0x0024, 5, 0)
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#define reg_hs_tclk_post DSI_DPHY_BITS(0x0028, 4, 0)
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#define reserved DSI_DPHY_BITS(0x002c, 1, 0)
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#define reg_hs_twakup_h DSI_DPHY_BITS(0x0030, 2, 0)
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#define reg_hs_twakup_l DSI_DPHY_BITS(0x0034, 8, 0)
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#define reg_hs_tclk_pre DSI_DPHY_BITS(0x0038, 4, 0)
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#define reg_hs_tta_go DSI_DPHY_BITS(0x0040, 6, 0)
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#define reg_hs_tta_sure DSI_DPHY_BITS(0x0044, 6, 0)
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#define reg_hs_tta_wait DSI_DPHY_BITS(0x0048, 6, 0)
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#ifdef DWC_DSI_VERSION_0x3131302A
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//MISC REGISTERS
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#define DSI_MISC_BITS(addr, bits, bit_offset) (REG_ADDR(addr) \
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| REG_BITS(bits) | BITS_OFFSET(bit_offset))
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#define CRU_CRU_CLKSEL1_CON (0x005c)
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#define CRU_CFG_MISC_CON (0x009c)
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#define cfg_mipiclk_gaten DSI_MISC_BITS(CRU_CRU_CLKSEL1_CON, 1, 10)
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#define mipi_int DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 19)
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#define mipi_edpihalt DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 16)
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#define pin_forcetxstopmode_3 DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 11)
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#define pin_forcetxstopmode_2 DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 10)
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#define pin_forcetxstopmode_1 DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 9)
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#define pin_forcetxstopmode_0 DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 8)
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#define pin_forcerxmode_0 DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 7)
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#define pin_turndisable_0 DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 6)
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#define dpicolom DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 2)
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#define dpishutdn DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 1)
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#else
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//#define mipi_int
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//#define mipi_edpihalt
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#define pin_forcetxstopmode_3
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#define pin_forcetxstopmode_2
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#define pin_forcetxstopmode_1
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#define pin_forcetxstopmode_0
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#define pin_forcerxmode_0
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#define pin_turndisable_0
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#define dpicolom
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#define dpishutdn
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#endif
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//global operation timing parameter
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struct gotp_m {
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//time uint is ns
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@@ -383,7 +182,6 @@ struct gotp {
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u32 WAKEUP; //min:1ms max:no
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};
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struct dsi_phy {
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u32 UI;
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u32 ref_clk; //input_clk
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@@ -435,9 +233,6 @@ struct dsi {
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#ifdef CONFIG_MIPI_DSI_LINUX
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struct clk *dsi_pclk;
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struct clk *dsi_pd;
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#ifdef CONFIG_HAS_EARLYSUSPEND
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struct early_suspend early_suspend;
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#endif
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#endif
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struct dentry *debugfs_dir;
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struct platform_device *pdev;
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@@ -447,6 +242,4 @@ int rk_mipi_get_dsi_clk(void);
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int rk_mipi_get_dsi_num(void);
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int rk_mipi_get_dsi_lane(void);
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extern int rk616_mipi_dsi_ft_init(void);
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int rk_mipi_dsi_init_lite(struct dsi *dsi);
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#endif /* end of RK616_MIPI_DSI_H */
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