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pinctrl: rockchip: refine drive strength levels for RV1126B

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This commit has refined the driver strength configuration of the RV1126B
from 6 levels to 23 levels

Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I61cee294cbb194366909acc70dec3d41a0a1e961
This commit is contained in:
Ye Zhang
2025-05-16 17:51:55 +08:00
committed by Tao Huang
parent 4502ce6f66
commit b7b90f1ca9
1 changed files with 29 additions and 22 deletions
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51
drivers/pinctrl/pinctrl-rockchip.c
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@@ -316,19 +316,12 @@
#define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \
PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
#define PIN_BANK_IOMUX_4_OFFSET_DRV_8(id, pins, label, offset0, \
offset1, offset2, offset3) \
PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(id, pins, label, \
IOMUX_WIDTH_4BIT, \
IOMUX_WIDTH_4BIT, \
IOMUX_WIDTH_4BIT, \
IOMUX_WIDTH_4BIT, \
offset0, offset1, \
offset2, offset3, \
DRV_TYPE_IO_LEVEL_8_BIT, \
DRV_TYPE_IO_LEVEL_8_BIT, \
DRV_TYPE_IO_LEVEL_8_BIT, \
DRV_TYPE_IO_LEVEL_8_BIT)
#define PIN_BANK_IOMUX_4_OFFSET(id, pins, label, offset0, \
offset1, offset2, offset3) \
PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, \
IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, \
IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, \
offset0, offset1, offset2, offset3)
static struct pinctrl_dev *g_pctldev;
static DEFINE_MUTEX(iomux_lock);
@@ -3624,6 +3617,17 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
if (ret)
return ret;
if (ctrl->type == RV1126B) {
rmask_bits = RV1126B_DRV_BITS_PER_PIN;
ret = regmap_read(regmap, reg, &data);
if (ret)
return ret;
data >>= bit;
data &= (1 << rmask_bits) - 1;
return data;
}
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
@@ -3745,7 +3749,6 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
ret = strength;
goto config;
} else if (ctrl->type == RV1106 ||
ctrl->type == RV1126B ||
ctrl->type == RK3506 ||
ctrl->type == RK3528 ||
ctrl->type == RK3562 ||
@@ -3757,6 +3760,10 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
rmask_bits = RK3576_DRV_BITS_PER_PIN;
ret = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1));
goto config;
} else if (ctrl->type == RV1126B) {
rmask_bits = RV1126B_DRV_BITS_PER_PIN;
ret = strength;
goto config;
}
ret = -EINVAL;
@@ -5312,21 +5319,21 @@ static struct rockchip_pin_ctrl rv1126_pin_ctrl __maybe_unused = {
};
static struct rockchip_pin_bank rv1126b_pin_banks[] = {
PIN_BANK_IOMUX_4_OFFSET_DRV_8(0, 32, "gpio0",
PIN_BANK_IOMUX_4_OFFSET(0, 32, "gpio0",
0x0, 0x8, 0x8010, 0x8018),
PIN_BANK_IOMUX_4_OFFSET_DRV_8(1, 32, "gpio1",
PIN_BANK_IOMUX_4_OFFSET(1, 32, "gpio1",
0x10020, 0x10028, 0x10030, 0x10038),
PIN_BANK_IOMUX_4_OFFSET_DRV_8(2, 32, "gpio2",
PIN_BANK_IOMUX_4_OFFSET(2, 32, "gpio2",
0x18040, 0x18048, 0x18050, 0x18058),
PIN_BANK_IOMUX_4_OFFSET_DRV_8(3, 32, "gpio3",
PIN_BANK_IOMUX_4_OFFSET(3, 32, "gpio3",
0x20060, 0x20068, 0x20070, 0x20078),
PIN_BANK_IOMUX_4_OFFSET_DRV_8(4, 32, "gpio4",
PIN_BANK_IOMUX_4_OFFSET(4, 32, "gpio4",
0x28080, 0x28088, 0x28090, 0x28098),
PIN_BANK_IOMUX_4_OFFSET_DRV_8(5, 32, "gpio5",
PIN_BANK_IOMUX_4_OFFSET(5, 32, "gpio5",
0x300a0, 0x300a8, 0x300b0, 0x300b8),
PIN_BANK_IOMUX_4_OFFSET_DRV_8(6, 32, "gpio6",
PIN_BANK_IOMUX_4_OFFSET(6, 32, "gpio6",
0x380c0, 0x380c8, 0x380d0, 0x380d8),
PIN_BANK_IOMUX_4_OFFSET_DRV_8(7, 32, "gpio7",
PIN_BANK_IOMUX_4_OFFSET(7, 32, "gpio7",
0x400e0, 0x400e8, 0x400f0, 0x400f8),
};