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drm/rockchip: vop2: add more log for debug
Signed-off-by: Sandy Huang <hjc@rock-chips.com> Change-Id: Id31728617b26d2c744633aad770b869d814843e5
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@@ -8484,8 +8484,10 @@ vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
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* modes of the right VP should be set as invalid when vop2 is working in
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* splice mode.
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*/
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if (vp->splice_mode_right)
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if (vp->splice_mode_right) {
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DRM_DEV_DEBUG(vop2->dev, "vp%d is in splice mode right\n", vp->id);
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return MODE_BAD;
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}
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if ((active_vp_mask & BIT(ROCKCHIP_VOP_VP1)) && !vcstate->splice_mode &&
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mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
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@@ -8494,15 +8496,21 @@ vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
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return MODE_BAD;
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}
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if (mode->hdisplay > vp_data->max_output.width)
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if (mode->hdisplay > vp_data->max_output.width) {
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DRM_DEV_DEBUG(vop2->dev, "hdisplay:%d is out of max_output width:%d\n",
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mode->hdisplay, vp_data->max_output.width);
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return MODE_BAD_HVALUE;
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}
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if (mode->flags & DRM_MODE_FLAG_DBLCLK || vcstate->output_if & VOP_OUTPUT_IF_BT656)
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request_clock *= 2;
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/* Pixel rate verify */
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if (request_clock > vp_data->dclk_max / 1000)
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if (request_clock > vp_data->dclk_max / 1000) {
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DRM_DEV_DEBUG(vop2->dev, "request_clock:%d is out of dclk_max:%ld\n",
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request_clock, vp_data->dclk_max / 1000);
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return MODE_CLOCK_HIGH;
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}
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if ((request_clock <= VOP2_MAX_DCLK_RATE) &&
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(vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll") ||
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@@ -8524,9 +8532,14 @@ vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
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* Hdmi or DisplayPort request a Accurate clock.
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*/
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if (vcstate->output_type == DRM_MODE_CONNECTOR_HDMIA ||
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vcstate->output_type == DRM_MODE_CONNECTOR_DisplayPort)
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if (clock != request_clock)
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vcstate->output_type == DRM_MODE_CONNECTOR_DisplayPort) {
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if (clock != request_clock) {
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DRM_DEV_DEBUG(vop2->dev,
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"round rate:%d is not equal to request rate:%d\n",
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clock, request_clock);
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return MODE_CLOCK_RANGE;
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}
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}
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return MODE_OK;
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}
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