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rk3036 lcdc: commit driver code, just pass compiling.
This commit is contained in:
Zheng Yang
97
arch/arm/boot/dts/lcd-box.dtsi
Executable file
97
arch/arm/boot/dts/lcd-box.dtsi
Executable file
@@ -0,0 +1,97 @@
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/*
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* RockChip. LCD_BOX
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*
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*/
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/ {
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disp_power_ctr: power_ctr {
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/* rockchip,debug = <0>;
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lcd_en:lcd_en {
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rockchip,power_type = <GPIO>;
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gpios = <&gpio0 GPIO_B0 GPIO_ACTIVE_HIGH>;
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rockchip,delay = <10>;
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};
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bl_en:bl_en {
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rockchip,power_type = <GPIO>;
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gpios = <&gpio0 GPIO_A2 GPIO_ACTIVE_HIGH>;
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rockchip,delay = <10>;
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};
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bl_ctr:bl_ctr {
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rockchip,power_type = <GPIO>;
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gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
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rockchip,delay = <10>;
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};
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lcd_rst:lcd_rst {
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rockchip,power_type = <REGULATOR>;
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rockchip,delay = <5>;
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};*/
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};
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disp_timings: display-timings {
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native-mode = <&timing0>;
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timing0: timing0 {
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screen-type = <SCREEN_RGB>;
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out-face = <OUT_P888>;
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clock-frequency = <74250000>;
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hactive = <1280>;
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vactive = <720>;
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hback-porch = <220>;
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hfront-porch = <110>;
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vback-porch = <20>;
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vfront-porch = <5>;
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hsync-len = <40>;
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vsync-len = <5>;
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hsync-active = <1>;
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vsync-active = <1>;
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de-active = <0>;
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pixelclk-active = <0>;
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swap-rb = <0>;
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swap-rg = <0>;
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swap-gb = <0>;
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};
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timing1: timing1 {
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screen-type = <SCREEN_RGB>;
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out-face = <OUT_P888>;
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clock-frequency = <148500000>;
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hactive = <1920>;
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vactive = <1080>;
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hback-porch = <148>;
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hfront-porch = <88>;
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vback-porch = <36>;
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vfront-porch = <4>;
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hsync-len = <44>;
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vsync-len = <5>;
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hsync-active = <1>;
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vsync-active = <1>;
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de-active = <0>;
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pixelclk-active = <0>;
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swap-rb = <0>;
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swap-rg = <0>;
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swap-gb = <0>;
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};
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timing2: timing2 {
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screen-type = <SCREEN_RGB>;
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out-face = <OUT_P888>;
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clock-frequency = <297000000>;
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hactive = <3840>;
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vactive = <2160>;
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hback-porch = <296>;
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hfront-porch = <176>;
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vback-porch = <72>;
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vfront-porch = <8>;
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hsync-len = <88>;
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vsync-len = <10>;
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hsync-active = <1>;
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vsync-active = <1>;
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de-active = <0>;
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pixelclk-active = <0>;
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swap-rb = <0>;
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swap-rg = <0>;
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swap-gb = <0>;
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};
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};
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};
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@@ -1,6 +1,7 @@
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/dts-v1/;
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#include <dt-bindings/rkfb/rk_fb.h>
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#include "rk3036.dtsi"
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#include "lcd-box.dtsi"
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/ {
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compatible = "rockchip,rk3036";
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@@ -400,7 +400,17 @@
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clocks = <&clk_gates1 6>, <&clk_gates7 3>;
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clock-names = "clk_usbphy1", "hclk_usb1";
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};
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lcdc: lcdc@10118000 {
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compatible = "rockchip,rk3036-lcdc";
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reg = <0x10118000 0x4000>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&clk_gates9 6>, <&dclk_lcdc1>, <&clk_gates9 5>;
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clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
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rockchip,iommu-enabled = <1>;
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};
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hdmi: hdmi@20034000 {
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compatible = "rockchip,rk3036-hdmi";
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reg = <0x20034000 0x4000>;
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@@ -413,7 +423,7 @@
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clock-names = "pclk_hdmi";
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status = "disabled";
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};
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/*
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vpu: vpu_service@10108000 {
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compatible = "vpu_service";
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reg = <0x10108000 0x800>;
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@@ -434,7 +444,7 @@
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clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
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name = "hevc_service";
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status = "disabled";
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*/
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vop_mmu {
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dbgname = "vop";
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compatible = "iommu,vop_mmu";
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@@ -31,3 +31,9 @@ config LCDC_RK3288
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depends on DRM_ROCKCHIP || FB_ROCKCHIP
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help
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Driver for rk3288 lcdc.There are two lcd controllers on rk3288
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config LCDC_RK3036
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bool "rk3036 lcdc support"
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depends on DRM_ROCKCHIP || FB_ROCKCHIP
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help
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Driver for rk3036 lcdc.
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@@ -3,3 +3,4 @@ obj-$(CONFIG_LCDC_RK2928) += rk2928_lcdc.o
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obj-$(CONFIG_LCDC_RK3066B) += rk3066b_lcdc.o
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obj-$(CONFIG_LCDC_RK3188) += rk3188_lcdc.o
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obj-$(CONFIG_LCDC_RK3288) += rk3288_lcdc.o
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obj-$(CONFIG_LCDC_RK3036) += rk3036_lcdc.o
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1247
drivers/video/rockchip/lcdc/rk3036_lcdc.c
Normal file
1247
drivers/video/rockchip/lcdc/rk3036_lcdc.c
Normal file
File diff suppressed because it is too large
Load Diff
546
drivers/video/rockchip/lcdc/rk3036_lcdc.h
Normal file
546
drivers/video/rockchip/lcdc/rk3036_lcdc.h
Normal file
@@ -0,0 +1,546 @@
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#ifndef _RK3036_LCDC_H_
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#define _RK3036_LCDC_H_
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#include<linux/rk_fb.h>
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#include<linux/io.h>
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#include<linux/clk.h>
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/*******************register definition**********************/
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#define SYS_CTRL (0x00)
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#define m_WIN0_EN (1<<0)
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#define m_WIN1_EN (1<<1)
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#define m_HWC_EN (1<<2)
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#define m_WIN0_FORMAT (7<<3)
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#define m_WIN1_FORMAT (7<<6)
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#define m_HWC_LUT_EN (1<<9)
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#define m_HWC_SIZE (1<<10)
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#define m_WIN0_RB_SWAP (1<<15)
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#define m_WIN0_ALPHA_SWAP (1<<16)
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#define m_WIN0_Y8_SWAP (1<<17)
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#define m_WIN0_UV_SWAP (1<<18)
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#define m_WIN1_RB_SWAP (1<<19)
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#define m_WIN1_ALPHA_SWAP (1<<20)
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#define m_WIN0_OTSD_DISABLE (1<<22)
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#define m_WIN1_OTSD_DISABLE (1<<23)
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#define m_DMA_BURST_LENGTH (3<<24)
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#define m_HWC_LODAD_EN (1<<26)
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#define m_DMA_STOP (1<<29)
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#define m_LCDC_STANDBY (1<<30)
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#define m_AUTO_GATING_EN (1<<31)
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#define v_WIN0_EN(x) (((x)&1)<<0)
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#define v_WIN1_EN(x) (((x)&1)<<1)
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#define v_HWC_EN(x) (((x)&1)<<2)
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#define v_WIN0_FORMAT(x) (((x)&7)<<3)
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#define v_WIN1_FORMAT(x) (((x)&7)<<6)
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#define v_HWC_LUT_EN(x) (((x)&1)<<9)
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#define v_HWC_SIZE(x) (((x)&1)<<10)
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#define v_WIN0_RB_SWAP(x) (((x)&1)<<15)
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#define v_WIN0_ALPHA_SWAP(x) (((x)&1)<<16)
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#define v_WIN0_Y8_SWAP(x) (((x)&1)<<17)
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#define v_WIN0_UV_SWAP(x) (((x)&1)<<18)
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#define v_WIN1_RB_SWAP(x) (((x)&1)<<19)
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#define v_WIN1_ALPHA_SWAP(x) (((x)&1)<<20)
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#define v_WIN0_OTSD_DISABLE(x) (((x)&1)<<22)
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#define v_WIN1_OTSD_DISABLE(x) (((x)&1)<<23)
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#define v_DMA_BURST_LENGTH(x) (((x)&3)<<24)
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#define v_HWC_LODAD_EN(x) (((x)&1)<<26)
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#define v_WIN1_LUT_EN(x) (((x)&1)<<27)
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#define v_DMA_STOP(x) (((x)&1)<<29)
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#define v_LCDC_STANDBY(x) (((x)&1)<<30)
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#define v_AUTO_GATING_EN(x) (((x)&1)<<31)
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#define DSP_CTRL0 (0x04)
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#define m_DSP_OUT_FORMAT (0x0f<<0)
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#define m_HSYNC_POL (1<<4)
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#define m_VSYNC_POL (1<<5)
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#define m_DEN_POL (1<<6)
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#define m_DCLK_POL (1<<7)
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#define m_WIN0_TOP (1<<8)
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#define m_DITHER_UP_EN (1<<9)
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#define m_INTERLACE_DSP_EN (1<<12)
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#define m_WIN1_INTERLACE_EN (1<<15)
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#define m_WIN0_YRGB_DEFLICK_EN (1<<16)
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#define m_WIN0_CBR_DEFLICK_EN (1<<17)
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#define m_WIN0_ALPHA_MODE (1<<18)
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#define m_WIN1_ALPHA_MODE (1<<19)
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#define m_WIN0_CSC_MODE (3<<20)
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#define m_WIN0_YUV_CLIP (1<<23)
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#define m_TVE_MODE (1<<25)
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#define m_HWC_ALPHA_MODE (1<<28)
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#define m_PREMUL_ALPHA_ENABLE (1<<29)
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#define m_ALPHA_MODE_SEL1 (1<<30)
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#define m_WIN1_DIFF_DCLK_EN (1<<31)
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#define v_DSP_OUT_FORMAT(x) (((x)&0x0f)<<0)
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#define v_HSYNC_POL(x) (((x)&1)<<4)
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#define v_VSYNC_POL(x) (((x)&1)<<5)
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#define v_DEN_POL(x) (((x)&1)<<6)
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#define v_DCLK_POL(x) (((x)&1)<<7)
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#define v_WIN0_TOP(x) (((x)&1)<<8)
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#define v_DITHER_UP_EN(x) (((x)&1)<<9)
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#define v_INTERLACE_DSP_EN(x) (((x)&1)<<12)
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#define v_WIN1_INTERLACE_EN(x) (((x)&1)<<15)
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#define v_WIN0_YRGB_DEFLICK_EN(x) (((x)&1)<<16)
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#define v_WIN0_CBR_DEFLICK_EN(x) (((x)&1)<<17)
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#define v_WIN0_ALPHA_MODE(x) (((x)&1)<<18)
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#define v_WIN1_ALPHA_MODE(x) (((x)&1)<<19)
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#define v_WIN0_CSC_MODE(x) (((x)&3)<<20)
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#define v_WIN0_YUV_CLIP(x) (((x)&1)<<23)
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#define v_TVE_MODE(x) (((x)&1)<<25)
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#define v_HWC_ALPHA_MODE(x) (((x)&1)<<28)
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#define v_PREMUL_ALPHA_ENABLE(x) (((x)&1)<<29)
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#define v_ALPHA_MODE_SEL1(x) (((x)&1)<<30)
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#define v_WIN1_DIFF_DCLK_EN(x) (((x)&1)<<31)
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#define DSP_CTRL1 (0x08)
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#define m_BG_COLOR (0xffffff<<0)
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#define m_BG_B (0xff<<0)
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#define m_BG_G (0xff<<8)
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#define m_BG_R (0xff<<16)
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#define m_BLANK_EN (1<<24)
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#define m_BLACK_EN (1<<25)
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#define m_DSP_BG_SWAP (1<<26)
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#define m_DSP_RB_SWAP (1<<27)
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#define m_DSP_RG_SWAP (1<<28)
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#define m_DSP_DELTA_SWAP (1<<29)
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#define m_DSP_DUMMY_SWAP (1<<30)
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#define m_DSP_OUT_ZERO (1<<31)
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#define v_BG_COLOR(x) (((x)&0xffffff)<<0)
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#define v_BG_B(x) (((x)&0xff)<<0)
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#define v_BG_G(x) (((x)&0xff)<<8)
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#define v_BG_R(x) (((x)&0xff)<<16)
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#define v_BLANK_EN(x) (((x)&1)<<24)
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#define v_BLACK_EN(x) (((x)&1)<<25)
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#define v_DSP_BG_SWAP(x) (((x)&1)<<26)
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#define v_DSP_RB_SWAP(x) (((x)&1)<<27)
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#define v_DSP_RG_SWAP(x) (((x)&1)<<28)
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||||
#define v_DSP_DELTA_SWAP(x) (((x)&1)<<29)
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#define v_DSP_DUMMY_SWAP(x) (((x)&1)<<30)
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#define v_DSP_OUT_ZERO(x) (((x)&1)<<31)
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||||
#define INT_STATUS (0x10)
|
||||
#define m_HS_INT_STA (1<<0) //status
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#define m_FS_INT_STA (1<<1)
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#define m_LF_INT_STA (1<<2)
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||||
#define m_BUS_ERR_INT_STA (1<<3)
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#define m_HS_INT_EN (1<<4) //enable
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#define m_FS_INT_EN (1<<5)
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#define m_LF_INT_EN (1<<6)
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||||
#define m_BUS_ERR_INT_EN (1<<7)
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||||
#define m_HS_INT_CLEAR (1<<8) //auto clear
|
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#define m_FS_INT_CLEAR (1<<9)
|
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#define m_LF_INT_CLEAR (1<<10)
|
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#define m_BUS_ERR_INT_CLEAR (1<<11)
|
||||
#define m_LF_INT_NUM (0xfff<<12)
|
||||
#define m_WIN0_EMPTY_INT_EN (1<<24)
|
||||
#define m_WIN1_EMPTY_INT_EN (1<<25)
|
||||
#define m_WIN0_EMPTY_INT_CLEAR (1<<26)
|
||||
#define m_WIN1_EMPTY_INT_CLEAR (1<<27)
|
||||
#define m_WIN0_EMPTY_INT_STA (1<<28)
|
||||
#define m_WIN1_EMPTY_INT_STA (1<<29)
|
||||
#define m_FS_RAW_STA (1<<30)
|
||||
#define m_LF_RAW_STA (1<<31)
|
||||
|
||||
#define v_HS_INT_EN(x) (((x)&1)<<4)
|
||||
#define v_FS_INT_EN(x) (((x)&1)<<5)
|
||||
#define v_LF_INT_EN(x) (((x)&1)<<6)
|
||||
#define v_BUS_ERR_INT_EN(x) (((x)&1)<<7)
|
||||
#define v_HS_INT_CLEAR(x) (((x)&1)<<8)
|
||||
#define v_FS_INT_CLEAR(x) (((x)&1)<<9)
|
||||
#define v_LF_INT_CLEAR(x) (((x)&1)<<10)
|
||||
#define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11)
|
||||
#define v_LF_INT_NUM(x) (((x)&0xfff)<<12)
|
||||
#define v_WIN0_EMPTY_INT_EN(x) (((x)&1)<<24)
|
||||
#define v_WIN1_EMPTY_INT_EN(x) (((x)&1)<<25)
|
||||
#define v_WIN0_EMPTY_INT_CLEAR(x) (((x)&1)<<26)
|
||||
#define v_WIN1_EMPTY_INT_CLEAR(x) (((x)&1)<<27)
|
||||
|
||||
|
||||
#define ALPHA_CTRL (0x14)
|
||||
#define m_WIN0_ALPHA_EN (1<<0)
|
||||
#define m_WIN1_ALPHA_EN (1<<1)
|
||||
#define m_HWC_ALPAH_EN (1<<2)
|
||||
#define m_WIN1_PREMUL_SCALE (1<<3)
|
||||
#define m_WIN0_ALPHA_VAL (0xff<<4)
|
||||
#define m_WIN1_ALPHA_VAL (0xff<<12)
|
||||
#define m_HWC_ALPAH_VAL (0x0f<<20)
|
||||
|
||||
#define v_WIN0_ALPHA_EN(x) (((x)&1)<<0)
|
||||
#define v_WIN1_ALPHA_EN(x) (((x)&1)<<1)
|
||||
#define v_HWC_ALPAH_EN(x) (((x)&1)<<2)
|
||||
#define v_WIN1_PREMUL_SCALE(x) (((x)&1)<<3)
|
||||
#define v_WIN0_ALPHA_VAL(x) (((x)&0xff)<<4)
|
||||
#define v_WIN1_ALPHA_VAL(x) (((x)&0xff)<<12)
|
||||
#define v_HWC_ALPAH_VAL(x) (((x)&0x0f)<<20)
|
||||
|
||||
#define WIN0_COLOR_KEY (0x18)
|
||||
#define WIN1_COLOR_KEY (0x1C)
|
||||
#define m_COLOR_KEY_VAL (0xffffff<<0)
|
||||
#define m_COLOR_KEY_EN (1<<24)
|
||||
#define v_COLOR_KEY_VAL(x) (((x)&0xffffff)<<0)
|
||||
#define v_COLOR_KEY_EN(x) (((x)&1)<<24)
|
||||
|
||||
/* Layer Registers */
|
||||
#define WIN0_YRGB_MST (0x20)
|
||||
#define WIN0_CBR_MST (0x24)
|
||||
#define WIN1_MST (0xa0)
|
||||
#define HWC_MST (0x58)
|
||||
|
||||
#define WIN1_VIR (0x28)
|
||||
#define WIN0_VIR (0x30)
|
||||
#define m_YRGB_VIR (0x1fff << 0)
|
||||
#define m_CBBR_VIR (0x1fff << 16)
|
||||
|
||||
#define v_YRGB_VIR(x) ((x & 0x1fff) << 0)
|
||||
#define v_CBBR_VIR(x) ((x & 0x1fff) << 16)
|
||||
|
||||
#define v_ARGB888_VIRWIDTH(x) (((x)&0x1fff)<<0)
|
||||
#define v_RGB888_VIRWIDTH(x) (((((x*3)>>2)+((x)%3))&0x1fff)<<0)
|
||||
#define v_RGB565_VIRWIDTH(x) ((DIV_ROUND_UP(x,2)&0x1fff)<<0)
|
||||
#define v_YUV_VIRWIDTH(x) ((DIV_ROUND_UP(x,4)&0x1fff)<<0)
|
||||
#define v_CBCR_VIR(x) ((x & 0x1fff) << 16)
|
||||
|
||||
#define WIN0_ACT_INFO (0x34)
|
||||
#define WIN1_ACT_INFO (0xB4)
|
||||
#define m_ACT_WIDTH (0x1fff<<0)
|
||||
#define m_ACT_HEIGHT (0x1fff<<16)
|
||||
#define v_ACT_WIDTH(x) (((x-1)&0x1fff)<<0)
|
||||
#define v_ACT_HEIGHT(x) (((x-1)&0x1fff)<<16)
|
||||
|
||||
#define WIN0_DSP_INFO (0x38)
|
||||
#define WIN1_DSP_INFO (0xB8)
|
||||
#define v_DSP_WIDTH(x) (((x-1)&0x7ff)<<0)
|
||||
#define v_DSP_HEIGHT(x) (((x-1)&0x7ff)<<16)
|
||||
|
||||
#define WIN0_DSP_ST (0x3C)
|
||||
#define WIN1_DSP_ST (0xBC)
|
||||
#define HWC_DSP_ST (0x5C)
|
||||
#define v_DSP_STX(x) (((x)&0xfff)<<0)
|
||||
#define v_DSP_STY(x) (((x)&0xfff)<<16)
|
||||
|
||||
#define WIN0_SCL_FACTOR_YRGB (0x40)
|
||||
#define WIN0_SCL_FACTOR_CBR (0x44)
|
||||
#define WIN1_SCL_FACTOR_YRGB (0xC0)
|
||||
#define v_X_SCL_FACTOR(x) (((x)&0xffff)<<0)
|
||||
#define v_Y_SCL_FACTOR(x) (((x)&0xffff)<<16)
|
||||
|
||||
#define WIN0_SCL_OFFSET (0x48)
|
||||
#define WIN1_SCL_OFFSET (0xC8)
|
||||
|
||||
/* LUT Registers */
|
||||
#define WIN1_LUT_ADDR (0x0400)
|
||||
#define HWC_LUT_ADDR (0x0800)
|
||||
|
||||
/* Display Infomation Registers */
|
||||
#define DSP_HTOTAL_HS_END (0x6C)
|
||||
#define v_HSYNC(x) (((x)&0xfff)<<0) //hsync pulse width
|
||||
#define v_HORPRD(x) (((x)&0xfff)<<16) //horizontal period
|
||||
|
||||
#define DSP_HACT_ST_END (0x70)
|
||||
#define v_HAEP(x) (((x)&0xfff)<<0) //horizontal active end point
|
||||
#define v_HASP(x) (((x)&0xfff)<<16) //horizontal active start point
|
||||
|
||||
#define DSP_VTOTAL_VS_END (0x74)
|
||||
#define v_VSYNC(x) (((x)&0xfff)<<0)
|
||||
#define v_VERPRD(x) (((x)&0xfff)<<16)
|
||||
|
||||
#define DSP_VACT_ST_END (0x78)
|
||||
#define v_VAEP(x) (((x)&0xfff)<<0)
|
||||
#define v_VASP(x) (((x)&0xfff)<<16)
|
||||
|
||||
#define DSP_VS_ST_END_F1 (0x7C)
|
||||
#define DSP_VACT_ST_END_F1 (0x80)
|
||||
|
||||
/*BCSH Registers*/
|
||||
#define BCSH_COLOR_BAR (0xD0)
|
||||
#define v_BCSH_EN(x) (((x)&1)<<0)
|
||||
#define v_BCSH_COLOR_BAR_Y(x) (((x)&0x3ff)<<2)
|
||||
#define v_BCSH_COLOR_BAR_U(x) (((x)&0x3ff)<<12)
|
||||
#define v_BCSH_COLOR_BAR_V(x) (((x)&0x3ff)<<22)
|
||||
|
||||
#define m_BCSH_EN (1<<0)
|
||||
#define m_BCSH_COLOR_BAR_Y (0x3ff<<2)
|
||||
#define m_BCSH_COLOR_BAR_U (0x3ff<<12)
|
||||
#define m_BCSH_COLOR_BAR_V ((u32)0x3ff<<22)
|
||||
|
||||
#define BCSH_BCS (0xD4)
|
||||
#define v_BCSH_BRIGHTNESS(x) (((x)&0xff)<<0)
|
||||
#define v_BCSH_CONTRAST(x) (((x)&0x1ff)<<8)
|
||||
#define v_BCSH_SAT_CON(x) (((x)&0x3ff)<<20)
|
||||
#define v_BCSH_OUT_MODE(x) (((x)&0x3)<<30)
|
||||
|
||||
#define m_BCSH_BRIGHTNESS (0xff<<0)
|
||||
#define m_BCSH_CONTRAST (0x1ff<<8)
|
||||
#define m_BCSH_SAT_CON (0x3ff<<20)
|
||||
#define m_BCSH_OUT_MODE ((u32)0x3<<30)
|
||||
|
||||
|
||||
#define BCSH_H (0xD8)
|
||||
#define v_BCSH_SIN_HUE(x) (((x)&0x1ff)<<0)
|
||||
#define v_BCSH_COS_HUE(x) (((x)&0x1ff)<<16)
|
||||
|
||||
#define m_BCSH_SIN_HUE (0x1ff<<0)
|
||||
#define m_BCSH_COS_HUE (0x1ff<<16)
|
||||
|
||||
/* Bus Register */
|
||||
#define AXI_BUS_CTRL (0x2C)
|
||||
#define m_IO_PAD_CLK (1 << 31)
|
||||
#define m_CORE_CLK_DIV_EN (1 << 30)
|
||||
#define m_HDMI_DCLK_INVERT (1 << 23)
|
||||
#define m_HDMI_DCLK_EN (1 << 22)
|
||||
#define m_TVE_DAC_DCLK_INVERT (1 << 21)
|
||||
#define m_TVE_DAC_DCLK_EN (1 << 20)
|
||||
#define m_HDMI_DCLK_DIV_EN (1 << 19)
|
||||
#define m_AXI_OUTSTANDING_MAX_NUM (0x1f << 12)
|
||||
#define m_AXI_MAX_OUTSTANDING_EN (1 << 11)
|
||||
#define m_MMU_EN (1 << 10)
|
||||
#define m_NOC_HURRY_THRESHOLD (0xf << 6)
|
||||
#define m_NOC_HURRY_VALUE (3 << 4)
|
||||
#define m_NOC_HURRY_EN (1 << 3)
|
||||
#define m_NOC_QOS_VALUE (3 << 1)
|
||||
#define m_NOC_QOS_EN (1 << 0)
|
||||
|
||||
#define v_IO_PAD_CLK(x) ((x&1) << 31)
|
||||
#define v_CORE_CLK_DIV_EN(x) ((x&1) << 30)
|
||||
#define v_HDMI_DCLK_INVERT(x) ((x&1) << 23)
|
||||
#define v_HDMI_DCLK_EN(x) ((x&1) << 22)
|
||||
#define v_TVE_DAC_DCLK_INVERT(x) ((x&1) << 21)
|
||||
#define v_TVE_DAC_DCLK_EN(x) ((x&1) << 20)
|
||||
#define v_HDMI_DCLK_DIV_EN(x) ((x&1) << 19)
|
||||
#define v_AXI_OUTSTANDING_MAX_NUM(x) ((x&0x1f) << 12)
|
||||
#define v_AXI_MAX_OUTSTANDING_EN(x) ((x&1) << 11)
|
||||
#define v_MMU_EN(x) ((x&1) << 10)
|
||||
#define v_NOC_HURRY_THRESHOLD(x) ((x&0xf) << 6)
|
||||
#define v_NOC_HURRY_VALUE(x) ((x&3) << 4)
|
||||
#define v_NOC_HURRY_EN(x) ((x&1) << 3)
|
||||
#define v_NOC_QOS_VALUE(x) ((x&3) << 1)
|
||||
#define v_NOC_QOS_EN(x) ((x&1) << 0)
|
||||
|
||||
#define GATHER_TRANSFER (0x84)
|
||||
#define m_WIN1_AXI_GATHER_NUM (0xf << 12)
|
||||
#define m_WIN0_CBCR_AXI_GATHER_NUM (0x7 << 8)
|
||||
#define m_WIN0_YRGB_AXI_GATHER_NUM (0xf << 4)
|
||||
#define m_WIN1_AXI_GAHTER_EN (1 << 2)
|
||||
#define m_WIN0_CBCR_AXI_GATHER_EN (1 << 1)
|
||||
#define m_WIN0_YRGB_AXI_GATHER_EN (1 << 0)
|
||||
|
||||
#define v_WIN1_AXI_GATHER_NUM(x) ((x & 0xf) << 12)
|
||||
#define v_WIN0_CBCR_AXI_GATHER_NUM(x) ((x & 0x7) << 8)
|
||||
#define v_WIN0_YRGB_AXI_GATHER_NUM(x) ((x & 0xf) << 4)
|
||||
#define v_WIN1_AXI_GAHTER_EN(x) ((x & 1) << 2)
|
||||
#define v_WIN0_CBCR_AXI_GATHER_EN(x) ((x & 1) << 1)
|
||||
#define v_WIN0_YRGB_AXI_GATHER_EN(x) ((x & 1) << 0)
|
||||
|
||||
#define VERSION_INFO (0x94)
|
||||
#define m_MAJOR (0xff << 24)
|
||||
#define m_MINOR (0xff << 16)
|
||||
#define m_BUILD (0xffff)
|
||||
|
||||
#define REG_CFG_DONE (0x90)
|
||||
|
||||
/* TV Control Registers */
|
||||
#define TV_CTRL (0x200)
|
||||
#define TV_SYNC_TIMING (0x204)
|
||||
#define TV_ACT_TIMING (0x208)
|
||||
#define TV_ADJ_TIMING (0x20c)
|
||||
#define TV_FREQ_SC (0x210)
|
||||
#define TV_FILTER0 (0x214)
|
||||
#define TV_FILTER1 (0x218)
|
||||
#define TV_FILTER2 (0x21C)
|
||||
#define TV_ACT_ST (0x234)
|
||||
#define TV_ROUTING (0x238)
|
||||
#define TV_SYNC_ADJUST (0x250)
|
||||
#define TV_STATUS (0x254)
|
||||
#define TV_RESET (0x268)
|
||||
#define TV_SATURATION (0x278)
|
||||
#define TV_BW_CTRL (0x28C)
|
||||
#define TV_BRIGHTNESS_CONTRAST (0x290)
|
||||
|
||||
|
||||
/* MMU registers */
|
||||
#define MMU_DTE_ADDR (0x0300)
|
||||
#define v_MMU_DTE_ADDR(x) (((x)&0xffffffff)<<0)
|
||||
#define m_MMU_DTE_ADDR (0xffffffff<<0)
|
||||
|
||||
#define MMU_STATUS (0x0304)
|
||||
#define v_PAGING_ENABLED(x) (((x)&1)<<0)
|
||||
#define v_PAGE_FAULT_ACTIVE(x) (((x)&1)<<1)
|
||||
#define v_STAIL_ACTIVE(x) (((x)&1)<<2)
|
||||
#define v_MMU_IDLE(x) (((x)&1)<<3)
|
||||
#define v_REPLAY_BUFFER_EMPTY(x) (((x)&1)<<4)
|
||||
#define v_PAGE_FAULT_IS_WRITE(x) (((x)&1)<<5)
|
||||
#define v_PAGE_FAULT_BUS_ID(x) (((x)&0x1f)<<6)
|
||||
#define m_PAGING_ENABLED (1<<0)
|
||||
#define m_PAGE_FAULT_ACTIVE (1<<1)
|
||||
#define m_STAIL_ACTIVE (1<<2)
|
||||
#define m_MMU_IDLE (1<<3)
|
||||
#define m_REPLAY_BUFFER_EMPTY (1<<4)
|
||||
#define m_PAGE_FAULT_IS_WRITE (1<<5)
|
||||
#define m_PAGE_FAULT_BUS_ID (0x1f<<6)
|
||||
|
||||
#define MMU_COMMAND (0x0308)
|
||||
#define v_MMU_CMD(x) (((x)&0x3)<<0)
|
||||
#define m_MMU_CMD (0x3<<0)
|
||||
|
||||
#define MMU_PAGE_FAULT_ADDR (0x030c)
|
||||
#define v_PAGE_FAULT_ADDR(x) (((x)&0xffffffff)<<0)
|
||||
#define m_PAGE_FAULT_ADDR (0xffffffff<<0)
|
||||
|
||||
#define MMU_ZAP_ONE_LINE (0x0310)
|
||||
#define v_MMU_ZAP_ONE_LINE(x) (((x)&0xffffffff)<<0)
|
||||
#define m_MMU_ZAP_ONE_LINE (0xffffffff<<0)
|
||||
|
||||
#define MMU_INT_RAWSTAT (0x0314)
|
||||
#define v_PAGE_FAULT_RAWSTAT(x) (((x)&1)<<0)
|
||||
#define v_READ_BUS_ERROR_RAWSTAT(x) (((x)&1)<<1)
|
||||
#define m_PAGE_FAULT_RAWSTAT (1<<0)
|
||||
#define m_READ_BUS_ERROR_RAWSTAT (1<<1)
|
||||
|
||||
#define MMU_INT_CLEAR (0x0318)
|
||||
#define v_PAGE_FAULT_CLEAR(x) (((x)&1)<<0)
|
||||
#define v_READ_BUS_ERROR_CLEAR(x) (((x)&1)<<1)
|
||||
#define m_PAGE_FAULT_CLEAR (1<<0)
|
||||
#define m_READ_BUS_ERROR_CLEAR (1<<1)
|
||||
|
||||
#define MMU_INT_MASK (0x031c)
|
||||
#define v_PAGE_FAULT_MASK(x) (((x)&1)<<0)
|
||||
#define v_READ_BUS_ERROR_MASK(x) (((x)&1)<<1)
|
||||
#define m_PAGE_FAULT_MASK (1<<0)
|
||||
#define m_READ_BUS_ERROR_MASK (1<<1)
|
||||
|
||||
#define MMU_INT_STATUS (0x0320)
|
||||
#define v_PAGE_FAULT_STATUS(x) (((x)&1)<<0)
|
||||
#define v_READ_BUS_ERROR_STATUS(x) (((x)&1)<<1)
|
||||
#define m_PAGE_FAULT_STATUS (1<<0)
|
||||
#define m_READ_BUS_ERROR_STATUS (1<<1)
|
||||
|
||||
#define MMU_AUTO_GATING (0x0324)
|
||||
#define v_MMU_AUTO_GATING(x) (((x)&1)<<0)
|
||||
#define m_MMU_AUTO_GATING (1<<0)
|
||||
|
||||
enum _vop_dma_burst {
|
||||
DMA_BURST_16 = 0,
|
||||
DMA_BURST_8,
|
||||
DMA_BURST_4
|
||||
};
|
||||
|
||||
enum _vop_format_e {
|
||||
VOP_FORMAT_ARGB888 = 0,
|
||||
VOP_FORMAT_RGB888,
|
||||
VOP_FORMAT_RGB565,
|
||||
VOP_FORMAT_YCBCR420,
|
||||
VOP_FORMAT_YCBCR422,
|
||||
VOP_FORMAT_YCBCR444
|
||||
};
|
||||
|
||||
enum _vop_tv_mode {
|
||||
TV_NTSC,
|
||||
TV_PAL,
|
||||
};
|
||||
|
||||
enum _vop_csc_mode {
|
||||
VOP_CSC_BT601 = 0,
|
||||
VOP_CSC_JPEG,
|
||||
VOP_CSC_BT709
|
||||
};
|
||||
|
||||
enum _vop_hwc_size {
|
||||
VOP_HWC_SIZE_32,
|
||||
VOP_HWC_SIZE_64
|
||||
};
|
||||
|
||||
#define CalScale(x, y) ((((u32)(x-1))*0x1000)/(y-1))
|
||||
|
||||
struct lcdc_device{
|
||||
int id;
|
||||
struct rk_lcdc_driver driver;
|
||||
struct device *dev;
|
||||
struct rk_screen *screen;
|
||||
|
||||
void __iomem *regs;
|
||||
void *regsbak; /*back up reg*/
|
||||
u32 reg_phy_base; /* physical basic address of lcdc register*/
|
||||
u32 len; /* physical map length of lcdc register*/
|
||||
spinlock_t reg_lock; /*one time only one process allowed to config the register*/
|
||||
|
||||
int __iomem *dsp_lut_addr_base;
|
||||
|
||||
|
||||
int prop; /*used for primary or extended display device*/
|
||||
bool pre_init;
|
||||
bool pwr18; /*if lcdc use 1.8v power supply*/
|
||||
bool clk_on; /*if aclk or hclk is closed ,acess to register is not allowed*/
|
||||
u8 atv_layer_cnt; /*active layer counter,when atv_layer_cnt = 0,disable lcdc*/
|
||||
|
||||
|
||||
unsigned int irq;
|
||||
|
||||
struct clk *pd; /*lcdc power domain*/
|
||||
struct clk *hclk; /*lcdc AHP clk*/
|
||||
struct clk *dclk; /*lcdc dclk*/
|
||||
struct clk *aclk; /*lcdc share memory frequency*/
|
||||
u32 pixclock;
|
||||
|
||||
u32 standby; /*1:standby,0:wrok*/
|
||||
};
|
||||
|
||||
static inline void lcdc_writel(struct lcdc_device *lcdc_dev,u32 offset,u32 v)
|
||||
{
|
||||
u32 *_pv = (u32*)lcdc_dev->regsbak;
|
||||
_pv += (offset >> 2);
|
||||
*_pv = v;
|
||||
writel_relaxed(v,lcdc_dev->regs+offset);
|
||||
}
|
||||
|
||||
static inline u32 lcdc_readl(struct lcdc_device *lcdc_dev,u32 offset)
|
||||
{
|
||||
u32 v;
|
||||
u32 *_pv = (u32*)lcdc_dev->regsbak;
|
||||
_pv += (offset >> 2);
|
||||
v = readl_relaxed(lcdc_dev->regs+offset);
|
||||
*_pv = v;
|
||||
return v;
|
||||
}
|
||||
|
||||
static inline u32 lcdc_read_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk)
|
||||
{
|
||||
u32 _v = readl_relaxed(lcdc_dev->regs+offset);
|
||||
_v &= msk;
|
||||
return (_v?1:0);
|
||||
}
|
||||
|
||||
static inline void lcdc_set_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk)
|
||||
{
|
||||
u32* _pv = (u32*)lcdc_dev->regsbak;
|
||||
_pv += (offset >> 2);
|
||||
(*_pv) |= msk;
|
||||
writel_relaxed(*_pv,lcdc_dev->regs + offset);
|
||||
}
|
||||
|
||||
static inline void lcdc_clr_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk)
|
||||
{
|
||||
u32* _pv = (u32*)lcdc_dev->regsbak;
|
||||
_pv += (offset >> 2);
|
||||
(*_pv) &= (~msk);
|
||||
writel_relaxed(*_pv,lcdc_dev->regs + offset);
|
||||
}
|
||||
|
||||
static inline void lcdc_msk_reg(struct lcdc_device *lcdc_dev,u32 offset,u32 msk,u32 v)
|
||||
{
|
||||
u32 *_pv = (u32*)lcdc_dev->regsbak;
|
||||
_pv += (offset >> 2);
|
||||
(*_pv) &= (~msk);
|
||||
(*_pv) |= v;
|
||||
writel_relaxed(*_pv,lcdc_dev->regs+offset);
|
||||
}
|
||||
|
||||
static inline void lcdc_cfg_done(struct lcdc_device *lcdc_dev)
|
||||
{
|
||||
writel_relaxed(0x01,lcdc_dev->regs+REG_CFG_DONE);
|
||||
dsb();
|
||||
}
|
||||
|
||||
#endif /* _RK3036_LCDC_H_ */
|
||||
@@ -2832,7 +2832,8 @@ int rk_fb_dpi_open(bool open)
|
||||
{
|
||||
struct rk_lcdc_driver *dev_drv = NULL;
|
||||
dev_drv = rk_get_prmry_lcdc_drv();
|
||||
dev_drv->ops->dpi_open(dev_drv, open);
|
||||
if(dev_drv->ops->dpi_open)
|
||||
dev_drv->ops->dpi_open(dev_drv, open);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -2841,18 +2842,20 @@ int rk_fb_dpi_win_sel(int win_id)
|
||||
{
|
||||
struct rk_lcdc_driver *dev_drv = NULL;
|
||||
dev_drv = rk_get_prmry_lcdc_drv();
|
||||
dev_drv->ops->dpi_win_sel(dev_drv, win_id);
|
||||
if(dev_drv->ops->dpi_win_sel)
|
||||
dev_drv->ops->dpi_win_sel(dev_drv, win_id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rk_fb_dpi_status(void)
|
||||
{
|
||||
int ret;
|
||||
int ret = 0;
|
||||
struct rk_lcdc_driver *dev_drv = NULL;
|
||||
dev_drv = rk_get_prmry_lcdc_drv();
|
||||
ret = dev_drv->ops->dpi_status(dev_drv);
|
||||
|
||||
if(dev_drv->ops->dpi_status)
|
||||
ret = dev_drv->ops->dpi_status(dev_drv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
@@ -330,13 +330,15 @@ static ssize_t show_dsp_bcsh(struct device *dev,
|
||||
struct rk_lcdc_driver *dev_drv =
|
||||
(struct rk_lcdc_driver *)fbi->par;
|
||||
int brightness, contrast, sat_con, sin_hue, cos_hue;
|
||||
|
||||
brightness = dev_drv->ops->get_dsp_bcsh_bcs(dev_drv, BRIGHTNESS);
|
||||
contrast = dev_drv->ops->get_dsp_bcsh_bcs(dev_drv, CONTRAST);
|
||||
sat_con = dev_drv->ops->get_dsp_bcsh_bcs(dev_drv, SAT_CON);
|
||||
sin_hue = dev_drv->ops->get_dsp_bcsh_hue(dev_drv,H_SIN);
|
||||
cos_hue = dev_drv->ops->get_dsp_bcsh_hue(dev_drv,H_COS);
|
||||
|
||||
if(dev_drv->ops->get_dsp_bcsh_bcs) {
|
||||
brightness = dev_drv->ops->get_dsp_bcsh_bcs(dev_drv, BRIGHTNESS);
|
||||
contrast = dev_drv->ops->get_dsp_bcsh_bcs(dev_drv, CONTRAST);
|
||||
sat_con = dev_drv->ops->get_dsp_bcsh_bcs(dev_drv, SAT_CON);
|
||||
}
|
||||
if(dev_drv->ops->get_dsp_bcsh_hue) {
|
||||
sin_hue = dev_drv->ops->get_dsp_bcsh_hue(dev_drv,H_SIN);
|
||||
cos_hue = dev_drv->ops->get_dsp_bcsh_hue(dev_drv,H_COS);
|
||||
}
|
||||
snprintf(buf, PAGE_SIZE, "brightness:%4d,contrast:%4d,sat_con:%4d,"
|
||||
"sin_hue:%4d,cos_hue:%4d\n",
|
||||
brightness, contrast,sat_con,sin_hue,cos_hue);
|
||||
@@ -350,37 +352,56 @@ static ssize_t set_dsp_bcsh(struct device *dev, struct device_attribute *attr,
|
||||
struct rk_lcdc_driver *dev_drv =
|
||||
(struct rk_lcdc_driver *)fbi->par;
|
||||
int brightness, contrast, sat_con, ret, sin_hue, cos_hue;
|
||||
|
||||
if (!strncmp(buf, "open", 4)) {
|
||||
ret = dev_drv->ops->open_bcsh(dev_drv, 1);
|
||||
if(dev_drv->ops->open_bcsh)
|
||||
ret = dev_drv->ops->open_bcsh(dev_drv, 1);
|
||||
else
|
||||
ret = -1;
|
||||
} else if (!strncmp(buf, "close", 5)) {
|
||||
ret = dev_drv->ops->open_bcsh(dev_drv, 0);
|
||||
if(dev_drv->ops->open_bcsh)
|
||||
ret = dev_drv->ops->open_bcsh(dev_drv, 0);
|
||||
else
|
||||
ret = -1;
|
||||
} else if (!strncmp(buf, "brightness", 10)) {
|
||||
sscanf(buf, "brightness %d", &brightness);
|
||||
if (unlikely(brightness > 255)) {
|
||||
dev_err(fbi->dev,"brightness should be [0:255],now=%d\n\n",brightness);
|
||||
brightness = 255;
|
||||
}
|
||||
ret = dev_drv->ops->set_dsp_bcsh_bcs(dev_drv, BRIGHTNESS,brightness);
|
||||
if(dev_drv->ops->set_dsp_bcsh_bcs)
|
||||
ret = dev_drv->ops->set_dsp_bcsh_bcs(dev_drv, BRIGHTNESS,brightness);
|
||||
else
|
||||
ret = -1;
|
||||
} else if (!strncmp(buf, "contrast", 8)) {
|
||||
sscanf(buf, "contrast %d", &contrast);
|
||||
if (unlikely(contrast > 510)) {
|
||||
dev_err(fbi->dev,"contrast should be [0:510],now=%d\n",contrast);
|
||||
contrast = 510;
|
||||
}
|
||||
ret = dev_drv->ops->set_dsp_bcsh_bcs(dev_drv, CONTRAST,contrast);
|
||||
if(dev_drv->ops->set_dsp_bcsh_bcs)
|
||||
ret = dev_drv->ops->set_dsp_bcsh_bcs(dev_drv, CONTRAST,contrast);
|
||||
else
|
||||
ret = -1;
|
||||
} else if (!strncmp(buf, "sat_con", 7)) {
|
||||
sscanf(buf, "sat_con %d", &sat_con);
|
||||
if (unlikely(sat_con > 1015)) {
|
||||
dev_err(fbi->dev,"sat_con should be [0:1015],now=%d\n",sat_con);
|
||||
sat_con = 1015;
|
||||
}
|
||||
ret = dev_drv->ops->set_dsp_bcsh_bcs(dev_drv, SAT_CON,sat_con);
|
||||
if(dev_drv->ops->set_dsp_bcsh_bcs)
|
||||
ret = dev_drv->ops->set_dsp_bcsh_bcs(dev_drv, SAT_CON,sat_con);
|
||||
else
|
||||
ret = -1;
|
||||
} else if (!strncmp(buf, "hue", 3)) {
|
||||
sscanf(buf, "hue %d %d", &sin_hue,&cos_hue);
|
||||
if (unlikely(sin_hue > 511 || cos_hue > 511)) {
|
||||
dev_err(fbi->dev,"sin_hue=%d,cos_hue=%d\n",sin_hue,cos_hue);
|
||||
}
|
||||
ret = dev_drv->ops->set_dsp_bcsh_hue(dev_drv,sin_hue,cos_hue);
|
||||
if(dev_drv->ops->set_dsp_bcsh_hue)
|
||||
ret = dev_drv->ops->set_dsp_bcsh_hue(dev_drv,sin_hue,cos_hue);
|
||||
else
|
||||
ret = -1;
|
||||
} else {
|
||||
printk("format error\n");
|
||||
}
|
||||
|
||||
@@ -74,6 +74,7 @@ struct rk_screen {
|
||||
u16 x_mirror;
|
||||
u16 y_mirror;
|
||||
int interlace;
|
||||
int pixelrepeat; //For 480i/576i format, pixel is repeated twice.
|
||||
u16 width;
|
||||
u16 height;
|
||||
u8 ft;
|
||||
|
||||
Reference in New Issue
Block a user