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https://github.com/hardkernel/linux.git
synced 2026-06-09 04:10:18 +09:00
rk3188 pm support
This commit is contained in:
xxx
@@ -84,6 +84,7 @@
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clock_regs {
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compatible = "rockchip,rk-clock-regs";
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reg = <0x0000 0x3ff>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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@@ -1180,6 +1181,7 @@
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"reserved", "clk_spdif_div",
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"clk_spdif_frac", "g_testclk";
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rockchip,suspend-clkgating-setting=<0x00bf 0x00bf>;
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#clock-cells = <1>;
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};
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@@ -1211,6 +1213,7 @@
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"clk_uart2_div", "clk_uart2_frac",
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"clk_uart3_div", "clk_uart3_frac";
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rockchip,suspend-clkgating-setting=<0x0 0x0>;
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#clock-cells = <1>;
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};
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@@ -1242,6 +1245,8 @@
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"g_mac_lbtest", "clk_sdio",
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"clk_emmc", "reserved";
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//rockchip,suspend-clkgating-setting=<0x1f 0x1b>;
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rockchip,suspend-clkgating-setting=<0x1f 0x1b>;
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#clock-cells = <1>;
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};
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@@ -1277,6 +1282,7 @@
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"g_h_vdpu", "reserved",
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"timer6", "clk_gpu";
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rockchip,suspend-clkgating-setting=<0x0 0x0>;
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#clock-cells = <1>;
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};
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@@ -1314,6 +1320,8 @@
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"g_a_intmem", "reserved",
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"g_h_imem1", "g_h_imem0";
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//rockchip,suspend-clkgating-setting=<0xd75e 0xd75e>;
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rockchip,suspend-clkgating-setting=<0xd75e 0xd75e>;
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#clock-cells = <1>;
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};
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@@ -1342,6 +1350,7 @@
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"g_h_sdmmc0", "g_h_sdio",
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"g_h_emmc", "g_h_otg0";
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rockchip,suspend-clkgating-setting=<0x80 0x80>;
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#clock-cells = <1>;
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};
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@@ -1372,6 +1381,7 @@
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"g_h_vio_bus", "g_a_vio0";
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rockchip,suspend-clkgating-setting=<0x0 0x0>;
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#clock-cells = <1>;
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};
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@@ -1402,6 +1412,7 @@
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"g_p_spi0", "g_p_spi1",
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"g_p_saradc", "g_p_wdt";
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rockchip,suspend-clkgating-setting=<0x0 0x0>;
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#clock-cells = <1>;
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};
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@@ -1431,6 +1442,7 @@
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"g_p_gpio1", "g_p_gpio2",
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"g_p_gpio3", "g_a_gps";
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rockchip,suspend-clkgating-setting=<0x200 0x200>;
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#clock-cells = <1>;
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};
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@@ -1450,6 +1462,7 @@
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"g_clk_l2c", "g_a_vio1",
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"g_p_ddrpubl", "g_a_gpu";
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rockchip,suspend-clkgating-setting=<0x50 0x50>;
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#clock-cells = <1>;
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};
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@@ -2,6 +2,7 @@
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#include "skeleton.dtsi"
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#include "rk3188-pinctrl.dtsi"
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#include <dt-bindings/rkfb/rk_fb.h>
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#include <dt-bindings/suspend/rockchip-pm.h>
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#include "rk3188_io_vol_domain.dtsi"
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#include <dt-bindings/sensor-dev.h>
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@@ -441,7 +442,25 @@
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<&clk_gpu 200000000>, <&aclk_lcdc0 300000000>,
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<&aclk_lcdc1 300000000>;
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};
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rkpm_suspend {
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compatible = "rockchip,rkpm_suspend";
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// define value is in dt-bindint/suspend/rockchip-pm.h
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rockchip,ctrbits = <
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(
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RKPM_CTR_PWR_DMNS
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|RKPM_CTR_GTCLKS
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|RKPM_CTR_PLLS
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|RKPM_CTR_SYSCLK_DIV
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|RKPM_CTR_NORIDLE_MD
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)
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>;
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rockchip,pmic-gpios=<
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RKPM_GPIOS_SETTING(GPIO0_A0,RKPM_GPIOS_OUTPUT,RKPM_GPIOS_OUT_H)
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RKPM_GPIOS_SETTING(GPIO0_A1,RKPM_GPIOS_OUTPUT,RKPM_GPIOS_OUT_H)
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>;
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};
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fb: fb{
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compatible = "rockchip,rk-fb";
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rockchip,disp-mode = <DUAL>;
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652
arch/arm/mach-rockchip/pm-rk3188.c
Executable file
652
arch/arm/mach-rockchip/pm-rk3188.c
Executable file
@@ -0,0 +1,652 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/suspend.h>
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#include <linux/of.h>
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#include <asm/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/rockchip/cpu.h>
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//#include <linux/rockchip/cru.h>
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#include <linux/rockchip/grf.h>
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#include <linux/rockchip/iomap.h>
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#include "pm.h"
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#define CPU 3188
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#include "sram.h"
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#include "pm-pie.c"
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#define PM_ERR(fmt, args...) printk(KERN_ERR fmt, ##args)
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#define PM_LOG(fmt, args...) printk(KERN_ERR fmt, ##args)
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#define PM_WARNING(fmt, args...) printk(KERN_WARNING fmt, ##args)
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#define cru_readl(offset) readl_relaxed(RK_CRU_VIRT + offset)
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#define cru_writel(v, offset) do { writel_relaxed(v, RK_CRU_VIRT + offset); dsb(); } while (0)
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#define pmu_readl(offset) readl_relaxed(RK_PMU_VIRT + offset)
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#define pmu_writel(v,offset) do { writel_relaxed(v, RK_PMU_VIRT + offset); dsb(); } while (0)
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#define grf_readl(offset) readl_relaxed(RK_GRF_VIRT + offset)
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#define grf_writel(v, offset) do { writel_relaxed(v, RK_GRF_VIRT + offset); dsb(); } while (0)
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#define reg_readl(base) readl_relaxed(base)
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#define reg_writel(v, base) do { writel_relaxed(v, base); dsb(); } while (0)
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#define RK3188_CLK_GATING_OPS(ID) cru_writel((0x1<<((ID%16)+16))|(0x1<<(ID%16)),RK3188_CLK_GATEID_TO_CON(ID))
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#define RK3188_CLK_UNGATING_OPS(ID) cru_writel(0x1<<((ID%16)+16),RK3188_CLK_GATEID_TO_CON(ID))
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/*************************cru define********************************************/
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/*******************CRU BITS*******************************/
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#define CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16))
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#define CRU_SET_BITS(val, bits_shift, msk) (((val)&(msk)) << (bits_shift))
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#define CRU_W_MSK_SETBITS(val, bits_shift,msk) \
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(CRU_W_MSK(bits_shift, msk) | CRU_SET_BITS(val, bits_shift, msk))
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#define RK3188_CRU_GET_REG_BITS_VAL(reg,bits_shift, msk) (((reg) >> (bits_shift))&(msk))
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#define RK3188_CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16))
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#define RK3188_CRU_SET_BITS(val,bits_shift, msk) (((val)&(msk)) << (bits_shift))
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#define RK3188_CRU_W_MSK_SETBITS(val,bits_shift,msk) \
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(RK3188_CRU_W_MSK(bits_shift, msk)|RK3188_CRU_SET_BITS(val,bits_shift, msk))
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/*******************RK3188_PLL CON3 BITS***************************/
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#define RK3188_PLL_PWR_DN_MSK (1 << 1)
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#define RK3188_PLL_PWR_DN_W_MSK (RK3188_PLL_PWR_DN_MSK << 16)
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#define RK3188_PLL_PWR_DN (1 << 1)
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#define RK3188_PLL_PWR_ON (0 << 1)
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/*******************CLKSEL0 BITS***************************/
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//RK3188_CORE_preiph div
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#define RK3188_CORE_PERIPH_W_MSK (3 << 22)
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#define RK3188_CORE_PERIPH_MSK (3 << 6)
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#define RK3188_CORE_PERIPH_2 (0 << 6)
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#define RK3188_CORE_PERIPH_4 (1 << 6)
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#define RK3188_CORE_PERIPH_8 (2 << 6)
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#define RK3188_CORE_PERIPH_16 (3 << 6)
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//clk_RK3188_CORE
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#define RK3188_CORE_SEL_PLL_MSK (1 << 8)
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#define RK3188_CORE_SEL_PLL_W_MSK (1 << 24)
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#define RK3188_CORE_SEL_APLL (0 << 8)
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#define RK3188_CORE_SEL_GPLL (1 << 8)
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#define RK3188_CORE_CLK_DIV_W_MSK (0x1F << 25)
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#define RK3188_CORE_CLK_DIV_MSK (0x1F << 9)
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#define RK3188_CORE_CLK_DIV(i) ((((i) - 1) & 0x1F) << 9)
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#define RK3188_CORE_CLK_MAX_DIV 32
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#define RK3188_CPU_SEL_PLL_MSK (1 << 5)
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#define RK3188_CPU_SEL_PLL_W_MSK (1 << 21)
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#define RK3188_CPU_SEL_APLL (0 << 5)
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#define RK3188_CPU_SEL_GPLL (1 << 5)
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#define RK3188_CPU_CLK_DIV_W_MSK (0x1F << 16)
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#define RK3188_CPU_CLK_DIV_MSK (0x1F)
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#define RK3188_CPU_CLK_DIV(i) (((i) - 1) & 0x1F)
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/*******************CLKSEL1 BITS***************************/
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//aclk div
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#define RK3188_GET_CORE_ACLK_VAL(reg) ((reg)>=4 ?8:((reg)+1))
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#define RK3188_CORE_ACLK_W_MSK (7 << 19)
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#define RK3188_CORE_ACLK_MSK (7 << 3)
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#define RK3188_CORE_ACLK_11 (0 << 3)
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#define RK3188_CORE_ACLK_21 (1 << 3)
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#define RK3188_CORE_ACLK_31 (2 << 3)
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#define RK3188_CORE_ACLK_41 (3 << 3)
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#define RK3188_CORE_ACLK_81 (4 << 3)
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//hclk div
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#define RK3188_ACLK_HCLK_W_MSK (3 << 24)
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#define RK3188_ACLK_HCLK_MSK (3 << 8)
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#define RK3188_ACLK_HCLK_11 (0 << 8)
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#define RK3188_ACLK_HCLK_21 (1 << 8)
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#define RK3188_ACLK_HCLK_41 (2 << 8)
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// pclk div
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#define RK3188_ACLK_PCLK_W_MSK (3 << 28)
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#define RK3188_ACLK_PCLK_MSK (3 << 12)
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#define RK3188_ACLK_PCLK_11 (0 << 12)
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#define RK3188_ACLK_PCLK_21 (1 << 12)
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#define RK3188_ACLK_PCLK_41 (2 << 12)
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#define RK3188_ACLK_PCLK_81 (3 << 12)
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// ahb2apb div
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#define RK3188_AHB2APB_W_MSK (3 << 30)
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#define RK3188_AHB2APB_MSK (3 << 14)
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#define RK3188_AHB2APB_11 (0 << 14)
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#define RK3188_AHB2APB_21 (1 << 14)
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#define RK3188_AHB2APB_41 (2 << 14)
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/*******************clksel10***************************/
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#define RK3188_PERI_ACLK_DIV_MASK 0x1f
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#define RK3188_PERI_ACLK_DIV_W_MSK (RK3188_PERI_ACLK_DIV_MASK << 16)
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#define RK3188_PERI_ACLK_DIV(i) (((i) - 1) & RK3188_PERI_ACLK_DIV_MASK)
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#define RK3188_PERI_ACLK_DIV_OFF 0
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#define RK3188_PERI_HCLK_DIV_MASK 0x3
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#define RK3188_PERI_HCLK_DIV_OFF 8
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#define RK3188_PERI_PCLK_DIV_MASK 0x3
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#define RK3188_PERI_PCLK_DIV_OFF 12
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/*************************gate id**************************************/
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#define RK3188_CLK_GATEID(i) (16 * (i))
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#define RK3188_CLK_GATEID_TO_CON(ID) RK3188_CRU_CLKGATES_CON((ID)/16)
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enum cru_clk_gate {
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/* SCU CLK GATE 0 CON */
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RK3188_CLKGATE_CORE_PERIPH = RK3188_CLK_GATEID(0),
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RK3188_CLKGATE_TIMER0 = RK3188_CLK_GATEID(1),
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RK3188_CLKGATE_UART0_SRC=RK3188_CLK_GATEID(1)+8,
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RK3188_CLKGATE_UART0_FRAC_SRC,
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RK3188_CLKGATE_PCLK_UART0 = RK3188_CLK_GATEID(8),
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RK3188_CLKGATE_CLK_CORE_DBG = RK3188_CLK_GATEID(9),
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RK3188_CLKGATE_MAX= RK3188_CLK_GATEID(10),
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};
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/*******************************gpio define **********************************************/
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#define GPIO_INTEN 0x30
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#define GPIO_INTMASK 0x34
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#define GPIO_INTTYPE_LEVEL 0x38
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#define GPIO_INT_POLARITY 0x3c
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#define GPIO_INT_STATUS 0x40
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/*******************************common code for rkxxx*********************************/
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static void inline uart_printch(char byte)
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{
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u32 reg_save[2];
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u32 u_clk_id=(RK3188_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART);
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u32 u_pclk_id=(RK3188_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
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reg_save[0]=cru_readl(RK3188_CLK_GATEID_TO_CON(u_clk_id));
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reg_save[1]=cru_readl(RK3188_CLK_GATEID_TO_CON(u_pclk_id));
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RK3188_CLK_UNGATING_OPS(u_clk_id);
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RK3188_CLK_UNGATING_OPS(u_pclk_id);
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rkpm_udelay(1);
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writel_relaxed(byte, RK_DEBUG_UART_VIRT);
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dsb();
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/* loop check LSR[6], Transmitter Empty bit */
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while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
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barrier();
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cru_writel(reg_save[0]|0x1<<((u_pclk_id%16)+16),RK3188_CLK_GATEID_TO_CON(u_clk_id));
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cru_writel(reg_save[1]|0x1<<((u_pclk_id%16)+16),RK3188_CLK_GATEID_TO_CON(u_pclk_id));
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if (byte == '\n')
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uart_printch('\r');
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}
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void PIE_FUNC(sram_printch)(char byte)
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{
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uart_printch(byte);
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}
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static void ddr_printch(char byte)
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{
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uart_printch(byte);
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}
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/*******************************clk gating config*******************************************/
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#define CLK_MSK_GATING(msk, con) cru_writel((msk << 16) | 0xffff, con)
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#define CLK_MSK_UNGATING(msk, con) cru_writel(((~msk) << 16) | 0xffff, con)
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static u32 clk_ungt_msk[RK3188_CRU_CLKGATES_CON_CNT];// first clk gating setting
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static u32 clk_ungt_save[RK3188_CRU_CLKGATES_CON_CNT]; //first clk gating value saveing
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u32 DEFINE_PIE_DATA(rkpm_clkgt_last_set[RK3188_CRU_CLKGATES_CON_CNT]);
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static u32 *p_rkpm_clkgt_last_set;
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u32 DEFINE_PIE_DATA(rkpm_clkgt_last_save[RK3188_CRU_CLKGATES_CON_CNT]);
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static u32 *p_rkpm_clkgt_last_save;
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void PIE_FUNC(gtclks_sram_suspend)(void)
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{
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int i;
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// u32 u_clk_id=(RK3188_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART);
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// u32 u_pclk_id=(RK3188_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
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for(i=0;i<RK3188_CRU_CLKGATES_CON_CNT;i++)
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{
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DATA(rkpm_clkgt_last_save[i])=cru_readl(RK3188_CRU_CLKGATES_CON(i));
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CLK_MSK_UNGATING( DATA(rkpm_clkgt_last_set[i]), RK3188_CRU_CLKGATES_CON(i));
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#if 0
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rkpm_sram_printch('\n');
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rkpm_sram_printhex(DATA(rkpm_clkgt_last_save[i]));
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rkpm_sram_printch('-');
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rkpm_sram_printhex(DATA(rkpm_clkgt_last_set[i]));
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rkpm_sram_printch('-');
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rkpm_sram_printhex(cru_readl(RK3188_CRU_CLKGATES_CON(i)));
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if(i==(RK3188_CRU_CLKGATES_CON_CNT-1))
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rkpm_sram_printch('\n');
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#endif
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}
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//RK3188_CLK_UNGATING_OPS(u_clk_id);
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//RK3188_CLK_UNGATING_OPS(u_pclk_id);
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}
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void PIE_FUNC(gtclks_sram_resume)(void)
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||||
{
|
||||
int i;
|
||||
for(i=0;i<RK3188_CRU_CLKGATES_CON_CNT;i++)
|
||||
{
|
||||
cru_writel(DATA(rkpm_clkgt_last_save[i])|0xffff0000, RK3188_CRU_CLKGATES_CON(i));
|
||||
}
|
||||
}
|
||||
|
||||
static void gtclks_suspend(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for(i=0;i<RK3188_CRU_CLKGATES_CON_CNT;i++)
|
||||
{
|
||||
|
||||
clk_ungt_save[i]=cru_readl(RK3188_CRU_CLKGATES_CON(i));
|
||||
//if(i!=4||i!=0)
|
||||
CLK_MSK_UNGATING(clk_ungt_msk[i],RK3188_CRU_CLKGATES_CON(i));
|
||||
#if 0
|
||||
rkpm_ddr_printch('\n');
|
||||
rkpm_ddr_printhex(clk_ungt_save[i]);
|
||||
rkpm_ddr_printch('-');
|
||||
rkpm_ddr_printhex(clk_ungt_msk[i]);
|
||||
rkpm_ddr_printch('-');
|
||||
rkpm_ddr_printhex(cru_readl(RK3188_CRU_CLKGATES_CON(i))) ;
|
||||
if(i==(RK3188_CRU_CLKGATES_CON_CNT-1))
|
||||
rkpm_ddr_printch('\n');
|
||||
#endif
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static void gtclks_resume(void)
|
||||
{
|
||||
int i;
|
||||
for(i=0;i<RK3188_CRU_CLKGATES_CON_CNT;i++)
|
||||
{
|
||||
cru_writel(clk_ungt_save[i]|0xffff0000,RK3188_CRU_CLKGATES_CON(i));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/********************************pll power down***************************************/
|
||||
|
||||
#define power_off_pll(id) \
|
||||
cru_writel(RK3188_PLL_PWR_DN_W_MSK | RK3188_PLL_PWR_DN, RK3188_PLL_CONS((id), 3))
|
||||
|
||||
static void pm_pll_wait_lock(u32 pll_idx)
|
||||
{
|
||||
u32 pll_state[4] = { 1, 0, 2, 3 };
|
||||
u32 bit = 0x20u << pll_state[pll_idx];
|
||||
u32 delay = pll_idx == RK3188_APLL_ID ? 600000U : 30000000U;
|
||||
dsb();
|
||||
dsb();
|
||||
dsb();
|
||||
dsb();
|
||||
dsb();
|
||||
dsb();
|
||||
while (delay > 0) {
|
||||
if (grf_readl(RK3188_GRF_SOC_STATUS0) & bit)
|
||||
break;
|
||||
delay--;
|
||||
}
|
||||
if (delay == 0) {
|
||||
//CRU_PRINTK_ERR("wait pll bit 0x%x time out!\n", bit);
|
||||
rkpm_ddr_printch('p');
|
||||
rkpm_ddr_printch('l');
|
||||
rkpm_ddr_printch('l');
|
||||
rkpm_ddr_printhex(pll_idx);
|
||||
rkpm_ddr_printch('\n');
|
||||
}
|
||||
}
|
||||
static void power_on_pll(u32 pll_id)
|
||||
{
|
||||
cru_writel(RK3188_PLL_PWR_DN_W_MSK | RK3188_PLL_PWR_ON, RK3188_PLL_CONS((pll_id), 3));
|
||||
pm_pll_wait_lock((pll_id));
|
||||
}
|
||||
|
||||
static u32 clk_sel0, clk_sel1, clk_sel10;
|
||||
static u32 cpll_con3;
|
||||
static u32 cru_mode_con;
|
||||
|
||||
void plls_suspend(void)
|
||||
{
|
||||
cru_mode_con = cru_readl(RK3188_CRU_MODE_CON);
|
||||
cru_writel(RK3188_PLL_MODE_SLOW(RK3188_CPLL_ID), RK3188_CRU_MODE_CON);
|
||||
|
||||
cpll_con3 = cru_readl(RK3188_PLL_CONS(RK3188_CPLL_ID, 3));
|
||||
power_off_pll(RK3188_CPLL_ID);
|
||||
|
||||
|
||||
//apll
|
||||
clk_sel0 = cru_readl(RK3188_CRU_CLKSELS_CON(0));
|
||||
clk_sel1 = cru_readl(RK3188_CRU_CLKSELS_CON(1));
|
||||
|
||||
cru_writel(RK3188_PLL_MODE_SLOW(RK3188_APLL_ID), RK3188_CRU_MODE_CON);
|
||||
|
||||
/* To make sure aclk_cpu select apll before div effect */
|
||||
cru_writel(RK3188_CPU_SEL_PLL_W_MSK | RK3188_CPU_SEL_APLL
|
||||
| RK3188_CORE_SEL_PLL_W_MSK | RK3188_CORE_SEL_APLL
|
||||
, RK3188_CRU_CLKSELS_CON(0));
|
||||
cru_writel(RK3188_CORE_PERIPH_W_MSK | RK3188_CORE_PERIPH_2
|
||||
| RK3188_CORE_CLK_DIV_W_MSK | RK3188_CORE_CLK_DIV(1)
|
||||
| RK3188_CPU_CLK_DIV_W_MSK | RK3188_CPU_CLK_DIV(1)
|
||||
, RK3188_CRU_CLKSELS_CON(0));
|
||||
cru_writel(RK3188_CORE_ACLK_W_MSK | RK3188_CORE_ACLK_11
|
||||
| RK3188_ACLK_HCLK_W_MSK | RK3188_ACLK_HCLK_11
|
||||
| RK3188_ACLK_PCLK_W_MSK | RK3188_ACLK_PCLK_11
|
||||
| RK3188_AHB2APB_W_MSK | RK3188_AHB2APB_11
|
||||
, RK3188_CRU_CLKSELS_CON(1));
|
||||
power_off_pll(RK3188_APLL_ID);
|
||||
cru_writel(RK3188_PLL_MODE_SLOW(RK3188_GPLL_ID), RK3188_CRU_MODE_CON);
|
||||
|
||||
|
||||
clk_sel10 = cru_readl(RK3188_CRU_CLKSELS_CON(10));
|
||||
cru_writel(RK3188_CRU_W_MSK_SETBITS(0, RK3188_PERI_ACLK_DIV_OFF, RK3188_PERI_ACLK_DIV_MASK)
|
||||
| RK3188_CRU_W_MSK_SETBITS(0,RK3188_PERI_HCLK_DIV_OFF, RK3188_PERI_HCLK_DIV_MASK)
|
||||
| RK3188_CRU_W_MSK_SETBITS(0, RK3188_PERI_PCLK_DIV_OFF, RK3188_PERI_PCLK_DIV_MASK)
|
||||
, RK3188_CRU_CLKSELS_CON(10));
|
||||
|
||||
power_off_pll(RK3188_GPLL_ID);
|
||||
|
||||
}
|
||||
|
||||
void plls_resume(void)
|
||||
{
|
||||
//gpll
|
||||
|
||||
cru_writel(0xffff0000 | clk_sel10, RK3188_CRU_CLKSELS_CON(10));
|
||||
|
||||
power_on_pll(RK3188_GPLL_ID);
|
||||
cru_writel((RK3188_PLL_MODE_MSK(RK3188_GPLL_ID) << 16)
|
||||
| (RK3188_PLL_MODE_MSK(RK3188_GPLL_ID) & cru_mode_con)
|
||||
, RK3188_CRU_MODE_CON);
|
||||
|
||||
//apll
|
||||
cru_writel(0xffff0000 | clk_sel1, RK3188_CRU_CLKSELS_CON(1));
|
||||
/* To make sure aclk_cpu select gpll after div effect */
|
||||
cru_writel((0xffff0000 & ~RK3188_CPU_SEL_PLL_W_MSK & ~RK3188_CORE_SEL_PLL_W_MSK)
|
||||
| clk_sel0
|
||||
, RK3188_CRU_CLKSELS_CON(0));
|
||||
|
||||
cru_writel(RK3188_CPU_SEL_PLL_W_MSK
|
||||
| RK3188_CORE_SEL_PLL_W_MSK
|
||||
| clk_sel0
|
||||
, RK3188_CRU_CLKSELS_CON(0));
|
||||
|
||||
power_on_pll(RK3188_APLL_ID);
|
||||
cru_writel((RK3188_PLL_MODE_MSK(RK3188_APLL_ID) << 16)
|
||||
| (RK3188_PLL_MODE_MSK(RK3188_APLL_ID) & cru_mode_con)
|
||||
, RK3188_CRU_MODE_CON);
|
||||
|
||||
|
||||
// it was power off ,don't need to power up
|
||||
if (((cpll_con3 & RK3188_PLL_PWR_DN_MSK) == RK3188_PLL_PWR_ON)
|
||||
&&((RK3188_PLL_MODE_NORM(RK3188_CPLL_ID) & RK3188_PLL_MODE_MSK(RK3188_CPLL_ID))
|
||||
== (cru_mode_con & RK3188_PLL_MODE_MSK(RK3188_CPLL_ID)))) {
|
||||
power_on_pll(RK3188_CPLL_ID);
|
||||
}
|
||||
cru_writel((RK3188_PLL_MODE_MSK(RK3188_CPLL_ID) << 16)
|
||||
| (RK3188_PLL_MODE_MSK(RK3188_CPLL_ID) & cru_mode_con)
|
||||
, RK3188_CRU_MODE_CON);
|
||||
}
|
||||
|
||||
u32 DEFINE_PIE_DATA(sysclk_cru_clksel0_con);
|
||||
u32 DEFINE_PIE_DATA(sysclk_cru_clksel10_con);
|
||||
u32 DEFINE_PIE_DATA(sysclk_cru_mode_con);
|
||||
|
||||
void PIE_FUNC(sysclk_suspend)(u32 sel_clk)
|
||||
{
|
||||
DATA(sysclk_cru_clksel0_con) = cru_readl(RK3188_CRU_CLKSELS_CON(0));
|
||||
if(sel_clk&(RKPM_CTR_SYSCLK_32K))
|
||||
{
|
||||
DATA(sysclk_cru_mode_con) = cru_readl(RK3188_CRU_MODE_CON);
|
||||
DATA(sysclk_cru_clksel10_con) = cru_readl(RK3188_CRU_CLKSELS_CON(10));
|
||||
|
||||
cru_writel(RK3188_PERI_ACLK_DIV_W_MSK | RK3188_PERI_ACLK_DIV(4), RK3188_CRU_CLKSELS_CON(10));
|
||||
cru_writel(RK3188_CORE_CLK_DIV_W_MSK | RK3188_CORE_CLK_DIV(4)
|
||||
| RK3188_CPU_CLK_DIV_W_MSK | RK3188_CPU_CLK_DIV(4)
|
||||
, RK3188_CRU_CLKSELS_CON(0));
|
||||
|
||||
cru_writel(0
|
||||
| RK3188_PLL_MODE_DEEP(RK3188_APLL_ID)
|
||||
//| RK3188_PLL_MODE_DEEP(RK3188_DPLL_ID)
|
||||
| RK3188_PLL_MODE_DEEP(RK3188_CPLL_ID)
|
||||
| RK3188_PLL_MODE_DEEP(RK3188_GPLL_ID)
|
||||
, RK3188_CRU_MODE_CON);
|
||||
rkpm_sram_printch('8');
|
||||
}
|
||||
else if(sel_clk&(RKPM_CTR_SYSCLK_DIV))
|
||||
{
|
||||
//set core_clk_div and cpu_clk_div to the largest
|
||||
cru_writel(RK3188_CORE_CLK_DIV_W_MSK | RK3188_CORE_CLK_DIV_MSK
|
||||
| RK3188_CPU_CLK_DIV_W_MSK | RK3188_CPU_CLK_DIV_MSK, RK3188_CRU_CLKSELS_CON(0));
|
||||
}
|
||||
}
|
||||
|
||||
void PIE_FUNC(sysclk_resume)(u32 sel_clk)
|
||||
{
|
||||
|
||||
if(sel_clk&(RKPM_CTR_SYSCLK_32K))
|
||||
{
|
||||
cru_writel((0xffff<<16) | DATA(sysclk_cru_mode_con), RK3188_CRU_MODE_CON);
|
||||
cru_writel(RK3188_CORE_CLK_DIV_W_MSK | RK3188_CPU_CLK_DIV_W_MSK
|
||||
| DATA(sysclk_cru_clksel0_con), RK3188_CRU_CLKSELS_CON(0));
|
||||
cru_writel(RK3188_PERI_ACLK_DIV_W_MSK | DATA(sysclk_cru_clksel10_con),
|
||||
RK3188_CRU_CLKSELS_CON(10));
|
||||
|
||||
rkpm_sram_printch('8');
|
||||
}
|
||||
else if(sel_clk&(RKPM_CTR_SYSCLK_DIV))
|
||||
{
|
||||
cru_writel(RK3188_CORE_CLK_DIV_W_MSK | RK3188_CPU_CLK_DIV_W_MSK
|
||||
| DATA(sysclk_cru_clksel0_con), RK3188_CRU_CLKSELS_CON(0));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void clks_gating_suspend_init(void)
|
||||
{
|
||||
// get clk gating info
|
||||
p_rkpm_clkgt_last_set= kern_to_pie(rockchip_pie_chunk, &DATA(rkpm_clkgt_last_set[0]));
|
||||
p_rkpm_clkgt_last_save= kern_to_pie(rockchip_pie_chunk, &DATA(rkpm_clkgt_last_save[0]));
|
||||
|
||||
if(clk_suspend_clkgt_info_get(clk_ungt_msk,p_rkpm_clkgt_last_set, RK3188_CRU_CLKGATES_CON_CNT)
|
||||
==RK3188_CRU_CLKGATES_CON(0))
|
||||
{
|
||||
rkpm_set_ops_gtclks(gtclks_suspend,gtclks_resume);
|
||||
rkpm_set_sram_ops_gtclks(fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_suspend)),
|
||||
fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_resume)));
|
||||
|
||||
PM_LOG("%s:clkgt info ok\n",__FUNCTION__);
|
||||
|
||||
}
|
||||
rkpm_set_sram_ops_sysclk(fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_suspend))
|
||||
,fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_resume)));
|
||||
}
|
||||
|
||||
/***************************prepare and finish reg_pread***********************************/
|
||||
|
||||
static noinline void rk30_pm_dump_irq(void)
|
||||
{
|
||||
#if 0
|
||||
u32 irq_gpio = (readl_relaxed(RK30_GICD_BASE + GIC_DIST_PENDING_SET + 8) >> 22) & 0x7F;
|
||||
printk("wakeup irq: %08x %08x %08x %08x\n",
|
||||
readl_relaxed(RK30_GICD_BASE + GIC_DIST_PENDING_SET + 4),
|
||||
readl_relaxed(RK30_GICD_BASE + GIC_DIST_PENDING_SET + 8),
|
||||
readl_relaxed(RK30_GICD_BASE + GIC_DIST_PENDING_SET + 12),
|
||||
readl_relaxed(RK30_GICD_BASE + GIC_DIST_PENDING_SET + 16));
|
||||
DUMP_GPIO_INT_STATUS(0);
|
||||
DUMP_GPIO_INT_STATUS(1);
|
||||
DUMP_GPIO_INT_STATUS(2);
|
||||
DUMP_GPIO_INT_STATUS(3);
|
||||
#if GPIO_BANKS > 4
|
||||
DUMP_GPIO_INT_STATUS(4);
|
||||
#endif
|
||||
#if GPIO_BANKS > 5
|
||||
DUMP_GPIO_INT_STATUS(6);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#define DUMP_GPIO_INTEN(ID) \
|
||||
do { \
|
||||
u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN); \
|
||||
if (en) { \
|
||||
rkpm_ddr_printascii("GPIO" #ID "_INTEN: "); \
|
||||
rkpm_ddr_printhex(en); \
|
||||
rkpm_ddr_printch('\n'); \
|
||||
printk(KERN_DEBUG "GPIO%d_INTEN: %08x\n", ID, en); \
|
||||
} \
|
||||
} while (0)
|
||||
static noinline void rk30_pm_dump_inten(void)
|
||||
{
|
||||
DUMP_GPIO_INTEN(0);
|
||||
DUMP_GPIO_INTEN(1);
|
||||
DUMP_GPIO_INTEN(2);
|
||||
DUMP_GPIO_INTEN(3);
|
||||
}
|
||||
|
||||
|
||||
static void rkpm_prepare(void)
|
||||
{
|
||||
#if 1
|
||||
u32 temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
|
||||
|
||||
// rkpm_ddr_printhex(temp);
|
||||
reg_writel(temp|0x1<<4,RK_GPIO_VIRT(0)+0x30);
|
||||
temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
|
||||
// rkpm_ddr_printhex(temp);
|
||||
#endif
|
||||
|
||||
// dump GPIO INTEN for debug
|
||||
rk30_pm_dump_inten();
|
||||
#ifdef CONFIG_DDR_TEST
|
||||
// memory tester
|
||||
ddr_testmode();
|
||||
#endif
|
||||
}
|
||||
|
||||
static void rkpm_finish(void)
|
||||
{
|
||||
rk30_pm_dump_irq();
|
||||
}
|
||||
|
||||
|
||||
static void interface_ctr_reg_pread(void)
|
||||
{
|
||||
//u32 addr;
|
||||
flush_cache_all();
|
||||
outer_flush_all();
|
||||
local_flush_tlb_all();
|
||||
#if 0 // do it in ddr suspend
|
||||
for (addr = (u32)SRAM_CODE_OFFSET; addr < (u32)(SRAM_CODE_OFFSET+rockchip_sram_size); addr += PAGE_SIZE)
|
||||
readl_relaxed(addr);
|
||||
#endif
|
||||
readl_relaxed(RK_PMU_VIRT);
|
||||
readl_relaxed(RK_GRF_VIRT);
|
||||
readl_relaxed(RK_DDR_VIRT);
|
||||
readl_relaxed(RK_GPIO_VIRT(0));
|
||||
//readl_relaxed(RK30_I2C1_BASE+SZ_4K);
|
||||
//readl_relaxed(RK_GPIO_VIRT(3));
|
||||
}
|
||||
|
||||
static u32 gpios_data[2];
|
||||
|
||||
|
||||
|
||||
|
||||
static int rk_pm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *parent;
|
||||
u32 pm_ctrbits;
|
||||
|
||||
|
||||
parent=pdev->dev.of_node;
|
||||
|
||||
PM_LOG("%s enter\n",__FUNCTION__);
|
||||
|
||||
if(of_property_read_u32_array(parent,"rockchip,ctrbits",&pm_ctrbits,1))
|
||||
{
|
||||
PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
|
||||
return -1;
|
||||
}
|
||||
PM_LOG("%s: pm_ctrbits =%x\n",__FUNCTION__,pm_ctrbits);
|
||||
|
||||
if(of_property_read_u32_array(parent,"rockchip,pmic-gpios",gpios_data,ARRAY_SIZE(gpios_data)))
|
||||
{
|
||||
PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
rkpm_set_ctrbits(pm_ctrbits);
|
||||
|
||||
rkpm_pie_init();
|
||||
|
||||
clks_gating_suspend_init();
|
||||
rkpm_set_ops_plls(plls_suspend,plls_resume);
|
||||
rkpm_set_ops_prepare_finish(rkpm_prepare,rkpm_finish);
|
||||
rkpm_set_ops_regs_pread(interface_ctr_reg_pread);
|
||||
|
||||
//rkpm_set_sram_ops_ddr(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_suspend))
|
||||
// ,fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_resume)));
|
||||
|
||||
rkpm_set_sram_ops_printch(fn_to_pie(rockchip_pie_chunk, &FUNC(sram_printch)));
|
||||
rkpm_set_ops_printch(ddr_printch);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk_pm_remove(struct platform_device *pdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rk_pm_of_match[] = {
|
||||
{.compatible = "rockchip,rkpm_suspend",},
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct platform_driver rk_pm_platdrv = {
|
||||
.driver = {
|
||||
.name = "rkpm_suspend",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = rk_pm_of_match,
|
||||
},
|
||||
.probe = rk_pm_probe,
|
||||
.remove = rk_pm_remove,
|
||||
};
|
||||
module_platform_driver(rk_pm_platdrv);
|
||||
|
||||
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
|
||||
MODULE_DESCRIPTION("Generic rk pm plat drv");
|
||||
MODULE_LICENSE("GPL");
|
||||
@@ -354,3 +354,7 @@ static int __init rk3188_ddr_init(void)
|
||||
return 0;
|
||||
}
|
||||
arch_initcall_sync(rk3188_ddr_init);
|
||||
|
||||
#include "pm-rk3188.c"
|
||||
|
||||
|
||||
|
||||
@@ -20,6 +20,9 @@
|
||||
|
||||
|
||||
/* GPIO0_A */
|
||||
#define GPIO0_A0 0x0A00
|
||||
#define GPIO0_A1 0x0A10
|
||||
|
||||
/* GPIO0_B */
|
||||
/* GPIO0_C */
|
||||
#define GPIO0_C0 0x0c00
|
||||
|
||||
Reference in New Issue
Block a user