arm64: dts: rockchip: add mipi_dphy_tx1rx1 and modify rkisp1_1 for rk3399

Change-Id: I94d01c6963dc5f2f9b61159df1b13fc0bb32a0f1
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
This commit is contained in:
Hu Kejun
2018-04-24 11:43:06 +08:00
committed by Jianqun Xu
parent 4b354f3e22
commit b9a7b77a8e

View File

@@ -1864,7 +1864,7 @@
reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "isp0_mmu";
clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
@@ -1877,10 +1877,12 @@
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_ISP1>,
<&cru ACLK_ISP1>, <&cru HCLK_ISP1>,
<&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
<&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>,
<&cru PCLK_ISP1_WRAPPER>;
clock-names = "clk_isp",
"aclk_isp", "hclk_isp",
"aclk_isp_wrap", "hclk_isp_wrap";
"aclk_isp_wrap", "hclk_isp_wrap",
"pclk_isp_wrap";
devfreq = <&dmc>;
power-domains = <&power RK3399_PD_ISP1>;
iommus = <&isp1_mmu>;
@@ -1892,7 +1894,7 @@
reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "isp1_mmu";
clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
@@ -2018,6 +2020,20 @@
};
};
mipi_dphy_tx1rx1: mipi-dphy-tx1rx1@0xff968000 {
compatible = "rockchip,rk3399-mipi-dphy";
reg = <0x0 0xff968000 0x0 0x8000>;
clocks = <&cru SCLK_MIPIDPHY_REF>,
<&cru SCLK_DPHY_TX1RX1_CFG>,
<&cru PCLK_VIO_GRF>,
<&cru PCLK_MIPI_DSI1>;
clock-names = "dphy-ref", "dphy-cfg",
"grf", "pclk_mipi_dsi";
rockchip,grf = <&grf>;
power-domains = <&power RK3399_PD_VIO>;
status = "disabled";
};
edp: edp@ff970000 {
compatible = "rockchip,rk3399-edp";
reg = <0x0 0xff970000 0x0 0x8000>;