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pinctrl: rockchip: add support for rv1126

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Change-Id: Icf6b6b1291cbc5a6116451ac6280e497bf59318f
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This commit is contained in:
Jianqun Xu
2019-12-11 17:16:16 +08:00
committed by Tao Huang
parent e7cff239ab
commit b9d2f63157
1 changed files with 325 additions and 7 deletions
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332
drivers/pinctrl/pinctrl-rockchip.c
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@@ -98,6 +98,7 @@ static const struct rockchip_gpio_regs gpio_regs_v2 = {
enum rockchip_pinctrl_type {
PX30,
RV1108,
RV1126,
RK1808,
RK2928,
RK3066B,
@@ -109,6 +110,9 @@ enum rockchip_pinctrl_type {
RK3399,
};
#define RK_GENMASK_VAL(h, l, v) \
(GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
#define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
#define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
@@ -122,6 +126,7 @@ enum rockchip_pinctrl_type {
#define IOMUX_WIDTH_3BIT BIT(4)
#define IOMUX_8WIDTH_2BIT BIT(5)
#define IOMUX_WRITABLE_32BIT BIT(6)
#define IOMUX_L_SOURCE_PMU BIT(7)
/**
* @type: iomux variant using IOMUX_* constants
@@ -260,6 +265,21 @@ struct rockchip_pin_bank {
}, \
}
#define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \
iom3, offset0, offset1, offset2, \
offset3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .type = iom0, .offset = offset0 }, \
{ .type = iom1, .offset = offset1 }, \
{ .type = iom2, .offset = offset2 }, \
{ .type = iom3, .offset = offset3 }, \
}, \
}
#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
{ \
.bank_num = id, \
@@ -789,6 +809,37 @@ static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
},
};
static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
{
.num = 0,
.pin = 20,
.reg = 0x10000,
.bit = 0,
.mask = 0xf
},
{
.num = 0,
.pin = 21,
.reg = 0x10000,
.bit = 4,
.mask = 0xf
},
{
.num = 0,
.pin = 22,
.reg = 0x10000,
.bit = 8,
.mask = 0xf
},
{
.num = 0,
.pin = 23,
.reg = 0x10000,
.bit = 12,
.mask = 0xf
},
};
static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
{
.num = 2,
@@ -1039,6 +1090,103 @@ static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
},
};
static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
MR_TOPGRF(RK_GPIO3, RK_PB0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
MR_TOPGRF(RK_GPIO0, RK_PD4, RK_FUNC_4, 0x10260, RK_GENMASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
MR_TOPGRF(RK_GPIO2, RK_PC7, RK_FUNC_6, 0x10260, RK_GENMASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
MR_TOPGRF(RK_GPIO1, RK_PD0, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
MR_TOPGRF(RK_GPIO2, RK_PB3, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
MR_TOPGRF(RK_GPIO3, RK_PD4, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_1, 0x10264, RK_GENMASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
MR_TOPGRF(RK_GPIO2, RK_PD1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
MR_TOPGRF(RK_GPIO2, RK_PA5, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
MR_TOPGRF(RK_GPIO3, RK_PB0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
MR_TOPGRF(RK_GPIO1, RK_PD0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
MR_TOPGRF(RK_GPIO1, RK_PC6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
MR_TOPGRF(RK_GPIO2, RK_PD5, RK_FUNC_6, 0x10264, RK_GENMASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
MR_TOPGRF(RK_GPIO2, RK_PB7, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
MR_TOPGRF(RK_GPIO3, RK_PA1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
MR_TOPGRF(RK_GPIO3, RK_PA7, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(0, 0, 0)), /* PWM8_M0 */
MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(0, 0, 1)), /* PWM8_M1 */
MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(2, 2, 0)), /* PWM9_M0 */
MR_TOPGRF(RK_GPIO2, RK_PD6, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(2, 2, 1)), /* PWM9_M1 */
MR_TOPGRF(RK_GPIO3, RK_PA6, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(4, 4, 0)), /* PWM10_M0 */
MR_TOPGRF(RK_GPIO2, RK_PD5, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(4, 4, 1)), /* PWM10_M1 */
MR_TOPGRF(RK_GPIO3, RK_PA7, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
MR_TOPGRF(RK_GPIO3, RK_PA1, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_1, 0x10268, RK_GENMASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
MR_TOPGRF(RK_GPIO1, RK_PA7, RK_FUNC_2, 0x10268, RK_GENMASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
MR_TOPGRF(RK_GPIO3, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
MR_TOPGRF(RK_GPIO2, RK_PA0, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(0, 0, 0)), /* PWM0_M0 */
MR_PMUGRF(RK_GPIO2, RK_PB3, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(0, 0, 1)), /* PWM0_M1 */
MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(2, 2, 0)), /* PWM1_M0 */
MR_PMUGRF(RK_GPIO2, RK_PB2, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(2, 2, 1)), /* PWM1_M1 */
MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(4, 4, 0)), /* PWM2_M0 */
MR_PMUGRF(RK_GPIO2, RK_PB1, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(4, 4, 1)), /* PWM2_M1 */
MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
MR_PMUGRF(RK_GPIO2, RK_PB0, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
MR_PMUGRF(RK_GPIO0, RK_PC2, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(8, 8, 0)), /* PWM4_M0 */
MR_PMUGRF(RK_GPIO2, RK_PA7, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(8, 8, 1)), /* PWM4_M1 */
MR_PMUGRF(RK_GPIO0, RK_PC3, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(10, 10, 0)), /* PWM5_M0 */
MR_PMUGRF(RK_GPIO2, RK_PA6, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(10, 10, 1)), /* PWM5_M1 */
MR_PMUGRF(RK_GPIO0, RK_PB2, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(12, 12, 0)), /* PWM6_M0 */
MR_PMUGRF(RK_GPIO2, RK_PD4, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(12, 12, 1)), /* PWM6_M1 */
MR_PMUGRF(RK_GPIO0, RK_PB1, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
MR_PMUGRF(RK_GPIO3, RK_PA0, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
MR_PMUGRF(RK_GPIO0, RK_PB0, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
MR_PMUGRF(RK_GPIO2, RK_PA1, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
MR_PMUGRF(RK_GPIO2, RK_PB2, RK_FUNC_6, 0x0118, RK_GENMASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_2, 0x0118, RK_GENMASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
MR_PMUGRF(RK_GPIO1, RK_PD0, RK_FUNC_5, 0x0118, RK_GENMASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
};
static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
int *reg, u8 *bit, int *mask)
{
@@ -1857,8 +2005,12 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
return RK_FUNC_GPIO;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? info->regmap_pmu : info->regmap_base;
if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
regmap = info->regmap_pmu;
else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
else
regmap = info->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
@@ -1945,8 +2097,12 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
bank->bank_num, pin, mux);
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? info->regmap_pmu : info->regmap_base;
if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
regmap = info->regmap_pmu;
else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
else
regmap = info->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
@@ -2191,6 +2347,115 @@ static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
#define RV1126_PULL_PMU_OFFSET 0x40
#define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
#define RV1126_PULL_PINS_PER_REG 8
#define RV1126_PULL_BITS_PER_PIN 2
#define RV1126_PULL_BANK_STRIDE 16
#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
if (RV1126_GPIO_C4_D7(pin_num)) {
*regmap = info->regmap_base;
*reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
*reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
*bit = pin_num % RV1126_PULL_PINS_PER_REG;
*bit *= RV1126_PULL_BITS_PER_PIN;
return;
}
*regmap = info->regmap_pmu;
*reg = RV1126_PULL_PMU_OFFSET;
} else {
*reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
*regmap = info->regmap_base;
*reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
}
*reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % RV1126_PULL_PINS_PER_REG);
*bit *= RV1126_PULL_BITS_PER_PIN;
}
#define RV1126_DRV_PMU_OFFSET 0x20
#define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
#define RV1126_DRV_BITS_PER_PIN 4
#define RV1126_DRV_PINS_PER_REG 4
#define RV1126_DRV_BANK_STRIDE 32
static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
if (RV1126_GPIO_C4_D7(pin_num)) {
*regmap = info->regmap_base;
*reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
*reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
*reg -= 0x4;
*bit = pin_num % RV1126_DRV_PINS_PER_REG;
*bit *= RV1126_DRV_BITS_PER_PIN;
return;
}
*regmap = info->regmap_pmu;
*reg = RV1126_DRV_PMU_OFFSET;
} else {
*regmap = info->regmap_base;
*reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
*reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
}
*reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
*bit = pin_num % RV1126_DRV_PINS_PER_REG;
*bit *= RV1126_DRV_BITS_PER_PIN;
}
#define RV1126_SCHMITT_PMU_OFFSET 0x60
#define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
#define RV1126_SCHMITT_BANK_STRIDE 16
#define RV1126_SCHMITT_PINS_PER_GRF_REG 8
#define RV1126_SCHMITT_PINS_PER_PMU_REG 8
static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
int pins_per_reg;
if (bank->bank_num == 0) {
if (RV1126_GPIO_C4_D7(pin_num)) {
*regmap = info->regmap_base;
*reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
*reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
*bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
return 0;
}
*regmap = info->regmap_pmu;
*reg = RV1126_SCHMITT_PMU_OFFSET;
pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
} else {
*regmap = info->regmap_base;
*reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
*reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
}
*reg += ((pin_num / pins_per_reg) * 4);
*bit = pin_num % pins_per_reg;
return 0;
}
#define RK1808_PULL_PMU_OFFSET 0x10
#define RK1808_PULL_GRF_OFFSET 0x80
#define RK1808_PULL_PINS_PER_REG 8
@@ -2718,6 +2983,11 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
bank->bank_num, pin_num, strength);
ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
if (ctrl->type == RV1126) {
rmask_bits = RV1126_DRV_BITS_PER_PIN;
ret = strength;
goto config;
}
ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
@@ -2787,6 +3057,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
return -EINVAL;
}
config:
/* enable the write to the equivalent lower bits */
data = ((1 << rmask_bits) - 1) << (bit + 16);
rmask = data | (data >> 16);
@@ -2885,6 +3156,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
break;
case PX30:
case RV1108:
case RV1126:
case RK1808:
case RK3188:
case RK3288:
@@ -3242,6 +3514,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
return pull ? false : true;
case PX30:
case RV1108:
case RV1126:
case RK1808:
case RK3188:
case RK3288:
@@ -4347,12 +4620,13 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
/* preset iomux offset value, set new start value */
if (iom->offset >= 0) {
if (iom->type & IOMUX_SOURCE_PMU)
if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
pmu_offs = iom->offset;
else
grf_offs = iom->offset;
} else { /* set current iomux offset */
iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
(iom->type & IOMUX_L_SOURCE_PMU)) ?
pmu_offs : grf_offs;
}
@@ -4377,7 +4651,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
inc = (iom->type & (IOMUX_WIDTH_4BIT |
IOMUX_WIDTH_3BIT |
IOMUX_8WIDTH_2BIT)) ? 8 : 4;
if (iom->type & IOMUX_SOURCE_PMU)
if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
pmu_offs += inc;
else
grf_offs += inc;
@@ -4666,6 +4940,48 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rv1126_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
0x10010, 0x10018, 0x10020, 0x10028),
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
IOMUX_WIDTH_4BIT, 0, 0, 0),
};
static struct rockchip_pin_ctrl rv1126_pin_ctrl = {
.pin_banks = rv1126_pin_banks,
.nr_banks = ARRAY_SIZE(rv1126_pin_banks),
.label = "RV1126-GPIO",
.type = RV1126,
.grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
.pmu_mux_offset = 0x0,
.iomux_routes = rv1126_mux_route_data,
.niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
.iomux_recalced = rv1126_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
.pull_calc_reg = rv1126_calc_pull_reg_and_bit,
.drv_calc_reg = rv1126_calc_drv_reg_and_bit,
.schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rk1808_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
@@ -5032,6 +5348,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = &px30_pin_ctrl },
{ .compatible = "rockchip,rv1108-pinctrl",
.data = &rv1108_pin_ctrl },
{ .compatible = "rockchip,rv1126-pinctrl",
.data = &rv1126_pin_ctrl },
{ .compatible = "rockchip,rk1808-pinctrl",
.data = &rk1808_pin_ctrl },
{ .compatible = "rockchip,rk2928-pinctrl",