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phy: rockchip: inno-usb2: fix some issues for rk3568 usb2 phy
This patch fixes the following issues for rk3568 usb2 phy. 1. Set utmi opmode to normal mode for rk3568 usb phy when usb phy enter suspend mode via usb phy grf. It can help to avoid the DM/DP floating and the line state be detected as 2'b11. 2. Fix the offset of INT_STATUS_CLR. It can help to avoid triggering the linestate irq constantly. Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com> Change-Id: Iba53e416c44a45baa180ad3abcc91d1d71900158
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@@ -2808,23 +2808,23 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
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.iddig_en = { 0x0000, 9, 9, 0, 1 },
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.idfall_det_en = { 0x0080, 5, 5, 0, 1 },
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.idfall_det_st = { 0x0084, 5, 5, 0, 1 },
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.idfall_det_clr = { 0x008c, 5, 5, 0, 1 },
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.idfall_det_clr = { 0x0088, 5, 5, 0, 1 },
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.idrise_det_en = { 0x0080, 4, 4, 0, 1 },
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.idrise_det_st = { 0x0084, 4, 4, 0, 1 },
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.idrise_det_clr = { 0x008c, 4, 4, 0, 1 },
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.idrise_det_clr = { 0x0088, 4, 4, 0, 1 },
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.ls_det_en = { 0x0080, 0, 0, 0, 1 },
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.ls_det_st = { 0x0084, 0, 0, 0, 1 },
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.ls_det_clr = { 0x008c, 0, 0, 0, 1 },
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.ls_det_clr = { 0x0088, 0, 0, 0, 1 },
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.utmi_avalid = { 0x00c0, 10, 10, 0, 1 },
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.utmi_bvalid = { 0x00c0, 9, 9, 0, 1 },
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.utmi_iddig = { 0x00c0, 6, 6, 0, 1 },
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.utmi_ls = { 0x00c0, 5, 4, 0, 1 },
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},
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[USB2PHY_PORT_HOST] = {
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.phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d5 },
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.phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
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.ls_det_en = { 0x0080, 1, 1, 0, 1 },
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.ls_det_st = { 0x0084, 1, 1, 0, 1 },
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.ls_det_clr = { 0x008c, 1, 1, 0, 1 },
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.ls_det_clr = { 0x0088, 1, 1, 0, 1 },
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.utmi_ls = { 0x00c0, 17, 16, 0, 1 },
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.utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
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}
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@@ -2848,18 +2848,18 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
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.clkout_ctl = { 0x0008, 4, 4, 1, 0 },
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.port_cfgs = {
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[USB2PHY_PORT_OTG] = {
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.phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d5 },
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.phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 },
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.ls_det_en = { 0x0080, 0, 0, 0, 1 },
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.ls_det_st = { 0x0084, 0, 0, 0, 1 },
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.ls_det_clr = { 0x008c, 0, 0, 0, 1 },
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.ls_det_clr = { 0x0088, 0, 0, 0, 1 },
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.utmi_ls = { 0x00c0, 5, 4, 0, 1 },
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.utmi_hstdet = { 0x00c0, 7, 7, 0, 1 }
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},
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[USB2PHY_PORT_HOST] = {
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.phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d5 },
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.phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
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.ls_det_en = { 0x0080, 1, 1, 0, 1 },
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.ls_det_st = { 0x0084, 1, 1, 0, 1 },
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.ls_det_clr = { 0x008c, 1, 1, 0, 1 },
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.ls_det_clr = { 0x0088, 1, 1, 0, 1 },
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.utmi_ls = { 0x00c0, 17, 16, 0, 1 },
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.utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
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}
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