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emmc: Clear the value of txdelay in legacy mode on the resume process [1/1]
PD#SWPL-7181 Problem: switch to high-speed from hs200 failed for resume process. Solution: set tx_delay as 0 for legacy mode. clear cfg_cmd_setup Verify: verify by TL1 Change-Id: I5dbb1bbc391da864464bf137837a2b0f54ccda42 Signed-off-by: Long Yu <long.yu@amlogic.com>
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@@ -1160,7 +1160,7 @@
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tx_delay = <0>;
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max_req_size = <0x20000>; /**128KB*/
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gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>;
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hw_reset = <&gpio BOOT_12 GPIO_ACTIVE_HIGH>;
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hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>;
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card_type = <1>;
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/* 1:mmc card(include eMMC),
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* 2:sd card(include tSD)
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@@ -1141,7 +1141,7 @@
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tx_delay = <0>;
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max_req_size = <0x20000>; /**128KB*/
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gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>;
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hw_reset = <&gpio BOOT_12 GPIO_ACTIVE_HIGH>;
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hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>;
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card_type = <1>;
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/* 1:mmc card(include eMMC),
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* 2:sd card(include tSD)
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@@ -396,6 +396,11 @@ static void aml_sd_emmc_set_timing_v3(struct amlsd_platform *pdata,
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clkc->tx_phase = para->sdr104.tx_phase;
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} else {
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ctrl->ddr = 0;
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clkc->tx_delay = 0;
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clkc->core_phase = para->init.core_phase;
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clkc->tx_phase = para->init.tx_phase;
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irq_en &= ~(1<<17);
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writel(irq_en, host->base + SD_EMMC_IRQ_EN);
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/* timing == MMC_TIMING_LEGACY */
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if (pdata->calc_f) {
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clkc->core_phase = para->calc.core_phase;
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