emmc: Clear the value of txdelay in legacy mode on the resume process [1/1]

PD#SWPL-7181

Problem:
switch to high-speed from hs200 failed for resume process.

Solution:
set tx_delay as 0 for legacy mode.
clear cfg_cmd_setup

Verify:
verify by TL1

Change-Id: I5dbb1bbc391da864464bf137837a2b0f54ccda42
Signed-off-by: Long Yu <long.yu@amlogic.com>
This commit is contained in:
Long Yu
2019-04-15 16:40:25 +08:00
committed by Tao Zeng
parent f962b98214
commit ba089425fd
3 changed files with 7 additions and 2 deletions

View File

@@ -1160,7 +1160,7 @@
tx_delay = <0>;
max_req_size = <0x20000>; /**128KB*/
gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>;
hw_reset = <&gpio BOOT_12 GPIO_ACTIVE_HIGH>;
hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>;
card_type = <1>;
/* 1:mmc card(include eMMC),
* 2:sd card(include tSD)

View File

@@ -1141,7 +1141,7 @@
tx_delay = <0>;
max_req_size = <0x20000>; /**128KB*/
gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>;
hw_reset = <&gpio BOOT_12 GPIO_ACTIVE_HIGH>;
hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>;
card_type = <1>;
/* 1:mmc card(include eMMC),
* 2:sd card(include tSD)

View File

@@ -396,6 +396,11 @@ static void aml_sd_emmc_set_timing_v3(struct amlsd_platform *pdata,
clkc->tx_phase = para->sdr104.tx_phase;
} else {
ctrl->ddr = 0;
clkc->tx_delay = 0;
clkc->core_phase = para->init.core_phase;
clkc->tx_phase = para->init.tx_phase;
irq_en &= ~(1<<17);
writel(irq_en, host->base + SD_EMMC_IRQ_EN);
/* timing == MMC_TIMING_LEGACY */
if (pdata->calc_f) {
clkc->core_phase = para->calc.core_phase;