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https://github.com/hardkernel/linux.git
synced 2026-06-07 19:30:30 +09:00
display transmitter:edp anx9804 anx9805 anx6345 support
This commit is contained in:
yxj
@@ -285,7 +285,7 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y
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# CONFIG_BACKLIGHT_GENERIC is not set
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CONFIG_DISPLAY_SUPPORT=y
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CONFIG_LCD_LP097QX1=y
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CONFIG_DP_RK_EDP=y
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CONFIG_DP_ANX6345=y
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CONFIG_FB_ROCKCHIP=y
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CONFIG_ONE_LCDC_DUAL_OUTPUT_INF=y
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CONFIG_LCDC_RK3066B=y
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@@ -52,9 +52,9 @@
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#include <linux/mfd/rk610_core.h>
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#endif
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#if defined(CONFIG_DP_RK_EDP)
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#include <linux/rk_edp.h>
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#endif
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#if defined(CONFIG_DP_ANX6345)
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#include<linux/anx6345.h>
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#endif
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#if defined(CONFIG_CT36X_TS)
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#include <linux/ct36x.h>
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@@ -734,17 +734,16 @@ static struct platform_device rk29_device_vibrator = {
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};
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#endif
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#ifdef CONFIG_DP_RK_EDP
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#ifdef CONFIG_DP_ANX6345
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#define DVDD33_EN_PIN RK30_PIN0_PB0
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#define DVDD33_EN_VALUE GPIO_LOW
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#define DVDD18_EN_MUX_NAME GPIO1B6_SPDIFTX_SPI1CSN1_NAME
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#define DVDD18_EN_PIN RK30_PIN1_PB6//RK30_PIN4_PC7
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#define DVDD18_EN_VALUE GPIO_HIGH
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#define EDP_RST_PIN RK30_PIN0_PB4
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static rk_edp_power_ctl(void)
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static int rk_edp_power_ctl(void)
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{
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int ret;
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ret = gpio_request(DVDD33_EN_PIN, "dvdd33_en_pin");
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@@ -759,7 +758,6 @@ static struct platform_device rk29_device_vibrator = {
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gpio_direction_output(DVDD33_EN_PIN, DVDD33_EN_VALUE);
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}
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//rk30_mux_api_set(DVDD18_EN_MUX_NAME, GPIO4C_GPIO4C7);
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ret = gpio_request(DVDD18_EN_PIN, "dvdd18_en_pin");
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if (ret != 0)
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{
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@@ -788,13 +786,13 @@ static struct platform_device rk29_device_vibrator = {
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return 0;
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}
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static struct rk_edp_platform_data rk_edp_platform_data = {
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.power_ctl = rk_edp_power_ctl,
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.dvdd33_en_pin = DVDD33_EN_PIN,
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.dvdd33_en_val = DVDD33_EN_VALUE,
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.dvdd18_en_pin = DVDD18_EN_PIN,
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.dvdd18_en_val = DVDD18_EN_VALUE,
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.edp_rst_pin = EDP_RST_PIN,
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static struct anx6345_platform_data anx6345_platform_data = {
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.power_ctl = rk_edp_power_ctl,
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.dvdd33_en_pin = DVDD33_EN_PIN,
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.dvdd33_en_val = DVDD33_EN_VALUE,
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.dvdd18_en_pin = DVDD18_EN_PIN,
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.dvdd18_en_val = DVDD18_EN_VALUE,
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.edp_rst_pin = EDP_RST_PIN,
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};
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#endif
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@@ -1905,15 +1903,16 @@ static struct i2c_board_info __initdata i2c2_info[] = {
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},
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#endif
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#if defined (CONFIG_DP_RK_EDP)
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#if defined (CONFIG_DP_ANX6345)
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{
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.type = "rk_edp",
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.type = "anx6345",
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.addr = 0x39,
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.flags = 0,
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.platform_data = &rk_edp_platform_data,
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.platform_data = &anx6345_platform_data,
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},
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#endif
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#if defined (CONFIG_CT36X_TS)
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{
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.type = CT36X_NAME,
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@@ -16,7 +16,7 @@ config TC358768_RGB2MIPI
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help
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"a chip that change RGB interface parallel signal into DSI serial signal"
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config DP_RK_EDP
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bool "RGB to Display Port transmitter RK_EDP support"
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config DP_ANX6345
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bool "RGB to Display Port transmitter anx6345,anx9804,anx9805 support"
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endchoice
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@@ -3,4 +3,4 @@
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#
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obj-$(CONFIG_RK610_LVDS) += rk610_lcd.o
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obj-$(CONFIG_TC358768_RGB2MIPI) += tc358768.o
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obj-$(CONFIG_DP_RK_EDP) += dp_rk_edp.o
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obj-$(CONFIG_DP_ANX6345) += dp_anx6345.o
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835
drivers/video/display/transmitter/dp_anx6345.c
Executable file
835
drivers/video/display/transmitter/dp_anx6345.c
Executable file
@@ -0,0 +1,835 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/fs.h>
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#include <linux/seq_file.h>
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#include <linux/time.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/i2c.h>
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#include <linux/gpio.h>
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#include <linux/anx6345.h>
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#include <linux/debugfs.h>
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//#define BIST_MODE 0
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static int anx6345_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val)
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{
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int ret;
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client->addr = DP_TX_PORT0_ADDR >> 1;
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ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
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if(ret < 0)
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{
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printk(KERN_ERR "%s>>err\n",__func__);
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}
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return ret;
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}
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static int anx6345_i2c_write_p0_reg(struct i2c_client *client, char reg, char *val)
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{
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int ret;
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client->addr = DP_TX_PORT0_ADDR >> 1;
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ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
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if(ret < 0)
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{
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printk(KERN_ERR "%s>>err\n",__func__);
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}
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return ret;
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}
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static int anx6345_i2c_read_p1_reg(struct i2c_client *client, char reg, char *val)
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{
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int ret;
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client->addr = HDMI_TX_PORT0_ADDR >> 1;
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ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
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if(ret < 0)
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{
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printk(KERN_ERR "%s>>err\n",__func__);
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}
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return ret;
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}
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static int anx6345_i2c_write_p1_reg(struct i2c_client *client, char reg, char *val)
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{
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int ret;
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client->addr = HDMI_TX_PORT0_ADDR >> 1;
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ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
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if(ret < 0)
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{
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printk(KERN_ERR "%s>>err\n",__func__);
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}
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return ret;
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}
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static int edp_reg_show(struct seq_file *s, void *v)
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{
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int i = 0;
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char val;
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struct edp_anx6345 *anx6345 = s->private;
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if(!anx6345)
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{
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printk(KERN_ERR "no edp device!\n");
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return 0;
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}
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seq_printf(s,"0x70:\n");
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for(i=0;i< MAX_REG;i++)
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{
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anx6345_i2c_read_p0_reg(anx6345->client, i , &val);
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seq_printf(s,"0x%02x>>0x%02x\n",i,val);
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}
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seq_printf(s,"\n0x72:\n");
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for(i=0;i< MAX_REG;i++)
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{
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anx6345_i2c_read_p1_reg(anx6345->client, i , &val);
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seq_printf(s,"0x%02x>>0x%02x\n",i,val);
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}
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return 0;
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}
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static int edp_reg_open(struct inode *inode, struct file *file)
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{
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struct edp_anx6345 *anx6345 = inode->i_private;
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return single_open(file, edp_reg_show, anx6345);
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}
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static const struct file_operations edp_reg_fops = {
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.owner = THIS_MODULE,
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.open = edp_reg_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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//get chip ID. Make sure I2C is OK
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static int get_dp_chip_id(struct i2c_client *client)
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{
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char c1,c2;
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int id;
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anx6345_i2c_read_p1_reg(client,SP_TX_DEV_IDL_REG,&c1);
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anx6345_i2c_read_p1_reg(client,SP_TX_DEV_IDH_REG,&c2);
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id = c2;
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return (id<<8)|c1;
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}
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static int anx980x_bist_mode(struct i2c_client *client)
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{
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char val,i;
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u8 cnt=0;
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//Power on total and select DP mode
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val = 00;
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anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val);
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//HW reset
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val = DP_TX_RST_HW_RST;
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anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
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msleep(10);
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val = 0x00;
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anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
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anx6345_i2c_read_p1_reg(client, DP_POWERD_CTRL_REG, &val);
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val = 0x00;
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anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val);
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//get chip ID. Make sure I2C is OK
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anx6345_i2c_read_p1_reg(client, DP_TX_DEV_IDH_REG , &val);
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if (val==0x98)
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printk("Chip found\n");
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//for clocl detect
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for(i=0;i<100;i++)
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{
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anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
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anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
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anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
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if((val&DP_TX_SYS_CTRL1_DET_STA)!=0)
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{
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printk("clock is detected.\n");
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break;
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}
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msleep(10);
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}
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//check whther clock is stable
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for(i=0;i<50;i++)
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{
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anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
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anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
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anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
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if((val&DP_TX_SYS_CTRL2_CHA_STA)==0)
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{
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printk("clock is stable.\n");
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break;
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}
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msleep(10);
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}
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//VESA range, 8bits BPC, RGB
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val = 0x10;
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anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL2_REG, &val);
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//RK_EDP chip analog setting
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val = 0x07;
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anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val);
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val = 0x19;
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anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val);
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val = 0xd9;
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anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val);
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//Select AC mode
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val = 0x40;
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anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
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//RK_EDP chip analog setting
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val = 0xf0;
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anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);
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val = 0x99;
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anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val);
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val = 0x7b;
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anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
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val = 0x30;
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anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val);
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val = 0x06;
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anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL, &val);
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//force HPD
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val = 0x30;
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anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL3_REG, &val);
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//power on 4 lanes
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val = 0x00;
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anx6345_i2c_write_p0_reg(client, 0xc8, &val);
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//lanes setting
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anx6345_i2c_write_p0_reg(client, 0xa3, &val);
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anx6345_i2c_write_p0_reg(client, 0xa4, &val);
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anx6345_i2c_write_p0_reg(client, 0xa5,&val);
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anx6345_i2c_write_p0_reg(client, 0xa6, &val);
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//reset AUX CH
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val = 0x44;
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anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
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val = 0x40;
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anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
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//Select 1.62G
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val = 0x06;
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anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val);
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//Select 4 lanes
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val = 0x04;
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anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val);
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//strart link traing
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//DP_TX_LINK_TRAINING_CTRL_EN is self clear. If link training is OK, it will self cleared.
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#if 1
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val = DP_TX_LINK_TRAINING_CTRL_EN;
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anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
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msleep(5);
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anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
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while((val&0x01)&&(cnt++ < 10))
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{
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printk("Waiting...\n");
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msleep(5);
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anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
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}
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if(cnt >= 10)
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{
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printk(KERN_INFO "HW LT fail\n");
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}
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else
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{
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printk(KERN_INFO "HW LT success ...cnt:%d\n",cnt);
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}
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#else
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DP_TX_HW_LT(client,0x0a,0x04); //2.7Gpbs 4lane
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#endif
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//DP_TX_Write_Reg(0x7a, 0x7c, 0x02);
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//Set bist format 2048x1536
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val = 0x2c;
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anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEL_REG, &val);
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val = 0x06;
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anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEH_REG, &val);
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val = 0x00;
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anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEL_REG, &val);
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val = 0x06;
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anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEH_REG,&val);
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val = 0x02;
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anx6345_i2c_write_p1_reg(client, DP_TX_VF_PORCH_REG, &val);
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val = 0x04;
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anx6345_i2c_write_p1_reg(client, DP_TX_VSYNC_CFG_REG,&val);
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val = 0x26;
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anx6345_i2c_write_p1_reg(client, DP_TX_VB_PORCH_REG, &val);
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val = 0x50;
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anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELL_REG, &val);
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val = 0x04;
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anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELH_REG, &val);
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val = 0x00;
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anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELL_REG, &val);
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val = 0x04;
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anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELH_REG, &val);
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val = 0x18;
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anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHL_REG, &val);
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val = 0x00;
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anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHH_REG, &val);
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val = 0x10;
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anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGL_REG,&val);
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val = 0x00;
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anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGH_REG,&val);
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val = 0x28;
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anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHL_REG, &val);
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val = 0x00;
|
||||
anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHH_REG, &val);
|
||||
val = 0x03;
|
||||
anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL10_REG, &val);
|
||||
|
||||
//enable BIST
|
||||
val = DP_TX_VID_CTRL4_BIST;
|
||||
anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL4_REG, &val);
|
||||
//enable video input
|
||||
val = 0x8d;
|
||||
anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
|
||||
//force HPD and stream valid
|
||||
val = 0x33;
|
||||
anx6345_i2c_write_p0_reg(client, 0x82, &val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int anx980x_aux_rst(struct i2c_client *client)
|
||||
{
|
||||
char val;
|
||||
anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
|
||||
val |= DP_TX_AUX_RST;
|
||||
anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
|
||||
val &= ~DP_TX_AUX_RST;
|
||||
anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int anx980x_wait_aux_finished(struct i2c_client *client)
|
||||
{
|
||||
char val,cnt;
|
||||
cnt = 0;
|
||||
|
||||
anx6345_i2c_read_p0_reg(client,DP_TX_AUX_CTRL_REG2, &val);
|
||||
while(val&0x01)
|
||||
{
|
||||
//delay_ms(20);
|
||||
cnt ++;
|
||||
if(cnt == 10)
|
||||
{
|
||||
printk("aux break");
|
||||
anx980x_aux_rst(client);
|
||||
//cnt = 0;
|
||||
break;
|
||||
}
|
||||
anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int anx980x_aux_dpcdread_bytes(struct i2c_client *client,unsigned long addr, char cCount,char* pBuf)
|
||||
{
|
||||
char val,i;
|
||||
|
||||
val = 0x80;
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_BUF_DATA_COUNT_REG, &val);
|
||||
|
||||
//set read cmd and count
|
||||
val = (((char)(cCount-1) <<4)&(0xf0))|0x09;
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG, &val);
|
||||
|
||||
//set aux address15:0
|
||||
val = (char)addr&0xff;
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_7_0_REG, &val);
|
||||
val = (char)((addr>>8)&0xff);
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_15_8_REG, &val);
|
||||
|
||||
//set address19:16 and enable aux
|
||||
anx6345_i2c_read_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val);
|
||||
val &=(0xf0)|(char)((addr>>16)&0xff);
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val);
|
||||
|
||||
//Enable Aux
|
||||
anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
|
||||
val |= 0x01;
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
|
||||
|
||||
//delay_ms(2);
|
||||
anx980x_wait_aux_finished(client);
|
||||
|
||||
for(i =0;i<cCount;i++)
|
||||
{
|
||||
anx6345_i2c_read_p0_reg(client, DP_TX_BUF_DATA_0_REG+i, &val);
|
||||
|
||||
//debug_printf("c = %.2x\n",(WORD)c);
|
||||
*(pBuf+i) = val;
|
||||
|
||||
if(i >= MAX_BUF_CNT)
|
||||
return 1;
|
||||
//break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
|
||||
}
|
||||
|
||||
static int anx_video_map_config(struct i2c_client *client)
|
||||
{
|
||||
char val = 0;
|
||||
char i = 0;
|
||||
anx6345_i2c_write_p1_reg(client, 0x40, &val);
|
||||
anx6345_i2c_write_p1_reg(client, 0x41, &val);
|
||||
anx6345_i2c_write_p1_reg(client, 0x48, &val);
|
||||
anx6345_i2c_write_p1_reg(client, 0x49, &val);
|
||||
anx6345_i2c_write_p1_reg(client, 0x50, &val);
|
||||
anx6345_i2c_write_p1_reg(client, 0x51, &val);
|
||||
for(i=0; i<6; i++)
|
||||
{
|
||||
val = i;
|
||||
anx6345_i2c_write_p1_reg(client, 0x42+i, &val);
|
||||
}
|
||||
|
||||
for(i=0; i<6; i++)
|
||||
{
|
||||
val = 6+i;
|
||||
anx6345_i2c_write_p1_reg(client, 0x4a+i, &val);
|
||||
}
|
||||
|
||||
for(i=0; i<6; i++)
|
||||
{
|
||||
val = 0x0c+i;
|
||||
anx6345_i2c_write_p1_reg(client, 0x52+i, &val);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
static int anx980x_eanble_video_input(struct i2c_client *client)
|
||||
{
|
||||
char val;
|
||||
|
||||
anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
|
||||
val |= DP_TX_VID_CTRL1_VID_EN;
|
||||
anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
|
||||
|
||||
anx_video_map_config(client);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int anx980x_init(struct i2c_client *client)
|
||||
{
|
||||
char val = 0x00;
|
||||
char safe_mode = 0;
|
||||
char ByteBuf[2];
|
||||
char dp_tx_bw,dp_tx_lane_count;
|
||||
char cnt = 10;
|
||||
|
||||
#if defined(BIST_MODE)
|
||||
return anx980x_bist_mode(client);
|
||||
#endif
|
||||
//power on all block and select DisplayPort mode
|
||||
val |= DP_POWERD_AUDIO_REG;
|
||||
anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val );
|
||||
|
||||
anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
|
||||
val &= ~DP_TX_VID_CTRL1_VID_EN;
|
||||
anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
|
||||
|
||||
//software reset
|
||||
anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
|
||||
val |= DP_TX_RST_SW_RST;
|
||||
anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG,&val);
|
||||
val &= ~DP_TX_RST_SW_RST;
|
||||
anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
|
||||
|
||||
|
||||
val = 0x07;
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val);
|
||||
val = 0x50;
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_EXTRA_ADDR_REG, &val);
|
||||
|
||||
//24bit SDR,negedge latch, and wait video stable
|
||||
val = 0x01;
|
||||
anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);//72:08 for 9804 SDR, neg edge 05/04/09 extra pxl
|
||||
val = 0x19;
|
||||
anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val);
|
||||
val = 0xd9;
|
||||
anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val);
|
||||
|
||||
//serdes ac mode.
|
||||
anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
|
||||
val |= DP_TX_AC_MODE;
|
||||
anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
|
||||
|
||||
//set termination
|
||||
val = 0xf0;
|
||||
anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);
|
||||
//set duty cycle
|
||||
val = 0x99;
|
||||
anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val);
|
||||
|
||||
anx6345_i2c_read_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
|
||||
val |= 0x2a;
|
||||
anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
|
||||
|
||||
//anx6345_i2c_write_p0_reg(client, DP_TX_HDCP_CTRL, 0x01);
|
||||
val = 0x30;
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val);
|
||||
|
||||
//for DP link CTS
|
||||
anx6345_i2c_read_p0_reg(client, DP_TX_GNS_CTRL_REG, &val);
|
||||
val |= 0x40;
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_GNS_CTRL_REG, &val);
|
||||
|
||||
//power down PLL filter
|
||||
val = 0x06;
|
||||
anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL,&val);
|
||||
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE0_SET_REG, &val);
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE1_SET_REG, &val);
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE2_SET_REG, &val);
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE3_SET_REG, &val);
|
||||
|
||||
val = 0x06;
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val);
|
||||
val = 0x04;
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val);
|
||||
|
||||
val = DP_TX_LINK_TRAINING_CTRL_EN;
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG,&val);
|
||||
msleep(2);
|
||||
anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
|
||||
while((val & DP_TX_LINK_TRAINING_CTRL_EN)&&(cnt--))
|
||||
{
|
||||
anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
|
||||
cnt--;
|
||||
}
|
||||
if(cnt < 0)
|
||||
{
|
||||
printk(KERN_INFO "HW LT fail\n");
|
||||
}
|
||||
else
|
||||
printk(KERN_INFO "HW LT Success!>>:times:%d\n",(11-cnt));
|
||||
//DP_TX_Config_Video(client);
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
|
||||
anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
|
||||
if(!(val & DP_TX_SYS_CTRL1_DET_STA))
|
||||
{
|
||||
printk("No pclk\n");
|
||||
//return; //mask by yxj
|
||||
}
|
||||
|
||||
anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
|
||||
anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
|
||||
anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
|
||||
if(val & DP_TX_SYS_CTRL2_CHA_STA)
|
||||
{
|
||||
printk("pclk not stable!\n");
|
||||
//return; mask by yxj
|
||||
}
|
||||
|
||||
anx980x_aux_dpcdread_bytes(client,(unsigned long)0x00001,2,ByteBuf);
|
||||
dp_tx_bw = ByteBuf[0];
|
||||
dp_tx_lane_count = ByteBuf[1] & 0x0f;
|
||||
printk("%s..lc:%d--bw:%d\n",__func__,dp_tx_lane_count,dp_tx_bw);
|
||||
|
||||
if(!safe_mode)
|
||||
{
|
||||
//set Input BPC mode & color space
|
||||
anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL2_REG, &val);
|
||||
val &= 0x8c;
|
||||
val = val |((char)(0) << 4); //8bits ,rgb
|
||||
anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL2_REG, &val);
|
||||
}
|
||||
|
||||
|
||||
|
||||
//enable video input
|
||||
anx980x_eanble_video_input(client);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int anx6345_bist_mode(struct i2c_client *client)
|
||||
{
|
||||
char val = 0x00;
|
||||
//these register are for bist mode
|
||||
val = 0x2c;
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEL_REG,&val);
|
||||
val = 0x06;
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEH_REG,&val);
|
||||
val = 0x00;
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEL_REG,&val);
|
||||
val = 0x06;
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEH_REG,&val);
|
||||
val = 0x02;
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_VF_PORCH_REG,&val);
|
||||
val = 0x04;
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_VSYNC_CFG_REG,&val);
|
||||
val = 0x26;
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_VB_PORCH_REG,&val);
|
||||
val = 0x50;
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELL_REG,&val);
|
||||
val = 0x04;
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELH_REG,&val);
|
||||
val = 0x00;
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELL_REG,&val);
|
||||
val = 0x04;
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELH_REG,&val);
|
||||
val = 0x18;
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHL_REG,&val);
|
||||
val = 0x00;
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHH_REG,&val);
|
||||
val = 0x10;
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGL_REG,&val);
|
||||
val = 0x00;
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGH_REG,&val);
|
||||
val = 0x28;
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_HB_PORCHL_REG,&val);
|
||||
val = 0x13;
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL10_REG,&val);
|
||||
|
||||
|
||||
//enable BIST. In normal mode, don't need to config this reg
|
||||
val = 0x08;
|
||||
anx6345_i2c_write_p1_reg(client, 0x0b, &val);
|
||||
printk("anx6345 enter bist mode\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
static int anx6345_init(struct i2c_client *client)
|
||||
{
|
||||
char val = 0x00;
|
||||
char i = 0;
|
||||
char lc,bw;
|
||||
char cnt = 50;
|
||||
|
||||
val = 0x30;
|
||||
anx6345_i2c_write_p1_reg(client,SP_POWERD_CTRL_REG,&val);
|
||||
|
||||
//clock detect
|
||||
for(i=0;i<50;i++)
|
||||
{
|
||||
|
||||
anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val);
|
||||
anx6345_i2c_write_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val);
|
||||
anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val);
|
||||
if((val&SP_TX_SYS_CTRL1_DET_STA)!=0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
mdelay(10);
|
||||
}
|
||||
if(i>49)
|
||||
printk("no clock detected by anx6345\n");
|
||||
|
||||
//check whether clock is stable
|
||||
for(i=0;i<50;i++)
|
||||
{
|
||||
anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL2_REG, &val);
|
||||
anx6345_i2c_write_p0_reg(client,SP_TX_SYS_CTRL2_REG, &val);
|
||||
anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL2_REG, &val);
|
||||
if((val&SP_TX_SYS_CTRL2_CHA_STA)==0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
mdelay(10);
|
||||
}
|
||||
if(i>49)
|
||||
printk("clk is not stable\n");
|
||||
|
||||
//VESA range, 6bits BPC, RGB
|
||||
val = 0x00;
|
||||
anx6345_i2c_write_p1_reg(client, SP_TX_VID_CTRL2_REG, &val);
|
||||
|
||||
//ANX6345 chip pll setting
|
||||
val = 0x00;
|
||||
anx6345_i2c_write_p0_reg(client, SP_TX_PLL_CTRL_REG, &val); //UPDATE: FROM 0X07 TO 0X00
|
||||
|
||||
|
||||
//ANX chip analog setting
|
||||
val = 0x70;
|
||||
anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val); //UPDATE: FROM 0XF0 TO 0X70
|
||||
val = 0x30;
|
||||
anx6345_i2c_write_p0_reg(client, SP_TX_LINK_DEBUG_REG, &val);
|
||||
|
||||
//force HPD
|
||||
//anx6345_i2c_write_p0_reg(client, SP_TX_SYS_CTRL3_REG, &val);
|
||||
|
||||
|
||||
//reset AUX
|
||||
anx6345_i2c_read_p1_reg(client, SP_TX_RST_CTRL2_REG, &val);
|
||||
val |= SP_TX_AUX_RST;
|
||||
anx6345_i2c_write_p1_reg(client, SP_TX_RST_CTRL2_REG, &val);
|
||||
val &= ~SP_TX_AUX_RST;
|
||||
anx6345_i2c_write_p1_reg(client, SP_TX_RST_CTRL2_REG, &val);
|
||||
|
||||
//Select 2.7G
|
||||
val = 0x0a;
|
||||
anx6345_i2c_write_p0_reg(client, SP_TX_LINK_BW_SET_REG, &val);
|
||||
//Select 2 lanes
|
||||
val = 0x02;
|
||||
anx6345_i2c_write_p0_reg(client,SP_TX_LANE_COUNT_SET_REG,&val);
|
||||
|
||||
val = SP_TX_LINK_TRAINING_CTRL_EN;
|
||||
anx6345_i2c_write_p0_reg(client, SP_TX_LINK_TRAINING_CTRL_REG, &val);
|
||||
mdelay(5);
|
||||
anx6345_i2c_read_p0_reg(client, SP_TX_LINK_TRAINING_CTRL_REG, &val);
|
||||
while((val&0x80)&&(cnt)) //UPDATE: FROM 0X01 TO 0X80
|
||||
{
|
||||
printk("Waiting...\n");
|
||||
mdelay(5);
|
||||
anx6345_i2c_read_p0_reg(client,SP_TX_LINK_TRAINING_CTRL_REG,&val);
|
||||
cnt--;
|
||||
}
|
||||
if(cnt <= 0)
|
||||
{
|
||||
printk(KERN_INFO "HW LT fail\n");
|
||||
}
|
||||
else
|
||||
printk("HW LT Success>>:times:%d\n",(51-cnt));
|
||||
|
||||
|
||||
|
||||
//enable video input, set DDR mode, the input DCLK should be 102.5MHz;
|
||||
//In normal mode, set this reg to 0x81, SDR mode, the input DCLK should be 205MHz
|
||||
|
||||
#if defined(BIST_MODE)
|
||||
anx6345_bist_mode(client);
|
||||
val = 0x8f;
|
||||
#else
|
||||
val = 0x81;
|
||||
#endif
|
||||
anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL1_REG,&val);
|
||||
|
||||
anx_video_map_config(client);
|
||||
//force HPD and stream valid
|
||||
val = 0x33;
|
||||
anx6345_i2c_write_p0_reg(client,SP_TX_SYS_CTRL3_REG,&val);
|
||||
|
||||
anx6345_i2c_read_p0_reg(client,SP_TX_LANE_COUNT_SET_REG, &lc);
|
||||
anx6345_i2c_read_p0_reg(client,SP_TX_LINK_BW_SET_REG, &bw);
|
||||
printk("%s..lc:%d--bw:%d\n",__func__,lc,bw);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_HAS_EARLYSUSPEND
|
||||
static void anx6345_early_suspend(struct early_suspend *h)
|
||||
{
|
||||
struct edp_anx6345 *anx6345 = container_of(h, struct edp_anx6345, early_suspend);
|
||||
gpio_set_value(anx6345->pdata->dvdd33_en_pin,!anx6345->pdata->dvdd33_en_val);
|
||||
gpio_set_value(anx6345->pdata->dvdd18_en_pin,!anx6345->pdata->dvdd18_en_val);
|
||||
}
|
||||
|
||||
static void anx6345_late_resume(struct early_suspend *h)
|
||||
{
|
||||
struct edp_anx6345 *anx6345 = container_of(h, struct edp_anx6345, early_suspend);
|
||||
gpio_set_value(anx6345->pdata->dvdd33_en_pin,anx6345->pdata->dvdd33_en_val);
|
||||
gpio_set_value(anx6345->pdata->dvdd18_en_pin,anx6345->pdata->dvdd18_en_val);
|
||||
gpio_set_value(anx6345->pdata->edp_rst_pin,0);
|
||||
msleep(50);
|
||||
gpio_set_value(anx6345->pdata->edp_rst_pin,1);
|
||||
anx6345->edp_anx_init(anx6345->client);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int anx6345_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id)
|
||||
{
|
||||
int ret;
|
||||
|
||||
struct edp_anx6345 *anx6345 = NULL;
|
||||
int chip_id;
|
||||
|
||||
|
||||
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
|
||||
{
|
||||
dev_err(&client->dev, "Must have I2C_FUNC_I2C.\n");
|
||||
ret = -ENODEV;
|
||||
}
|
||||
anx6345 = kzalloc(sizeof(struct edp_anx6345), GFP_KERNEL);
|
||||
if (anx6345 == NULL)
|
||||
{
|
||||
printk(KERN_ALERT "alloc for struct anx6345 fail\n");
|
||||
ret = -ENOMEM;
|
||||
}
|
||||
|
||||
anx6345->client = client;
|
||||
anx6345->pdata = client->dev.platform_data;
|
||||
i2c_set_clientdata(client,anx6345);
|
||||
if(anx6345->pdata->power_ctl)
|
||||
anx6345->pdata->power_ctl();
|
||||
|
||||
debugfs_create_file("edp-reg", S_IRUSR,NULL,anx6345,&edp_reg_fops);
|
||||
|
||||
#ifdef CONFIG_HAS_EARLYSUSPEND
|
||||
anx6345->early_suspend.suspend = anx6345_early_suspend;
|
||||
anx6345->early_suspend.resume = anx6345_late_resume;
|
||||
anx6345->early_suspend.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING;
|
||||
register_early_suspend(&anx6345->early_suspend);
|
||||
#endif
|
||||
chip_id = get_dp_chip_id(client);
|
||||
if(chip_id == 0x9805)
|
||||
anx6345->edp_anx_init = anx980x_init;
|
||||
else
|
||||
anx6345->edp_anx_init = anx6345_init;
|
||||
|
||||
anx6345->edp_anx_init(client);
|
||||
|
||||
printk("edp anx%x probe ok\n",get_dp_chip_id(client));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devexit anx6345_i2c_remove(struct i2c_client *client)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct i2c_device_id id_table[] = {
|
||||
{"anx6345", 0 },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct i2c_driver anx6345_i2c_driver = {
|
||||
.driver = {
|
||||
.name = "anx6345",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = &anx6345_i2c_probe,
|
||||
.remove = &anx6345_i2c_remove,
|
||||
.id_table = id_table,
|
||||
};
|
||||
|
||||
|
||||
static int __init anx6345_module_init(void)
|
||||
{
|
||||
return i2c_add_driver(&anx6345_i2c_driver);
|
||||
}
|
||||
|
||||
static void __exit anx6345_module_exit(void)
|
||||
{
|
||||
i2c_del_driver(&anx6345_i2c_driver);
|
||||
}
|
||||
|
||||
fs_initcall_sync(anx6345_module_init);
|
||||
module_exit(anx6345_module_exit);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
703
include/linux/anx6345.h
Executable file
703
include/linux/anx6345.h
Executable file
@@ -0,0 +1,703 @@
|
||||
#ifndef __ANX6345_H_
|
||||
#define __ANX6345_H_
|
||||
|
||||
#include<linux/rk_screen.h>
|
||||
#include<linux/earlysuspend.h>
|
||||
#include<linux/anx9805.h>
|
||||
|
||||
#define ANX6345_SCL_RATE (100*1000)
|
||||
|
||||
#define MAX_REG 0xf0
|
||||
#define MAX_BUF_CNT 6
|
||||
|
||||
|
||||
#define DP_TX_PORT0_ADDR 0x70
|
||||
#define HDMI_TX_PORT0_ADDR 0x72
|
||||
|
||||
/***************************************************************/
|
||||
// DEV_ADDR = 0x7A or 0x7B , MIPI Rx Registers
|
||||
#define MIPI_ANALOG_PWD_CTRL0 0x00
|
||||
#define MIPI_ANALOG_PWD_CTRL1 0x01
|
||||
#define MIPI_ANALOG_PWD_CTRL2 0x02
|
||||
|
||||
#define MIPI_MISC_CTRL 0x03
|
||||
|
||||
#define MIPI_TIMING_REG0 0x04
|
||||
#define MIPI_TIMING_REG1 0x05
|
||||
#define MIPI_TIMING_REG2 0x06
|
||||
#define MIPI_TIMING_REG3 0x07
|
||||
#define MIPI_TIMING_REG4 0x08
|
||||
#define MIPI_TIMING_REG5 0x09
|
||||
#define MIPI_TIMING_REG6 0x0a
|
||||
|
||||
#define MIPI_HS_JITTER_REG 0x0B
|
||||
|
||||
#define MIPI_VID_STABLE_CNT 0x0C
|
||||
|
||||
#define MIPI_ANALOG_CTRL0 0x0D
|
||||
#define MIPI_ANALOG_CTRL1 0x0E
|
||||
#define MIPI_ANALOG_CTRL2 0x0F
|
||||
|
||||
#define MIPI_PRBS_REG 0x10
|
||||
#define MIPI_PROTOCOL_STATE 0x11
|
||||
|
||||
|
||||
//End for DEV_addr 0x7A/0x7E
|
||||
|
||||
/***************************************************************/
|
||||
// DEV_ADDR = 0x70 or 0x78 , Displayport mode and HDCP registers
|
||||
#define SP_TX_HDCP_STATUS 0x00
|
||||
#define SP_TX_HDCP_AUTH_PASS 0x02//bit position
|
||||
|
||||
#define SP_TX_HDCP_CONTROL_0_REG 0x01
|
||||
#define SP_TX_HDCP_CONTROL_0_STORE_AN 0x80//bit position
|
||||
#define SP_TX_HDCP_CONTROL_0_RX_REPEATER 0x40//bit position
|
||||
#define SP_TX_HDCP_CONTROL_0_RE_AUTH 0x20//bit position
|
||||
#define SP_TX_HDCP_CONTROL_0_SW_AUTH_OK 0x10//bit position
|
||||
#define SP_TX_HDCP_CONTROL_0_HARD_AUTH_EN 0x08//bit position
|
||||
#define SP_TX_HDCP_CONTROL_0_HDCP_ENC_EN 0x04//bit position
|
||||
#define SP_TX_HDCP_CONTROL_0_BKSV_SRM_PASS 0x02//bit position
|
||||
#define SP_TX_HDCP_CONTROL_0_KSVLIST_VLD 0x01//bit position
|
||||
|
||||
|
||||
#define SP_TX_HDCP_CONTROL_1_REG 0x02
|
||||
#define SP_TX_HDCP_CONTROL_1_DDC_NO_STOP 0x20//bit position
|
||||
#define SP_TX_HDCP_CONTROL_1_DDC_NO_ACK 0x10//bit position
|
||||
#define SP_TX_HDCP_CONTROL_1_EDDC_NO_ACK 0x08//bit position
|
||||
//#define SP_TX_HDCP_CONTROL_1_HDCP_EMB_SCREEN_EN 0x04//bit position
|
||||
#define SP_TX_HDCP_CONTROL_1_RCV_11_EN 0x02//bit position
|
||||
#define SP_TX_HDCP_CONTROL_1_HDCP_11_EN 0x01//bit position
|
||||
|
||||
#define SP_TX_HDCP_LINK_CHK_FRAME_NUM 0x03
|
||||
#define SP_TX_HDCP_CONTROL_2_REG 0x04
|
||||
|
||||
#define SP_TX_HDCP_AKSV0 0x05
|
||||
#define SP_TX_HDCP_AKSV1 0x06
|
||||
#define SP_TX_HDCP_AKSV2 0x07
|
||||
#define SP_TX_HDCP_AKSV3 0x08
|
||||
#define SP_TX_HDCP_AKSV4 0x09
|
||||
|
||||
//AKSV
|
||||
#define SP_TX_HDCP_AN0 0x0A
|
||||
#define SP_TX_HDCP_AN1 0x0B
|
||||
#define SP_TX_HDCP_AN2 0x0C
|
||||
#define SP_TX_HDCP_AN3 0x0D
|
||||
#define SP_TX_HDCP_AN4 0x0E
|
||||
#define SP_TX_HDCP_AN5 0x0F
|
||||
#define SP_TX_HDCP_AN6 0x10
|
||||
#define SP_TX_HDCP_AN7 0x11
|
||||
|
||||
//BKSV
|
||||
#define SP_TX_HDCP_BKSV0 0x12
|
||||
#define SP_TX_HDCP_BKSV1 0x13
|
||||
#define SP_TX_HDCP_BKSV2 0x14
|
||||
#define SP_TX_HDCP_BKSV3 0x15
|
||||
#define SP_TX_HDCP_BKSV4 0x16
|
||||
|
||||
#define SP_TX_HDCP_R0_L 0x17
|
||||
#define SP_TX_HDCP_R0_H 0x18
|
||||
|
||||
#define M_VID_0 0xC0
|
||||
#define M_VID_1 0xC1
|
||||
#define M_VID_2 0xC2
|
||||
#define N_VID_0 0xC3
|
||||
#define N_VID_1 0xC4
|
||||
#define N_VID_2 0xC5
|
||||
|
||||
#define SP_TX_HDCP_R0_WAIT_Timer 0x40
|
||||
|
||||
|
||||
|
||||
#define SP_TX_SYS_CTRL1_REG 0x80
|
||||
//#define SP_TX_SYS_CTRL1_PD_IO 0x80 // bit position
|
||||
//#define SP_TX_SYS_CTRL1_PD_VID 0x40 // bit position
|
||||
//#define SP_TX_SYS_CTRL1_PD_LINK 0x20 // bit position
|
||||
//#define SP_TX_SYS_CTRL1_PD_TOTAL 0x10 // bit position
|
||||
//#define SP_TX_SYS_CTRL1_MODE_SEL 0x08 // bit position
|
||||
#define SP_TX_SYS_CTRL1_DET_STA 0x04 // bit position
|
||||
#define SP_TX_SYS_CTRL1_FORCE_DET 0x02 // bit position
|
||||
#define SP_TX_SYS_CTRL1_DET_CTRL 0x01 // bit position
|
||||
|
||||
#define SP_TX_SYS_CTRL2_REG 0x81
|
||||
// #define SP_TX_SYS_CTRL2_ENHANCED 0x08 //bit position
|
||||
#define SP_TX_SYS_CTRL2_CHA_STA 0x04 // bit position
|
||||
#define SP_TX_SYS_CTRL2_FORCE_CHA 0x02 // bit position
|
||||
#define SP_TX_SYS_CTRL2_CHA_CTRL 0x01 // bit position
|
||||
|
||||
#define SP_TX_SYS_CTRL3_REG 0x82
|
||||
#define SP_TX_SYS_CTRL3_HPD_STATUS 0x40 // bit position
|
||||
#define SP_TX_SYS_CTRL3_F_HPD 0x20 // bit position
|
||||
#define SP_TX_SYS_CTRL3_HPD_CTRL 0x10 // bit position
|
||||
#define SP_TX_SYS_CTRL3_STRM_VALID 0x04 // bit position
|
||||
#define SP_TX_SYS_CTRL3_F_VALID 0x02 // bit position
|
||||
#define SP_TX_SYS_CTRL3_VALID_CTRL 0x01 // bit position
|
||||
|
||||
#define SP_TX_SYS_CTRL4_REG 0x83
|
||||
#define SP_TX_SYS_CTRL4_ENHANCED 0x08//bit position
|
||||
|
||||
#define SP_TX_VID_CTRL 0x84
|
||||
|
||||
#define SP_TX_AUD_CTRL 0x87
|
||||
#define SP_TX_AUD_CTRL_AUD_EN 0x01
|
||||
|
||||
|
||||
#define SP_TX_PKT_EN_REG 0x90
|
||||
#define SP_TX_PKT_AUD_UP 0x80 // bit position
|
||||
#define SP_TX_PKT_AVI_UD 0x40 // bit position
|
||||
#define SP_TX_PKT_MPEG_UD 0x20 // bit position
|
||||
#define SP_TX_PKT_SPD_UD 0x10 // bit position
|
||||
#define SP_TX_PKT_AUD_EN 0x08 // bit position=
|
||||
#define SP_TX_PKT_AVI_EN 0x04 // bit position
|
||||
#define SP_TX_PKT_MPEG_EN 0x02 // bit position
|
||||
#define SP_TX_PKT_SPD_EN 0x01 // bit position
|
||||
|
||||
|
||||
#define SP_TX_HDCP_CTRL 0x92
|
||||
|
||||
#define SP_TX_LINK_BW_SET_REG 0xA0
|
||||
#define SP_TX_LANE_COUNT_SET_REG 0xA1
|
||||
|
||||
#define SP_TX_TRAINING_PTN_SET_REG 0xA2
|
||||
#define SP_TX_SCRAMBLE_DISABLE 0x20//bit 5
|
||||
|
||||
#define SP_TX_TRAINING_LANE0_SET_REG 0xA3
|
||||
#define SP_TX_TRAINING_LANE0_SET_MAX_PRE_REACH 0x20 // bit position
|
||||
#define SP_TX_TRAINING_LANE0_SET_MAX_DRIVE_REACH 0x04 // bit position
|
||||
|
||||
#define SP_TX_TRAINING_LANE1_SET_REG 0xA4
|
||||
|
||||
|
||||
#define SSC_CTRL_REG1 0xA7
|
||||
#define SPREAD_AMP 0x10//bit 4
|
||||
#define MODULATION_FREQ 0x01//bit 0
|
||||
|
||||
|
||||
#define SP_TX_LINK_TRAINING_CTRL_REG 0xA8
|
||||
#define SP_TX_LINK_TRAINING_CTRL_EN 0x01 // bit position
|
||||
|
||||
|
||||
#define SP_TX_DEBUG_REG1 0xB0
|
||||
#define SP_TX_DEBUG_HPD_POLLING_DET 0x40//bit position
|
||||
#define SP_TX_DEBUG_HPD_POLLING_EN 0x20//bit position
|
||||
#define SP_TX_DEBUG_PLL_LOCK 0x10//bit position
|
||||
|
||||
|
||||
#define SP_TX_LINK_DEBUG_REG 0xB8
|
||||
#define SP_TX_LINK_DEBUG_INSERT_ER 0x02 // bit position
|
||||
#define SP_TX_LINK_DEBUG_PRBS31_EN 0x01 // bit position
|
||||
|
||||
#define SP_TX_SINK_COUNT_REG 0xB9
|
||||
|
||||
#define SP_TX_LINK_STATUS_REG1 0xBB
|
||||
|
||||
#define SP_TX_SINK_STATUS_REG 0xBE
|
||||
#define SP_TX_SINK_STATUS_SINK_STATUS_1 0x02 // bit position
|
||||
#define SP_TX_SINK_STATUS_SINK_STATUS_0 0x01 // bit position
|
||||
|
||||
|
||||
//#define SP_TX_LINK_TEST_COUNT 0xC0
|
||||
|
||||
|
||||
#define SP_TX_PLL_CTRL_REG 0xC7
|
||||
#define SP_TX_PLL_CTRL_PLL_PD 0x80 // bit position
|
||||
#define SP_TX_PLL_CTRL_PLL_RESET 0x40 // bit position
|
||||
//#define SP_TX_PLL_CTRL_CPREG_BLEED 0x08 // bit position
|
||||
|
||||
#define SP_TX_ANALOG_POWER_DOWN_REG 0xC8
|
||||
#define SP_TX_ANALOG_POWER_DOWN_MACRO_PD 0x20 // bit position
|
||||
#define SP_TX_ANALOG_POWER_DOWN_AUX_PD 0x10 // bit position
|
||||
//#define SP_TX_ANALOG_POWER_DOWN_CH3_PD 0x08 // bit position
|
||||
//#define SP_TX_ANALOG_POWER_DOWN_CH2_PD 0x04 // bit position
|
||||
#define SP_TX_ANALOG_POWER_DOWN_CH1_PD 0x02 // bit position
|
||||
#define SP_TX_ANALOG_POWER_DOWN_CH0_PD 0x01 // bit position
|
||||
|
||||
|
||||
#define SP_TX_ANALOG_TEST_REG 0xC9
|
||||
#define SP_TX_ANALOG_TEST_MACRO_RST 0x20 // bit position
|
||||
#define SP_TX_ANALOG_TEST_PLL_TEST 0x10 // bit position
|
||||
#define SP_TX_ANALOG_TEST_CH3_TEST 0x08 // bit position
|
||||
#define SP_TX_ANALOG_TEST_CH2_TEST 0x04 // bit position
|
||||
#define SP_TX_ANALOG_TEST_CH1_TEST 0x02 // bit position
|
||||
#define SP_TX_ANALOG_TEST_CH0_TEST 0x01 // bit position
|
||||
|
||||
#define SP_TX_GNS_CTRL_REG 0xCD
|
||||
#define SP_EQ_LOOP_CNT 0x40//bit position
|
||||
#define SP_TX_VIDEO_MAP_CTRL 0x02 // bit position
|
||||
#define SP_TX_RS_CTRL 0x01 // bit position
|
||||
|
||||
#define SP_TX_DOWN_SPREADING_CTRL1 0xD0 //guochuncheng
|
||||
#define SP_TX_DOWN_SPREADING_CTRL2 0xD1
|
||||
#define SP_TX_DOWN_SPREADING_CTRL3 0xD2
|
||||
#define SP_TX_SSC_D_CTRL 0x40 //bit position
|
||||
#define SP_TX_FS_CTRL_TH_CTRL 0x20 //bit position
|
||||
|
||||
#define SP_TX_M_CALCU_CTRL 0xD9
|
||||
#define M_GEN_CLK_SEL 0x01//bit 0
|
||||
|
||||
|
||||
#define SP_TX_EXTRA_ADDR_REG 0xCE
|
||||
#define SP_TX_I2C_STRETCH_CTRL_REG 0xDB
|
||||
#define SP_TX_AUX_STATUS 0xE0
|
||||
#define SP_TX_DEFER_CTRL_REG 0xE2
|
||||
#define SP_TXL_DEFER_CTRL_EN 0x80 // bit position
|
||||
|
||||
#define SP_TX_BUF_DATA_COUNT_REG 0xE4
|
||||
#define SP_TX_AUX_CTRL_REG 0xE5
|
||||
#define SP_TX_MOT_BIT 0x04//bit 2
|
||||
|
||||
#define SP_TX_AUX_ADDR_7_0_REG 0xE6
|
||||
#define SP_TX_AUX_ADDR_15_8_REG 0xE7
|
||||
#define SP_TX_AUX_ADDR_19_16_REG 0xE8
|
||||
|
||||
#define SP_TX_AUX_CTRL_REG2 0xE9
|
||||
#define SP_TX_ADDR_ONLY_BIT 0x02//bit 1
|
||||
|
||||
#define SP_TX_BUF_DATA_0_REG 0xf0
|
||||
#define SP_TX_BUF_DATA_1_REG 0xf1
|
||||
#define SP_TX_BUF_DATA_2_REG 0xf2
|
||||
#define SP_TX_BUF_DATA_3_REG 0xf3
|
||||
#define SP_TX_BUF_DATA_4_REG 0xf4
|
||||
#define SP_TX_BUF_DATA_5_REG 0xf5
|
||||
#define SP_TX_BUF_DATA_6_REG 0xf6
|
||||
#define SP_TX_BUF_DATA_7_REG 0xf7
|
||||
#define SP_TX_BUF_DATA_8_REG 0xf8
|
||||
#define SP_TX_BUF_DATA_9_REG 0xf9
|
||||
#define SP_TX_BUF_DATA_10_REG 0xfa
|
||||
#define SP_TX_BUF_DATA_11_REG 0xfb
|
||||
#define SP_TX_BUF_DATA_12_REG 0xfc
|
||||
#define SP_TX_BUF_DATA_13_REG 0xfd
|
||||
#define SP_TX_BUF_DATA_14_REG 0xfe
|
||||
#define SP_TX_BUF_DATA_15_REG 0xff
|
||||
|
||||
//End for Address 0x70 or 0x78
|
||||
|
||||
/***************************************************************/
|
||||
// DEV_ADDR = 0x72 or 0x76, System control registers
|
||||
#define SP_TX_VND_IDL_REG 0x00
|
||||
#define SP_TX_VND_IDH_REG 0x01
|
||||
#define SP_TX_DEV_IDL_REG 0x02
|
||||
#define SP_TX_DEV_IDH_REG 0x03
|
||||
#define SP_TX_DEV_REV_REG 0x04
|
||||
|
||||
#define SP_POWERD_CTRL_REG 0x05
|
||||
#define SP_POWERD_REGISTER_REG 0x80// bit position
|
||||
//#define SP_POWERD_MISC_REG 0x40// bit position
|
||||
#define SP_POWERD_IO_REG 0x20// bit position
|
||||
#define SP_POWERD_AUDIO_REG 0x10// bit position
|
||||
#define SP_POWERD_VIDEO_REG 0x08// bit position
|
||||
#define SP_POWERD_LINK_REG 0x04// bit position
|
||||
#define SP_POWERD_TOTAL_REG 0x02// bit position
|
||||
#define SP_MODE_SEL_REG 0x01// bit position
|
||||
|
||||
#define SP_TX_RST_CTRL_REG 0x06
|
||||
#define SP_TX_RST_MISC_REG 0x80 // bit position
|
||||
#define SP_TX_RST_VIDCAP_REG 0x40 // bit position
|
||||
#define SP_TX_RST_VIDFIF_REG 0x20 // bit position
|
||||
#define SP_TX_RST_AUDFIF_REG 0x10 // bit position
|
||||
#define SP_TX_RST_AUDCAP_REG 0x08 // bit position
|
||||
#define SP_TX_RST_HDCP_REG 0x04 // bit position
|
||||
#define SP_TX_RST_SW_RST 0x02 // bit position
|
||||
#define SP_TX_RST_HW_RST 0x01 // bit position
|
||||
|
||||
#define SP_TX_RST_CTRL2_REG 0x07
|
||||
#define SP_TX_RST_SSC 0x80//bit position
|
||||
#define SP_TX_AC_MODE 0x40//bit position
|
||||
//#define SP_TX_DDC_RST 0x10//bit position
|
||||
//#define SP_TX_TMDS_BIST_RST 0x08//bit position
|
||||
#define SP_TX_AUX_RST 0x04//bit position
|
||||
#define SP_TX_SERDES_FIFO_RST 0x02//bit position
|
||||
#define SP_TX_I2C_REG_RST 0x01//bit position
|
||||
|
||||
|
||||
#define SP_TX_VID_CTRL1_REG 0x08
|
||||
#define SP_TX_VID_CTRL1_VID_EN 0x80 // bit position
|
||||
#define SP_TX_VID_CTRL1_VID_MUTE 0x40 // bit position
|
||||
#define SP_TX_VID_CTRL1_DE_GEN 0x20 // bit position
|
||||
#define SP_TX_VID_CTRL1_DEMUX 0x10 // bit position
|
||||
#define SP_TX_VID_CTRL1_IN_BIT 0x04 // bit position
|
||||
#define SP_TX_VID_CTRL1_DDRCTRL 0x02 // bit position
|
||||
#define SP_TX_VID_CTRL1_EDGE 0x01 // bit position
|
||||
|
||||
#define SP_TX_VID_CTRL2_REG 0x09
|
||||
#define SP_TX_VID_CTRL1_YCBIT_SEL 0x04 // bit position
|
||||
|
||||
#define SP_TX_VID_CTRL3_REG 0x0A
|
||||
|
||||
#define SP_TX_VID_CTRL4_REG 0x0B
|
||||
#define SP_TX_VID_CTRL4_E_SYNC_EN 0x80 //bit position
|
||||
#define SP_TX_VID_CTRL4_EX_E_SYNC 0x40 // bit position
|
||||
#define SP_TX_VID_CTRL4_BIST 0x08 // bit position
|
||||
#define SP_TX_VID_CTRL4_BIST_WIDTH 0x04 // bit position
|
||||
|
||||
#define SP_TX_VID_CTRL5_REG 0x0C
|
||||
|
||||
#define SP_TX_VID_CTRL6_REG 0x0D
|
||||
#define SP_TX_VID_UPSAMPLE 0x02//bit position
|
||||
|
||||
#define SP_TX_VID_CTRL7_REG 0x0E
|
||||
#define SP_TX_VID_CTRL8_REG 0x0F
|
||||
#define SP_TX_VID_CTRL9_REG 0x10
|
||||
|
||||
#define SP_TX_VID_CTRL10_REG 0x11
|
||||
#define SP_TX_VID_CTRL10_INV_F 0x08 // bit position
|
||||
#define SP_TX_VID_CTRL10_I_SCAN 0x04 // bit position
|
||||
#define SP_TX_VID_CTRL10_VSYNC_POL 0x02 // bit position
|
||||
#define SP_TX_VID_CTRL10_HSYNC_POL 0x01 // bit position
|
||||
|
||||
#define SP_TX_TOTAL_LINEL_REG 0x12
|
||||
#define SP_TX_TOTAL_LINEH_REG 0x13
|
||||
#define SP_TX_ACT_LINEL_REG 0x14
|
||||
#define SP_TX_ACT_LINEH_REG 0x15
|
||||
#define SP_TX_VF_PORCH_REG 0x16
|
||||
#define SP_TX_VSYNC_CFG_REG 0x17
|
||||
#define SP_TX_VB_PORCH_REG 0x18
|
||||
#define SP_TX_TOTAL_PIXELL_REG 0x19
|
||||
#define SP_TX_TOTAL_PIXELH_REG 0x1A
|
||||
#define SP_TX_ACT_PIXELL_REG 0x1B
|
||||
#define SP_TX_ACT_PIXELH_REG 0x1C
|
||||
#define SP_TX_HF_PORCHL_REG 0x1D
|
||||
#define SP_TX_HF_PORCHH_REG 0x1E
|
||||
#define SP_TX_HSYNC_CFGL_REG 0x1F
|
||||
#define SP_TX_HSYNC_CFGH_REG 0x20
|
||||
#define SP_TX_HB_PORCHL_REG 0x21
|
||||
#define SP_TX_HB_PORCHH_REG 0x22
|
||||
|
||||
#define SP_TX_VID_STATUS 0x23
|
||||
|
||||
#define SP_TX_TOTAL_LINE_STA_L 0x24
|
||||
#define SP_TX_TOTAL_LINE_STA_H 0x25
|
||||
#define SP_TX_ACT_LINE_STA_L 0x26
|
||||
#define SP_TX_ACT_LINE_STA_H 0x27
|
||||
#define SP_TX_V_F_PORCH_STA 0x28
|
||||
#define SP_TX_V_SYNC_STA 0x29
|
||||
#define SP_TX_V_B_PORCH_STA 0x2A
|
||||
#define SP_TX_TOTAL_PIXEL_STA_L 0x2B
|
||||
#define SP_TX_TOTAL_PIXEL_STA_H 0x2C
|
||||
#define SP_TX_ACT_PIXEL_STA_L 0x2D
|
||||
#define SP_TX_ACT_PIXEL_STA_H 0x2E
|
||||
#define SP_TX_H_F_PORCH_STA_L 0x2F
|
||||
#define SP_TX_H_F_PORCH_STA_H 0x30
|
||||
#define SP_TX_H_SYNC_STA_L 0x31
|
||||
#define SP_TX_H_SYNC_STA_H 0x32
|
||||
#define SP_TX_H_B_PORCH_STA_L 0x33
|
||||
#define SP_TX_H_B_PORCH_STA_H 0x34
|
||||
|
||||
#define SP_TX_Video_Interface_BIST 0x35
|
||||
|
||||
#define SPDIF_AUDIO_CTRL0 0x36
|
||||
#define SPDIF_AUDIO_CTRL0_SPDIF_IN 0x80 // bit position
|
||||
|
||||
#define SPDIF_AUDIO_STATUS0 0x38
|
||||
#define SPDIF_AUDIO_STATUS0_CLK_DET 0x80
|
||||
#define SPDIF_AUDIO_STATUS0_AUD_DET 0x01
|
||||
|
||||
#define SPDIF_AUDIO_STATUS1 0x39
|
||||
|
||||
#define AUDIO_BIST_CTRL 0x3c
|
||||
#define AUDIO_BIST_EN 0x01
|
||||
|
||||
//#define AUDIO_BIST_CHANNEL_STATUS1 0xd0
|
||||
//#define AUDIO_BIST_CHANNEL_STATUS2 0xd1
|
||||
//#define AUDIO_BIST_CHANNEL_STATUS3 0xd2
|
||||
//#define AUDIO_BIST_CHANNEL_STATUS4 0xd3
|
||||
//#define AUDIO_BIST_CHANNEL_STATUS5 0xd4
|
||||
|
||||
#define SP_TX_VIDEO_BIT_CTRL_0_REG 0x40
|
||||
#define SP_TX_VIDEO_BIT_CTRL_1_REG 0x41
|
||||
#define SP_TX_VIDEO_BIT_CTRL_2_REG 0x42
|
||||
#define SP_TX_VIDEO_BIT_CTRL_3_REG 0x43
|
||||
#define SP_TX_VIDEO_BIT_CTRL_4_REG 0x44
|
||||
#define SP_TX_VIDEO_BIT_CTRL_5_REG 0x45
|
||||
#define SP_TX_VIDEO_BIT_CTRL_6_REG 0x46
|
||||
#define SP_TX_VIDEO_BIT_CTRL_7_REG 0x47
|
||||
#define SP_TX_VIDEO_BIT_CTRL_8_REG 0x48
|
||||
#define SP_TX_VIDEO_BIT_CTRL_9_REG 0x49
|
||||
#define SP_TX_VIDEO_BIT_CTRL_10_REG 0x4a
|
||||
#define SP_TX_VIDEO_BIT_CTRL_11_REG 0x4b
|
||||
#define SP_TX_VIDEO_BIT_CTRL_12_REG 0x4c
|
||||
#define SP_TX_VIDEO_BIT_CTRL_13_REG 0x4d
|
||||
#define SP_TX_VIDEO_BIT_CTRL_14_REG 0x4e
|
||||
#define SP_TX_VIDEO_BIT_CTRL_15_REG 0x4f
|
||||
#define SP_TX_VIDEO_BIT_CTRL_16_REG 0x50
|
||||
#define SP_TX_VIDEO_BIT_CTRL_17_REG 0x51
|
||||
#define SP_TX_VIDEO_BIT_CTRL_18_REG 0x52
|
||||
#define SP_TX_VIDEO_BIT_CTRL_19_REG 0x53
|
||||
#define SP_TX_VIDEO_BIT_CTRL_20_REG 0x54
|
||||
#define SP_TX_VIDEO_BIT_CTRL_21_REG 0x55
|
||||
#define SP_TX_VIDEO_BIT_CTRL_22_REG 0x56
|
||||
#define SP_TX_VIDEO_BIT_CTRL_23_REG 0x57
|
||||
#define SP_TX_VIDEO_BIT_CTRL_24_REG 0x58
|
||||
#define SP_TX_VIDEO_BIT_CTRL_25_REG 0x59
|
||||
#define SP_TX_VIDEO_BIT_CTRL_26_REG 0x5a
|
||||
#define SP_TX_VIDEO_BIT_CTRL_27_REG 0x5b
|
||||
#define SP_TX_VIDEO_BIT_CTRL_28_REG 0x5c
|
||||
#define SP_TX_VIDEO_BIT_CTRL_29_REG 0x5d
|
||||
#define SP_TX_VIDEO_BIT_CTRL_30_REG 0x5e
|
||||
#define SP_TX_VIDEO_BIT_CTRL_31_REG 0x5f
|
||||
#define SP_TX_VIDEO_BIT_CTRL_32_REG 0x60
|
||||
#define SP_TX_VIDEO_BIT_CTRL_33_REG 0x61
|
||||
#define SP_TX_VIDEO_BIT_CTRL_34_REG 0x62
|
||||
#define SP_TX_VIDEO_BIT_CTRL_35_REG 0x63
|
||||
#define SP_TX_VIDEO_BIT_CTRL_36_REG 0x64
|
||||
#define SP_TX_VIDEO_BIT_CTRL_37_REG 0x65
|
||||
#define SP_TX_VIDEO_BIT_CTRL_38_REG 0x66
|
||||
#define SP_TX_VIDEO_BIT_CTRL_39_REG 0x67
|
||||
#define SP_TX_VIDEO_BIT_CTRL_40_REG 0x68
|
||||
#define SP_TX_VIDEO_BIT_CTRL_41_REG 0x69
|
||||
#define SP_TX_VIDEO_BIT_CTRL_42_REG 0x6a
|
||||
#define SP_TX_VIDEO_BIT_CTRL_43_REG 0x6b
|
||||
#define SP_TX_VIDEO_BIT_CTRL_44_REG 0x6c
|
||||
#define SP_TX_VIDEO_BIT_CTRL_45_REG 0x6d
|
||||
#define SP_TX_VIDEO_BIT_CTRL_46_REG 0x6e
|
||||
#define SP_TX_VIDEO_BIT_CTRL_47_REG 0x6f
|
||||
|
||||
//AVI info frame
|
||||
#define SP_TX_AVI_TYPE 0x70
|
||||
#define SP_TX_AVI_VER 0x71
|
||||
#define SP_TX_AVI_LEN 0x72
|
||||
#define SP_TX_AVI_DB0 0x73
|
||||
#define SP_TX_AVI_DB1 0x74
|
||||
#define SP_TX_AVI_DB2 0x75
|
||||
#define SP_TX_AVI_DB3 0x76
|
||||
#define SP_TX_AVI_DB4 0x77
|
||||
#define SP_TX_AVI_DB5 0x78
|
||||
#define SP_TX_AVI_DB6 0x79
|
||||
#define SP_TX_AVI_DB7 0x7A
|
||||
#define SP_TX_AVI_DB8 0x7B
|
||||
#define SP_TX_AVI_DB9 0x7C
|
||||
#define SP_TX_AVI_DB10 0x7D
|
||||
#define SP_TX_AVI_DB11 0x7E
|
||||
#define SP_TX_AVI_DB12 0x7F
|
||||
#define SP_TX_AVI_DB13 0x80
|
||||
#define SP_TX_AVI_DB14 0x81
|
||||
#define SP_TX_AVI_DB15 0x82
|
||||
|
||||
//Audio info frame
|
||||
#define SP_TX_AUD_TYPE 0x83
|
||||
#define SP_TX_AUD_VER 0x84
|
||||
#define SP_TX_AUD_LEN 0x85
|
||||
#define SP_TX_AUD_DB0 0x86
|
||||
#define SP_TX_AUD_DB1 0x87
|
||||
#define SP_TX_AUD_DB2 0x88
|
||||
#define SP_TX_AUD_DB3 0x89
|
||||
#define SP_TX_AUD_DB4 0x8A
|
||||
#define SP_TX_AUD_DB5 0x8B
|
||||
#define SP_TX_AUD_DB6 0x8C
|
||||
#define SP_TX_AUD_DB7 0x8D
|
||||
#define SP_TX_AUD_DB8 0x8E
|
||||
#define SP_TX_AUD_DB9 0x8F
|
||||
#define SP_TX_AUD_DB10 0x90
|
||||
|
||||
//SPD info frame
|
||||
#define SP_TX_SPD_TYPE 0x91
|
||||
#define SP_TX_SPD_VER 0x92
|
||||
#define SP_TX_SPD_LEN 0x93
|
||||
#define SP_TX_SPD_DATA0 0x94
|
||||
#define SP_TX_SPD_DATA1 0x95
|
||||
#define SP_TX_SPD_DATA2 0x96
|
||||
#define SP_TX_SPD_DATA3 0x97
|
||||
#define SP_TX_SPD_DATA4 0x98
|
||||
#define SP_TX_SPD_DATA5 0x99
|
||||
#define SP_TX_SPD_DATA6 0x9A
|
||||
#define SP_TX_SPD_DATA7 0x9B
|
||||
#define SP_TX_SPD_DATA8 0x9C
|
||||
#define SP_TX_SPD_DATA9 0x9D
|
||||
#define SP_TX_SPD_DATA10 0x9E
|
||||
#define SP_TX_SPD_DATA11 0x9F
|
||||
#define SP_TX_SPD_DATA12 0xA0
|
||||
#define SP_TX_SPD_DATA13 0xA1
|
||||
#define SP_TX_SPD_DATA14 0xA2
|
||||
#define SP_TX_SPD_DATA15 0xA3
|
||||
#define SP_TX_SPD_DATA16 0xA4
|
||||
#define SP_TX_SPD_DATA17 0xA5
|
||||
#define SP_TX_SPD_DATA18 0xA6
|
||||
#define SP_TX_SPD_DATA19 0xA7
|
||||
#define SP_TX_SPD_DATA20 0xA8
|
||||
#define SP_TX_SPD_DATA21 0xA9
|
||||
#define SP_TX_SPD_DATA22 0xAA
|
||||
#define SP_TX_SPD_DATA23 0xAB
|
||||
#define SP_TX_SPD_DATA24 0xAC
|
||||
#define SP_TX_SPD_DATA25 0xAD
|
||||
#define SP_TX_SPD_DATA26 0xAE
|
||||
#define SP_TX_SPD_DATA27 0xAF
|
||||
|
||||
//Mpeg source info frame
|
||||
#define SP_TX_MPEG_TYPE 0xB0
|
||||
#define SP_TX_MPEG_VER 0xB1
|
||||
#define SP_TX_MPEG_LEN 0xB2
|
||||
#define SP_TX_MPEG_DATA0 0xB3
|
||||
#define SP_TX_MPEG_DATA1 0xB4
|
||||
#define SP_TX_MPEG_DATA2 0xB5
|
||||
#define SP_TX_MPEG_DATA3 0xB6
|
||||
#define SP_TX_MPEG_DATA4 0xB7
|
||||
#define SP_TX_MPEG_DATA5 0xB8
|
||||
#define SP_TX_MPEG_DATA6 0xB9
|
||||
#define SP_TX_MPEG_DATA7 0xBA
|
||||
#define SP_TX_MPEG_DATA8 0xBB
|
||||
#define SP_TX_MPEG_DATA9 0xBC
|
||||
#define SP_TX_MPEG_DATA10 0xBD
|
||||
#define SP_TX_MPEG_DATA11 0xBE
|
||||
#define SP_TX_MPEG_DATA12 0xBF
|
||||
#define SP_TX_MPEG_DATA13 0xC0
|
||||
#define SP_TX_MPEG_DATA14 0xC1
|
||||
#define SP_TX_MPEG_DATA15 0xC2
|
||||
#define SP_TX_MPEG_DATA16 0xC3
|
||||
#define SP_TX_MPEG_DATA17 0xC4
|
||||
#define SP_TX_MPEG_DATA18 0xC5
|
||||
#define SP_TX_MPEG_DATA19 0xC6
|
||||
#define SP_TX_MPEG_DATA20 0xC7
|
||||
#define SP_TX_MPEG_DATA21 0xC8
|
||||
#define SP_TX_MPEG_DATA22 0xC9
|
||||
#define SP_TX_MPEG_DATA23 0xCA
|
||||
#define SP_TX_MPEG_DATA24 0xCB
|
||||
#define SP_TX_MPEG_DATA25 0xCC
|
||||
#define SP_TX_MPEG_DATA26 0xCD
|
||||
#define SP_TX_MPEG_DATA27 0xCE
|
||||
|
||||
//#define GNSS_CTRL_REG 0xCD
|
||||
//#define ENABLE_SSC_FILTER 0x80//bit
|
||||
|
||||
//#define SSC_D_VALUE 0xD0
|
||||
//#define SSC_CTRL_REG2 0xD1
|
||||
|
||||
#define ANALOG_DEBUG_REG1 0xDC
|
||||
#define ANALOG_SEL_BG 0x40//bit 4
|
||||
#define ANALOG_SWING_A_30PER 0x08//bit 3
|
||||
|
||||
#define ANALOG_DEBUG_REG2 0xDD
|
||||
#define ANALOG_24M_SEL 0x08//bit 3
|
||||
//#define ANALOG_FILTER_ENABLED 0x10//bit 4
|
||||
|
||||
|
||||
#define ANALOG_DEBUG_REG3 0xDE
|
||||
|
||||
#define PLL_FILTER_CTRL1 0xDF
|
||||
#define PD_RING_OSC 0x40//bit 6
|
||||
|
||||
#define PLL_FILTER_CTRL2 0xE0
|
||||
#define PLL_FILTER_CTRL3 0xE1
|
||||
#define PLL_FILTER_CTRL4 0xE2
|
||||
#define PLL_FILTER_CTRL5 0xE3
|
||||
#define PLL_FILTER_CTRL6 0xE4
|
||||
|
||||
#define SP_TX_I2S_CTRL 0xE6
|
||||
#define SP_TX_I2S_FMT 0xE7
|
||||
#define SP_TX_I2S_CH_Status1 0xD0
|
||||
#define SP_TX_I2S_CH_Status2 0xD1
|
||||
#define SP_TX_I2S_CH_Status3 0xD2
|
||||
#define SP_TX_I2S_CH_Status4 0xD3
|
||||
#define SP_TX_I2S_CH_Status5 0xD4
|
||||
|
||||
//interrupt
|
||||
#define SP_COMMON_INT_STATUS1 0xF1
|
||||
#define SP_COMMON_INT1_PLL_LOCK_CHG 0x40//bit position
|
||||
#define SP_COMMON_INT1_VIDEO_FORMAT_CHG 0x08//bit position
|
||||
#define SP_COMMON_INT1_AUDIO_CLK_CHG 0x04//bit position
|
||||
#define SP_COMMON_INT1_VIDEO_CLOCK_CHG 0x02//bit position
|
||||
|
||||
|
||||
#define SP_COMMON_INT_STATUS2 0xF2
|
||||
#define SP_COMMON_INT2_AUTHCHG 0x02 //bit position
|
||||
#define SP_COMMON_INT2_AUTHDONE 0x01 //bit position
|
||||
|
||||
#define SP_COMMON_INT_STATUS3 0xF3
|
||||
#define SP_COMMON_INT3_AFIFO_UNDER 0x80//bit position
|
||||
#define SP_COMMON_INT3_AFIFO_OVER 0x40//bit position
|
||||
|
||||
#define SP_COMMON_INT_STATUS4 0xF4
|
||||
#define SP_COMMON_INT4_PLUG 0x01 // bit position
|
||||
#define SP_COMMON_INT4_ESYNC_ERR 0x10 // bit position
|
||||
#define SP_COMMON_INT4_HPDLOST 0x02 //bit position
|
||||
#define SP_COMMON_INT4_HPD_CHANGE 0x04 //bit position
|
||||
|
||||
|
||||
#define SP_TX_INT_STATUS1 0xF7
|
||||
#define SP_TX_INT_STATUS1_HPD 0x40 //bit position
|
||||
#define SP_TX_INT_STATUS1_TRAINING_Finish 0x20 // bit position
|
||||
#define SP_TX_INT_STATUS1_POLLING_ERR 0x10 // bit position
|
||||
|
||||
#define SP_TX_INT_SINK_CHG 0x08//bit position
|
||||
|
||||
//interrupt mask
|
||||
#define SP_COMMON_INT_MASK1 0xF8
|
||||
#define SP_COMMON_INT_MASK2 0xF9
|
||||
#define SP_COMMON_INT_MASK3 0xFA
|
||||
#define SP_COMMON_INT_MASK4 0xFB
|
||||
#define SP_INT_MASK 0xFE
|
||||
#define SP_TX_INT_CTRL_REG 0xFF
|
||||
//End for dev_addr 0x72 or 0x76
|
||||
|
||||
/***************************************************************/
|
||||
/***************************************************************/
|
||||
|
||||
//DPCD regs
|
||||
#define DPCD_DPCD_REV 0x00
|
||||
#define DPCD_MAX_LINK_RATE 0x01
|
||||
#define DPCD_MAX_LANE_COUNT 0x02
|
||||
#define DPCD_MAX_DOWNSPREAD 0x03
|
||||
#define DPCD_NORP 0x04
|
||||
#define DPCD_DOWNSTREAMPORT_PRESENT 0x05
|
||||
|
||||
#define DPCD_RECEIVE_PORT0_CAP_0 0x08
|
||||
#define DPCD_RECEIVE_PORT0_CAP_1 0x09
|
||||
#define DPCD_RECEIVE_PORT0_CAP_2 0x0a
|
||||
#define DPCD_RECEIVE_PORT0_CAP_3 0x0b
|
||||
|
||||
#define DPCD_LINK_BW_SET 0x00
|
||||
#define DPCD_LANE_COUNT_SET 0x01
|
||||
#define DPCD_TRAINING_PATTERN_SET 0x02
|
||||
#define DPCD_TRAINNIG_LANE0_SET 0x03
|
||||
#define DPCD_TRAINNIG_LANE1_SET 0x04
|
||||
#define DPCD_TRAINNIG_LANE2_SET 0x05
|
||||
#define DPCD_TRAINNIG_LANE3_SET 0x06
|
||||
#define DPCD_DOWNSPREAD_CTRL 0x07
|
||||
|
||||
#define DPCD_SINK_COUNT 0x00
|
||||
#define DPCD_DEVICE_SERVICE_IRQ_VECTOR 0x01
|
||||
#define DPCD_LANE0_1_STATUS 0x02
|
||||
#define DPCD_LANE2_3_STATUS 0x03
|
||||
#define DPCD_LANE_ALIGN_STATUS_UPDATED 0x04
|
||||
#define DPCD_SINK_STATUS 0x05
|
||||
#define DPCD_ADJUST_REQUEST_LANE0_1 0x06
|
||||
#define DPCD_ADJUST_REQUEST_LANE2_3 0x07
|
||||
#define DPCD_TRAINING_SCORE_LANE0 0x08
|
||||
#define DPCD_TRAINING_SCORE_LANE1 0x09
|
||||
#define DPCD_TRAINING_SCORE_LANE2 0x0a
|
||||
#define DPCD_TRAINING_SCORE_LANE3 0x0b
|
||||
|
||||
#define DPCD_TEST_REQUEST 0x18
|
||||
#define DPCD_TEST_LINK_RATE 0x19
|
||||
|
||||
#define DPCD_TEST_LANE_COUNT 0x20
|
||||
|
||||
#define DPCD_TEST_Response 0x60
|
||||
#define TEST_ACK 0x01
|
||||
#define DPCD_TEST_EDID_Checksum_Write 0x04//bit position
|
||||
|
||||
#define DPCD_TEST_EDID_Checksum 0x61
|
||||
|
||||
|
||||
#define DPCD_SPECIFIC_INTERRUPT 0x10
|
||||
#define DPCD_USER_COMM1 0x22//define for downstream HDMI Rx sense detection
|
||||
|
||||
|
||||
struct anx6345_platform_data {
|
||||
unsigned int dvdd33_en_pin;
|
||||
int dvdd33_en_val;
|
||||
unsigned int dvdd18_en_pin;
|
||||
int dvdd18_en_val;
|
||||
unsigned int edp_rst_pin;
|
||||
int (*power_ctl)(void);
|
||||
};
|
||||
|
||||
struct edp_anx6345 {
|
||||
struct i2c_client *client;
|
||||
struct anx6345_platform_data *pdata;
|
||||
int (*edp_anx_init)(struct i2c_client *client);
|
||||
rk_screen screen;
|
||||
#ifdef CONFIG_HAS_EARLYSUSPEND
|
||||
struct early_suspend early_suspend;
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -1,15 +1,7 @@
|
||||
#ifndef _DP_TX_Reg_def_H
|
||||
#define _DP_TX_Reg_def_H
|
||||
/***************************************************************/
|
||||
#include <linux/rk_screen.h>
|
||||
#include<linux/earlysuspend.h>
|
||||
#define RK_EDP_SCL_RATE (100*1000)
|
||||
#ifndef _DP_ANX9805_H_
|
||||
#define _DP_ANX9805_H_
|
||||
/**************register define for anx9805 anx9804********/
|
||||
|
||||
#define MAX_REG 0xf0
|
||||
#define MAX_BUF_CNT 6
|
||||
|
||||
#define DP_TX_PORT0_ADDR 0x70
|
||||
#define HDMI_TX_PORT0_ADDR 0x72
|
||||
#define DP_TX_VND_IDL_REG 0x00
|
||||
#define DP_TX_VND_IDH_REG 0x01
|
||||
#define DP_TX_DEV_IDL_REG 0x02
|
||||
Reference in New Issue
Block a user