tvafe: add av/atv/cvbs support for tm2 [1/1]

PD#:SWPL-6702 Problem: tm2 bringup Solution: add av/atv/cvbs support for tm2 Verify: tm2 T962E2 Change-Id: I1c7358cd17463843fbdd7a93c7416a22aaa2387c Signed-off-by: Nian Jing <nian.jing@amlogic.com>
2026-04-03 11:43:03 +09:00 · 2019-04-03 15:33:01 +08:00
parent 2c05842e63
commit bab3adbe76
24 changed files with 253 additions and 68 deletions
--- a/arch/arm/boot/dts/amlogic/mesontm2.dtsi
+++ b/arch/arm/boot/dts/amlogic/mesontm2.dtsi
@@ -1531,7 +1531,7 @@
 	};

 	vdac {
-		compatible = "amlogic, vdac-tl1";
+		compatible = "amlogic, vdac-tm2";
 		status = "okay";
 	};

--- a/arch/arm/boot/dts/amlogic/tm2_pxp.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_pxp.dts
@@ -390,7 +390,7 @@
 	/* Audio Related end */

 	tvafe_avin_detect {
-		compatible = "amlogic, tl1_tvafe_avin_detect";
+		compatible = "amlogic, tm2_tvafe_avin_detect";
 		status = "okay";
 		device_mask = <1>;/*bit0:ch1;bit1:ch2*/
 		interrupts = <0 12 1>,
@@ -482,6 +482,73 @@
 		tv_bit_mode = <0x15>;
 	};

+	tvafe {
+		compatible = "amlogic, tvafe-tm2";
+		/*memory-region = <&tvafe_cma_reserved>;*/
+		status = "okay";
+		flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
+		cma_size = <5>;/*MByte*/
+		reg = <0xff654000 0x2000>;/*tvafe reg base*/
+		reserve-iomap = "true";
+		tvafe_id = <0>;
+		//pinctrl-names = "default";
+		/*!!particular sequence, no more and no less!!!*/
+		tvafe_pin_mux = <
+				3 /* TVAFE_CVBS_IN2, CVBS_IN0 = 0 */
+				1 /* TVAFE_CVBS_IN0, CVBS_IN1 */
+				2 /* TVAFE_CVBS_IN1, CVBS_IN2 */
+				4 /* TVAFE_CVBS_IN3, CVBS_IN3 */
+		>;
+		clocks = <&clkc CLKID_DAC_CLK>;
+		clock-names = "vdac_clk_gate";
+	};
+
+	vbi {
+		compatible = "amlogic, vbi";
+		status = "okay";
+		interrupts = <0 83 1>;
+	};
+
+	cvbsout {
+		compatible = "amlogic, cvbsout-tm2";
+		status = "disabled";
+		clocks = <&clkc CLKID_VCLK2_ENCI
+			&clkc CLKID_VCLK2_VENCI0
+			&clkc CLKID_VCLK2_VENCI1
+			&clkc CLKID_DAC_CLK>;
+		clock-names = "venci_top_gate",
+			"venci_0_gate",
+			"venci_1_gate",
+			"vdac_clk_gate";
+		/* clk path */
+		/* 0:vid_pll vid2_clk */
+		/* 1:gp0_pll vid2_clk */
+		/* 2:vid_pll vid1_clk */
+		/* 3:gp0_pll vid1_clk */
+		clk_path = <0>;
+
+		/* performance: reg_address, reg_value */
+		/* tm2 */
+		performance = <0x1bf0  0x9
+			0x1b56  0x333
+			0x1b12  0x8080
+			0x1b05  0xfd
+			0x1c59  0xf850
+			0xffff  0x0>; /* ending flag */
+		performance_sarft = <0x1bf0  0x9
+			0x1b56  0x333
+			0x1b12  0x0
+			0x1b05  0x9
+			0x1c59  0xfc48
+			0xffff  0x0>; /* ending flag */
+		performance_revB_telecom = <0x1bf0  0x9
+			0x1b56  0x546
+			0x1b12  0x8080
+			0x1b05  0x9
+			0x1c59  0xf850
+			0xffff  0x0>; /* ending flag */
+	};
+
 	hdmirx {
 		compatible = "amlogic, hdmirx_tl1";
 		#address-cells=<1>;
--- a/arch/arm/boot/dts/amlogic/tm2_t962e2_ab311.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_t962e2_ab311.dts
@@ -471,7 +471,7 @@
 	};

 	tvafe_avin_detect {
-		compatible = "amlogic, tl1_tvafe_avin_detect";
+		compatible = "amlogic, tm2_tvafe_avin_detect";
 		status = "okay";
 		device_mask = <1>;/*bit0:ch1;bit1:ch2*/
 		interrupts = <0 12 1>,
@@ -568,7 +568,7 @@
 	};

 	tvafe {
-		compatible = "amlogic, tvafe-tl1";
+		compatible = "amlogic, tvafe-tm2";
 		/*memory-region = <&tvafe_cma_reserved>;*/
 		status = "okay";
 		flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
@@ -595,7 +595,7 @@
 	};

 	cvbsout {
-		compatible = "amlogic, cvbsout-tl1";
+		compatible = "amlogic, cvbsout-tm2";
 		status = "disabled";
 		clocks = <&clkc CLKID_VCLK2_ENCI
 			&clkc CLKID_VCLK2_VENCI0
@@ -613,7 +613,7 @@
 		clk_path = <0>;

 		/* performance: reg_address, reg_value */
-		/* tl1 */
+		/* tm2 */
 		performance = <0x1bf0  0x9
 			0x1b56  0x333
 			0x1b12  0x8080
--- a/arch/arm/boot/dts/amlogic/tm2_t962e2_ab319.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_t962e2_ab319.dts
@@ -459,7 +459,7 @@
 	};

 	tvafe_avin_detect {
-		compatible = "amlogic, tl1_tvafe_avin_detect";
+		compatible = "amlogic, tm2_tvafe_avin_detect";
 		status = "okay";
 		device_mask = <1>;/*bit0:ch1;bit1:ch2*/
 		interrupts = <0 12 1>,
@@ -556,7 +556,7 @@
 	};

 	tvafe {
-		compatible = "amlogic, tvafe-tl1";
+		compatible = "amlogic, tvafe-tm2";
 		/*memory-region = <&tvafe_cma_reserved>;*/
 		status = "okay";
 		flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
@@ -583,7 +583,7 @@
 	};

 	cvbsout {
-		compatible = "amlogic, cvbsout-tl1";
+		compatible = "amlogic, cvbsout-tm2";
 		status = "disabled";
 		clocks = <&clkc CLKID_VCLK2_ENCI
 			&clkc CLKID_VCLK2_VENCI0
@@ -601,7 +601,7 @@
 		clk_path = <0>;

 		/* performance: reg_address, reg_value */
-		/* tl1 */
+		/* tm2 */
 		performance = <0x1bf0  0x9
 			0x1b56  0x333
 			0x1b12  0x8080
--- a/arch/arm/boot/dts/amlogic/tm2_t962x3_ab301.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_t962x3_ab301.dts
@@ -471,7 +471,7 @@
 	};

 	tvafe_avin_detect {
-		compatible = "amlogic, tl1_tvafe_avin_detect";
+		compatible = "amlogic, tm2_tvafe_avin_detect";
 		status = "okay";
 		device_mask = <1>;/*bit0:ch1;bit1:ch2*/
 		interrupts = <0 12 1>,
@@ -568,7 +568,7 @@
 	};

 	tvafe {
-		compatible = "amlogic, tvafe-tl1";
+		compatible = "amlogic, tvafe-tm2";
 		/*memory-region = <&tvafe_cma_reserved>;*/
 		status = "okay";
 		flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
@@ -595,7 +595,7 @@
 	};

 	cvbsout {
-		compatible = "amlogic, cvbsout-tl1";
+		compatible = "amlogic, cvbsout-tm2";
 		status = "disabled";
 		clocks = <&clkc CLKID_VCLK2_ENCI
 			&clkc CLKID_VCLK2_VENCI0
@@ -613,7 +613,7 @@
 		clk_path = <0>;

 		/* performance: reg_address, reg_value */
-		/* tl1 */
+		/* tm2 */
 		performance = <0x1bf0  0x9
 			0x1b56  0x333
 			0x1b12  0x8080
--- a/arch/arm/boot/dts/amlogic/tm2_t962x3_ab309.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_t962x3_ab309.dts
@@ -459,7 +459,7 @@
 	};

 	tvafe_avin_detect {
-		compatible = "amlogic, tl1_tvafe_avin_detect";
+		compatible = "amlogic, tm2_tvafe_avin_detect";
 		status = "okay";
 		device_mask = <1>;/*bit0:ch1;bit1:ch2*/
 		interrupts = <0 12 1>,
@@ -556,7 +556,7 @@
 	};

 	tvafe {
-		compatible = "amlogic, tvafe-tl1";
+		compatible = "amlogic, tvafe-tm2";
 		/*memory-region = <&tvafe_cma_reserved>;*/
 		status = "okay";
 		flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
@@ -583,7 +583,7 @@
 	};

 	cvbsout {
-		compatible = "amlogic, cvbsout-tl1";
+		compatible = "amlogic, cvbsout-tm2";
 		status = "disabled";
 		clocks = <&clkc CLKID_VCLK2_ENCI
 			&clkc CLKID_VCLK2_VENCI0
@@ -601,7 +601,7 @@
 		clk_path = <0>;

 		/* performance: reg_address, reg_value */
-		/* tl1 */
+		/* tm2 */
 		performance = <0x1bf0  0x9
 			0x1b56  0x333
 			0x1b12  0x8080
--- a/arch/arm64/boot/dts/amlogic/mesontm2.dtsi
+++ b/arch/arm64/boot/dts/amlogic/mesontm2.dtsi
@@ -1511,7 +1511,7 @@
 	};

 	vdac {
-		compatible = "amlogic, vdac-tl1";
+		compatible = "amlogic, vdac-tm2";
 		status = "okay";
 	};

--- a/arch/arm64/boot/dts/amlogic/tm2_pxp.dts
+++ b/arch/arm64/boot/dts/amlogic/tm2_pxp.dts
@@ -389,7 +389,7 @@
 	/* Audio Related end */

 	tvafe_avin_detect {
-		compatible = "amlogic, tl1_tvafe_avin_detect";
+		compatible = "amlogic, tm2_tvafe_avin_detect";
 		status = "okay";
 		device_mask = <1>;/*bit0:ch1;bit1:ch2*/
 		interrupts = <0 12 1>,
@@ -482,6 +482,73 @@
 		tv_bit_mode = <0x15>;
 	};

+	tvafe {
+		compatible = "amlogic, tvafe-tm2";
+		/*memory-region = <&tvafe_cma_reserved>;*/
+		status = "okay";
+		flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
+		cma_size = <5>;/*MByte*/
+		reg = <0xff654000 0x2000>;/*tvafe reg base*/
+		reserve-iomap = "true";
+		tvafe_id = <0>;
+		//pinctrl-names = "default";
+		/*!!particular sequence, no more and no less!!!*/
+		tvafe_pin_mux = <
+				3 /* TVAFE_CVBS_IN2, CVBS_IN0 = 0 */
+				1 /* TVAFE_CVBS_IN0, CVBS_IN1 */
+				2 /* TVAFE_CVBS_IN1, CVBS_IN2 */
+				4 /* TVAFE_CVBS_IN3, CVBS_IN3 */
+		>;
+		clocks = <&clkc CLKID_DAC_CLK>;
+		clock-names = "vdac_clk_gate";
+	};
+
+	vbi {
+		compatible = "amlogic, vbi";
+		status = "okay";
+		interrupts = <0 83 1>;
+	};
+
+	cvbsout {
+		compatible = "amlogic, cvbsout-tm2";
+		status = "disabled";
+		clocks = <&clkc CLKID_VCLK2_ENCI
+			&clkc CLKID_VCLK2_VENCI0
+			&clkc CLKID_VCLK2_VENCI1
+			&clkc CLKID_DAC_CLK>;
+		clock-names = "venci_top_gate",
+			"venci_0_gate",
+			"venci_1_gate",
+			"vdac_clk_gate";
+		/* clk path */
+		/* 0:vid_pll vid2_clk */
+		/* 1:gp0_pll vid2_clk */
+		/* 2:vid_pll vid1_clk */
+		/* 3:gp0_pll vid1_clk */
+		clk_path = <0>;
+
+		/* performance: reg_address, reg_value */
+		/* tm2 */
+		performance = <0x1bf0  0x9
+			0x1b56  0x333
+			0x1b12  0x8080
+			0x1b05  0xfd
+			0x1c59  0xf850
+			0xffff  0x0>; /* ending flag */
+		performance_sarft = <0x1bf0  0x9
+			0x1b56  0x333
+			0x1b12  0x0
+			0x1b05  0x9
+			0x1c59  0xfc48
+			0xffff  0x0>; /* ending flag */
+		performance_revB_telecom = <0x1bf0  0x9
+			0x1b56  0x546
+			0x1b12  0x8080
+			0x1b05  0x9
+			0x1c59  0xf850
+			0xffff  0x0>; /* ending flag */
+	};
+
 	hdmirx {
 		compatible = "amlogic, hdmirx_tl1";
 		#address-cells=<1>;
--- a/arch/arm64/boot/dts/amlogic/tm2_t962e2_ab311.dts
+++ b/arch/arm64/boot/dts/amlogic/tm2_t962e2_ab311.dts
@@ -466,7 +466,7 @@
 	};

 	tvafe_avin_detect {
-		compatible = "amlogic, tl1_tvafe_avin_detect";
+		compatible = "amlogic, tm2_tvafe_avin_detect";
 		status = "okay";
 		device_mask = <1>;/*bit0:ch1;bit1:ch2*/
 		interrupts = <0 12 1>,
@@ -563,7 +563,7 @@
 	};

 	tvafe {
-		compatible = "amlogic, tvafe-tl1";
+		compatible = "amlogic, tvafe-tm2";
 		/*memory-region = <&tvafe_cma_reserved>;*/
 		status = "okay";
 		flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
@@ -590,7 +590,7 @@
 	};

 	cvbsout {
-		compatible = "amlogic, cvbsout-tl1";
+		compatible = "amlogic, cvbsout-tm2";
 		status = "disabled";
 		clocks = <&clkc CLKID_VCLK2_ENCI
 			&clkc CLKID_VCLK2_VENCI0
@@ -608,7 +608,7 @@
 		clk_path = <0>;

 		/* performance: reg_address, reg_value */
-		/* tl1 */
+		/* tm2 */
 		performance = <0x1bf0  0x9
 			0x1b56  0x333
 			0x1b12  0x8080
--- a/arch/arm64/boot/dts/amlogic/tm2_t962e2_ab319.dts
+++ b/arch/arm64/boot/dts/amlogic/tm2_t962e2_ab319.dts
@@ -458,7 +458,7 @@
 	};

 	tvafe_avin_detect {
-		compatible = "amlogic, tl1_tvafe_avin_detect";
+		compatible = "amlogic, tm2_tvafe_avin_detect";
 		status = "okay";
 		device_mask = <1>;/*bit0:ch1;bit1:ch2*/
 		interrupts = <0 12 1>,
@@ -555,7 +555,7 @@
 	};

 	tvafe {
-		compatible = "amlogic, tvafe-tl1";
+		compatible = "amlogic, tvafe-tm2";
 		/*memory-region = <&tvafe_cma_reserved>;*/
 		status = "okay";
 		flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
@@ -582,7 +582,7 @@
 	};

 	cvbsout {
-		compatible = "amlogic, cvbsout-tl1";
+		compatible = "amlogic, cvbsout-tm2";
 		status = "disabled";
 		clocks = <&clkc CLKID_VCLK2_ENCI
 			&clkc CLKID_VCLK2_VENCI0
@@ -600,7 +600,7 @@
 		clk_path = <0>;

 		/* performance: reg_address, reg_value */
-		/* tl1 */
+		/* tm2 */
 		performance = <0x1bf0  0x9
 			0x1b56  0x333
 			0x1b12  0x8080
--- a/arch/arm64/boot/dts/amlogic/tm2_t962x3_ab301.dts
+++ b/arch/arm64/boot/dts/amlogic/tm2_t962x3_ab301.dts
@@ -458,7 +458,7 @@
 	};

 	tvafe_avin_detect {
-		compatible = "amlogic, tl1_tvafe_avin_detect";
+		compatible = "amlogic, tm2_tvafe_avin_detect";
 		status = "okay";
 		device_mask = <1>;/*bit0:ch1;bit1:ch2*/
 		interrupts = <0 12 1>,
@@ -555,7 +555,7 @@
 	};

 	tvafe {
-		compatible = "amlogic, tvafe-tl1";
+		compatible = "amlogic, tvafe-tm2";
 		/*memory-region = <&tvafe_cma_reserved>;*/
 		status = "okay";
 		flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
@@ -582,7 +582,7 @@
 	};

 	cvbsout {
-		compatible = "amlogic, cvbsout-tl1";
+		compatible = "amlogic, cvbsout-tm2";
 		status = "disabled";
 		clocks = <&clkc CLKID_VCLK2_ENCI
 			&clkc CLKID_VCLK2_VENCI0
@@ -600,7 +600,7 @@
 		clk_path = <0>;

 		/* performance: reg_address, reg_value */
-		/* tl1 */
+		/* tm2 */
 		performance = <0x1bf0  0x9
 			0x1b56  0x333
 			0x1b12  0x8080
--- a/arch/arm64/boot/dts/amlogic/tm2_t962x3_ab309.dts
+++ b/arch/arm64/boot/dts/amlogic/tm2_t962x3_ab309.dts
@@ -458,7 +458,7 @@
 	};

 	tvafe_avin_detect {
-		compatible = "amlogic, tl1_tvafe_avin_detect";
+		compatible = "amlogic, tm2_tvafe_avin_detect";
 		status = "okay";
 		device_mask = <1>;/*bit0:ch1;bit1:ch2*/
 		interrupts = <0 12 1>,
@@ -555,7 +555,7 @@
 	};

 	tvafe {
-		compatible = "amlogic, tvafe-tl1";
+		compatible = "amlogic, tvafe-tm2";
 		/*memory-region = <&tvafe_cma_reserved>;*/
 		status = "okay";
 		flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
@@ -582,7 +582,7 @@
 	};

 	cvbsout {
-		compatible = "amlogic, cvbsout-tl1";
+		compatible = "amlogic, cvbsout-tm2";
 		status = "disabled";
 		clocks = <&clkc CLKID_VCLK2_ENCI
 			&clkc CLKID_VCLK2_VENCI0
@@ -600,7 +600,7 @@
 		clk_path = <0>;

 		/* performance: reg_address, reg_value */
-		/* tl1 */
+		/* tm2 */
 		performance = <0x1bf0  0x9
 			0x1b56  0x333
 			0x1b12  0x8080
--- a/drivers/amlogic/media/vin/tvin/tvafe/tvafe.c
+++ b/drivers/amlogic/media/vin/tvin/tvafe/tvafe.c
@@ -261,7 +261,8 @@ int tvafe_dec_open(struct tvin_frontend_s *fe, enum tvin_port_e port)
 #ifdef CONFIG_AMLOGIC_MEDIA_TVIN_AVDETECT
 	/*only txlx chip enabled*/
 	if (tvafe_cpu_type() == CPU_TYPE_TXLX ||
-		tvafe_cpu_type() == CPU_TYPE_TL1) {
+		tvafe_cpu_type() == CPU_TYPE_TL1 ||
+		tvafe_cpu_type() == CPU_TYPE_TM2) {
 		/*synctip set to 0 when tvafe working&&av connected*/
 		/*enable clamp if av connected*/
 		if (port == TVIN_PORT_CVBS1) {
@@ -356,7 +357,8 @@ void tvafe_dec_start(struct tvin_frontend_s *fe, enum tvin_sig_fmt_e fmt)

 #ifdef CONFIG_AMLOGIC_MEDIA_TVIN_AVDETECT
 	if (tvafe_cpu_type() == CPU_TYPE_TXLX ||
-		tvafe_cpu_type() == CPU_TYPE_TL1) {
+		tvafe_cpu_type() == CPU_TYPE_TL1 ||
+		tvafe_cpu_type() == CPU_TYPE_TM2) {
 		if (port == TVIN_PORT_CVBS1)
 			tvafe_avin_detect_ch1_anlog_enable(0);
 		else if (port == TVIN_PORT_CVBS2)
@@ -423,7 +425,8 @@ void tvafe_dec_stop(struct tvin_frontend_s *fe, enum tvin_port_e port)
 	}
 #ifdef CONFIG_AMLOGIC_MEDIA_TVIN_AVDETECT
 	if (tvafe_cpu_type() == CPU_TYPE_TXLX ||
-		tvafe_cpu_type() == CPU_TYPE_TL1) {
+		tvafe_cpu_type() == CPU_TYPE_TL1 ||
+		tvafe_cpu_type() == CPU_TYPE_TM2) {
 		if (port == TVIN_PORT_CVBS1)
 			tvafe_avin_detect_ch1_anlog_enable(1);
 		else if (port == TVIN_PORT_CVBS2)
@@ -492,7 +495,8 @@ void tvafe_dec_close(struct tvin_frontend_s *fe)
 #endif
 #ifdef CONFIG_AMLOGIC_MEDIA_TVIN_AVDETECT
 	if (tvafe_cpu_type() == CPU_TYPE_TXLX ||
-		tvafe_cpu_type() == CPU_TYPE_TL1) {
+		tvafe_cpu_type() == CPU_TYPE_TL1 ||
+		tvafe_cpu_type() == CPU_TYPE_TM2) {
 		/*avsync tip set 1 to resume av detect*/
 		if (tvafe->parm.port == TVIN_PORT_CVBS1) {
 			avport_opened = 0;
@@ -1203,6 +1207,11 @@ struct meson_tvafe_data meson_tl1_tvafe_data = {
 	.name = "meson-tl1-tvafe",
 };

+struct meson_tvafe_data meson_tm2_tvafe_data = {
+	.cpu_id = CPU_TYPE_TM2,
+	.name = "meson-tm2-tvafe",
+};
+
 static const struct of_device_id meson_tvafe_dt_match[] = {
 	{
 		.compatible = "amlogic, tvafe-gxtvbb",
@@ -1219,6 +1228,9 @@ static const struct of_device_id meson_tvafe_dt_match[] = {
 	}, {
 		.compatible = "amlogic, tvafe-tl1",
 		.data		= &meson_tl1_tvafe_data,
+	}, {
+		.compatible = "amlogic, tvafe-tm2",
+		.data		= &meson_tm2_tvafe_data,
 	},
 	{},
 };
--- a/drivers/amlogic/media/vin/tvin/tvafe/tvafe_avin_detect.c
+++ b/drivers/amlogic/media/vin/tvin/tvafe/tvafe_avin_detect.c
@@ -933,12 +933,20 @@ struct meson_avin_data tl1_data = {
 	.name = "meson-tl1-avin-detect",
 };

+struct meson_avin_data tm2_data = {
+	.cpu_id = AVIN_CPU_TYPE_TM2,
+	.name = "meson-tm2-avin-detect",
+};
+
 static const struct of_device_id tvafe_avin_dt_match[] = {
 	{	.compatible = "amlogic, tvafe_avin_detect",
 	},
 	{	.compatible = "amlogic, tl1_tvafe_avin_detect",
 		.data = &tl1_data,
 	},
+	{	.compatible = "amlogic, tm2_tvafe_avin_detect",
+		.data = &tm2_data,
+	},
 	{},
 };
 #else
--- a/drivers/amlogic/media/vin/tvin/tvafe/tvafe_avin_detect.h
+++ b/drivers/amlogic/media/vin/tvin/tvafe/tvafe_avin_detect.h
@@ -136,6 +136,7 @@ enum avin_cpu_type {
 	AVIN_CPU_TYPE_TXLX   = 1,
 	AVIN_CPU_TYPE_TXHD   = 2,
 	AVIN_CPU_TYPE_TL1   = 3,
+	AVIN_CPU_TYPE_TM2   = 4,
 	AVIN_CPU_TYPE_MAX,
 };

--- a/drivers/amlogic/media/vin/tvin/tvafe/tvafe_cvd.c
+++ b/drivers/amlogic/media/vin/tvin/tvafe/tvafe_cvd.c
@@ -421,7 +421,8 @@ static void tvafe_cvd2_write_mode_reg(struct tvafe_cvd2_s *cvd2,
 	/*setting for txhd snow*/
 	if (tvafe_get_snow_cfg() &&
 		(tvafe_cpu_type() == CPU_TYPE_TXHD ||
-		tvafe_cpu_type() == CPU_TYPE_TL1)) {
+		tvafe_cpu_type() == CPU_TYPE_TL1 ||
+		tvafe_cpu_type() == CPU_TYPE_TM2)) {
 		W_APB_BIT(CVD2_OUTPUT_CONTROL, 3, 5, 2);
 		W_APB_REG(ACD_REG_6C, 0x80500000);
 	}
@@ -2621,7 +2622,8 @@ void tvafe_snow_config(unsigned int onoff)
 {
 	if (tvafe_snow_function_flag == 0 ||
 		tvafe_cpu_type() == CPU_TYPE_TXHD ||
-		tvafe_cpu_type() == CPU_TYPE_TL1)
+		tvafe_cpu_type() == CPU_TYPE_TL1 ||
+		tvafe_cpu_type() == CPU_TYPE_TM2)
 		return;
 	if (onoff)
 		W_APB_BIT(CVD2_OUTPUT_CONTROL, 3, BLUE_MODE_BIT, BLUE_MODE_WID);
@@ -2632,7 +2634,8 @@ void tvafe_snow_config(unsigned int onoff)
 void tvafe_snow_config_clamp(unsigned int onoff)
 {
 	if (tvafe_cpu_type() == CPU_TYPE_TXHD ||
-		tvafe_cpu_type() == CPU_TYPE_TL1) {
+		tvafe_cpu_type() == CPU_TYPE_TL1 ||
+		tvafe_cpu_type() == CPU_TYPE_TM2) {
 		if (onoff)
 			vdin_adjust_tvafesnow_brightness();
 		return;
--- a/drivers/amlogic/media/vin/tvin/tvafe/tvafe_general.c
+++ b/drivers/amlogic/media/vin/tvin/tvafe/tvafe_general.c
@@ -245,14 +245,14 @@ static enum tvafe_adc_ch_e tvafe_adc_pin_muxing(
 	if (tvafe_cpu_type() == CPU_TYPE_TXL ||
 		tvafe_cpu_type() == CPU_TYPE_TXLX ||
 		tvafe_cpu_type() == CPU_TYPE_TXHD ||
-		tvafe_cpu_type() == CPU_TYPE_TL1) {
+		tvafe_cpu_type() >= CPU_TYPE_TL1) {
 		tvafe_pr_info("[tvafe]%s:pin:%d\n",
 			__func__, (unsigned int)pin);
 		if (pin == TVAFE_CVBS_IN0) {

 			W_APB_BIT(TVFE_VAFE_CTRL1, 1,
 				VAFE_IN_SEL_BIT, VAFE_IN_SEL_WID);
-			if (tvafe_cpu_type() != CPU_TYPE_TL1)
+			if (tvafe_cpu_type() < CPU_TYPE_TL1)
 				W_APB_BIT(TVFE_VAFE_CTRL2, 3, 4, 3);
 			ret = TVAFE_ADC_CH_0;

@@ -260,7 +260,7 @@ static enum tvafe_adc_ch_e tvafe_adc_pin_muxing(

 			W_APB_BIT(TVFE_VAFE_CTRL1, 2,
 				VAFE_IN_SEL_BIT, VAFE_IN_SEL_WID);
-			if (tvafe_cpu_type() != CPU_TYPE_TL1)
+			if (tvafe_cpu_type() < CPU_TYPE_TL1)
 				W_APB_BIT(TVFE_VAFE_CTRL2, 5, 4, 3);
 			ret = TVAFE_ADC_CH_1;

@@ -384,7 +384,7 @@ static void tvafe_set_cvbs_default(struct tvafe_cvd2_s *cvd2,
 	unsigned int i = 0;

 	/**disable auto mode clock**/
-	if (tvafe_cpu_type() != CPU_TYPE_TL1)
+	if (tvafe_cpu_type() < CPU_TYPE_TL1)
 		W_HIU_REG(HHI_TVFE_AUTOMODE_CLK_CNTL, 0);

 	/*config adc*/
@@ -400,7 +400,7 @@ static void tvafe_set_cvbs_default(struct tvafe_cvd2_s *cvd2,
 			W_HIU_REG(HHI_DADC_CNTL, 0x00102038);
 			W_HIU_REG(HHI_DADC_CNTL2, 0x00000401);
 			W_HIU_REG(HHI_DADC_CNTL3, 0x00082183);
-		} else if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+		} else if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
 			/** DADC CNTL for LIF signal input **/
 			W_HIU_REG(HHI_DADC_CNTL, 0x0030303c);
 			W_HIU_REG(HHI_DADC_CNTL2, 0x00003480);
@@ -421,7 +421,7 @@ static void tvafe_set_cvbs_default(struct tvafe_cvd2_s *cvd2,
 			W_HIU_REG(HHI_DADC_CNTL, 0x00102038);
 			W_HIU_REG(HHI_DADC_CNTL2, 0x00000400);
 			W_HIU_REG(HHI_DADC_CNTL3, 0x00082183);
-		} else if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+		} else if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
 			W_HIU_REG(HHI_DADC_CNTL, 0x0030303c);
 			W_HIU_REG(HHI_DADC_CNTL2, 0x00003400);
 			W_HIU_REG(HHI_DADC_CNTL3, 0x08300b83);
@@ -440,8 +440,8 @@ static void tvafe_set_cvbs_default(struct tvafe_cvd2_s *cvd2,
 	if (tvafe_cpu_type() == CPU_TYPE_TXL ||
 		tvafe_cpu_type() == CPU_TYPE_TXLX ||
 		tvafe_cpu_type() == CPU_TYPE_TXHD ||
-		tvafe_cpu_type() == CPU_TYPE_TL1) {
-		if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+		tvafe_cpu_type() >= CPU_TYPE_TL1) {
+		if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
 			if (port == TVIN_PORT_CVBS3) {
 				W_APB_REG(TVFE_VAFE_CTRL0, 0x000d0710);
 				W_APB_REG(TVFE_VAFE_CTRL1, 0x00003000);
@@ -550,7 +550,7 @@ void tvafe_set_ddemod_default(void)
 		W_APB_REG(TVFE_VAFE_CTRL0, 0x000d0710);
 		W_APB_REG(TVFE_VAFE_CTRL1, 0x0);
 		W_APB_REG(TVFE_VAFE_CTRL2, 0x1010eeb0);
-	} else if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+	} else if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
 		W_APB_REG(TVFE_VAFE_CTRL0, 0x000d0710);
 		W_APB_REG(TVFE_VAFE_CTRL1, 0x3000);
 		W_APB_REG(TVFE_VAFE_CTRL2, 0x1fe09e31);
@@ -571,7 +571,7 @@ void tvafe_enable_avout(enum tvin_port_e port, bool enable)
 	if (tvafe_cpu_type() == CPU_TYPE_TXL ||
 		tvafe_cpu_type() == CPU_TYPE_TXLX ||
 		tvafe_cpu_type() == CPU_TYPE_TXHD ||
-		tvafe_cpu_type() == CPU_TYPE_TL1) {
+		tvafe_cpu_type() >= CPU_TYPE_TL1) {
 		if (enable) {
 			tvafe_clk_gate_ctrl(1);
 			if (port == TVIN_PORT_CVBS3) {
@@ -642,7 +642,7 @@ int adc_set_pll_cntl(bool on, unsigned int module_sel, void *pDtvPara)
 			break;
 		}
 		mutex_lock(&pll_mutex);
-		if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+		if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
 			do {
 				W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x012004e0);
 				W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x312004e0);
@@ -705,7 +705,7 @@ int adc_set_pll_cntl(bool on, unsigned int module_sel, void *pDtvPara)
 			break;
 		}
 		mutex_lock(&pll_mutex);
-		if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+		if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
 			do {
 				W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x012004e0);
 				W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x312004e0);
@@ -796,7 +796,7 @@ int adc_set_pll_cntl(bool on, unsigned int module_sel, void *pDtvPara)
 			break;
 		}
 		mutex_lock(&pll_mutex);
-		if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+		if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
 			do {
 				W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x012004e0);
 				W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x312004e0);
@@ -910,7 +910,7 @@ int adc_set_pll_cntl(bool on, unsigned int module_sel, void *pDtvPara)
 			W_HIU_REG(HHI_DEMOD_CLK_CNTL, 0x1000502);

 			adc_pll_lock_cnt = 1;
-		} else if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+		} else if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
 			do {//25M
 				W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x001104c8);
 				W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x301104c8);
@@ -995,7 +995,7 @@ void tvafe_init_reg(struct tvafe_cvd2_s *cvd2,
 	if ((port >= TVIN_PORT_CVBS0) && (port <= TVIN_PORT_CVBS3)) {

 #ifdef CRYSTAL_25M
-	if (tvafe_cpu_type() != CPU_TYPE_TL1)
+	if (tvafe_cpu_type() < CPU_TYPE_TL1)
 		W_HIU_REG(HHI_VAFE_CLKIN_CNTL, 0x703);/* can't write !!! */
 #endif

@@ -1055,7 +1055,7 @@ void tvafe_enable_module(bool enable)
 	/* enable */

 	/* main clk up */
-	if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+	if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
 		W_HIU_BIT(HHI_ATV_DMD_SYS_CLK_CNTL, 1,
 			VAFE_CLK_SELECT, VAFE_CLK_SELECT_WIDTH);
 		W_HIU_BIT(HHI_ATV_DMD_SYS_CLK_CNTL, 1,
@@ -1098,7 +1098,7 @@ void tvafe_enable_module(bool enable)
 			TVFE_ADC_CLK_DIV_WID);

 		/* main clk down */
-		if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+		if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
 			W_HIU_BIT(HHI_ATV_DMD_SYS_CLK_CNTL, 0,
 				VAFE_CLK_SELECT, VAFE_CLK_SELECT_WIDTH);
 			W_HIU_BIT(HHI_ATV_DMD_SYS_CLK_CNTL, 0,
--- a/drivers/amlogic/media/vin/tvin/tvafe/tvafe_general.h
+++ b/drivers/amlogic/media/vin/tvin/tvafe/tvafe_general.h
@@ -159,6 +159,7 @@ enum tvafe_cpu_type {
 	CPU_TYPE_TXHD = 3,
 	CPU_TYPE_GXLX = 4,
 	CPU_TYPE_TL1 = 5,
+	CPU_TYPE_TM2 = 6,
 };

 struct meson_tvafe_data {
--- a/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c
+++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c
@@ -1554,9 +1554,10 @@ static void vdin_set_color_matrix0_g12a(unsigned int offset,
 			VDIN_MATRIX_COEF_INDEX_BIT, VDIN_MATRIX_COEF_INDEX_WID);

 		wr(offset,
-			VDIN_MATRIX_PRE_OFFSET0_1, matrix_tbl->pre_offset0_1);
+			VDIN_HDR2_MATRIXI_PRE_OFFSET0_1,
+				matrix_tbl->pre_offset0_1);
 		wr(offset,
-			VDIN_MATRIX_PRE_OFFSET2, matrix_tbl->pre_offset2);
+			VDIN_HDR2_MATRIXI_PRE_OFFSET2, matrix_tbl->pre_offset2);
 		wr(offset, VDIN_HDR2_MATRIXI_COEF00_01, matrix_tbl->coef00_01);
 		wr(offset, VDIN_HDR2_MATRIXI_COEF02_10, matrix_tbl->coef02_10);
 		wr(offset, VDIN_HDR2_MATRIXI_COEF11_12, matrix_tbl->coef11_12);
--- a/drivers/amlogic/media/vout/cvbs/cvbs_out.c
+++ b/drivers/amlogic/media/vout/cvbs/cvbs_out.c
@@ -1458,6 +1458,12 @@ struct meson_cvbsout_data meson_sm1_cvbsout_data = {
 	.name = "meson-sm1-cvbsout",
 };

+struct meson_cvbsout_data meson_tm2_cvbsout_data = {
+	.cntl0_val = 0x906001,
+	.cpu_id = CVBS_CPU_TYPE_TM2,
+	.name = "meson-tm2-cvbsout",
+};
+
 static const struct of_device_id meson_cvbsout_dt_match[] = {
 	{
 		.compatible = "amlogic, cvbsout-gxl",
@@ -1480,6 +1486,9 @@ static const struct of_device_id meson_cvbsout_dt_match[] = {
 	}, {
 		.compatible = "amlogic, cvbsout-sm1",
 		.data		= &meson_sm1_cvbsout_data,
+	}, {
+		.compatible = "amlogic, cvbsout-tm2",
+		.data		= &meson_tm2_cvbsout_data,
 	},
 	{},
 };
--- a/drivers/amlogic/media/vout/cvbs/cvbs_out.h
+++ b/drivers/amlogic/media/vout/cvbs/cvbs_out.h
@@ -53,6 +53,7 @@ enum cvbs_cpu_type {
 	CVBS_CPU_TYPE_G12B   = 5,
 	CVBS_CPU_TYPE_TL1    = 6,
 	CVBS_CPU_TYPE_SM1	 = 7,
+	CVBS_CPU_TYPE_TM2	 = 8,
 };

 struct meson_cvbsout_data {
--- a/drivers/amlogic/media/vout/cvbs/enc_clk_config.c
+++ b/drivers/amlogic/media/vout/cvbs/enc_clk_config.c
@@ -214,7 +214,8 @@ void set_vmode_clk(void)
 		}
 		if (ret)
 			pr_info("[error]:hdmi_pll lock failed\n");
-	} else if (cvbs_cpu_type() == CVBS_CPU_TYPE_TL1) {
+	} else if (cvbs_cpu_type() == CVBS_CPU_TYPE_TL1 ||
+		cvbs_cpu_type() == CVBS_CPU_TYPE_TM2) {
 		cvbs_out_hiu_write(HHI_TCON_PLL_CNTL0,	0x202f04f7);
 		udelay(100);
 		cvbs_out_hiu_write(HHI_TCON_PLL_CNTL0,	0x302f04f7);
@@ -257,7 +258,8 @@ void set_vmode_clk(void)
 			cvbs_set_vid1_clk(cvbs_clk_path & 0x1);
 		else
 			cvbs_set_vid2_clk(cvbs_clk_path & 0x1);
-	} else if (cvbs_cpu_type() == CVBS_CPU_TYPE_TL1) {
+	} else if (cvbs_cpu_type() == CVBS_CPU_TYPE_TL1 ||
+		cvbs_cpu_type() == CVBS_CPU_TYPE_TM2) {
 		if (cvbs_clk_path & 0x2)
 			cvbs_set_vid1_clk(0);
 		else
--- a/drivers/amlogic/media/vout/vdac/vdac_dev.c
+++ b/drivers/amlogic/media/vout/vdac/vdac_dev.c
@@ -443,14 +443,16 @@ void vdac_enable(bool on, unsigned int module_sel)
 				break;
 			vdac_out_cntl1_bit3(0, VDAC_MODULE_TVAFE);
 			vdac_out_cntl0_bit10(1, VDAC_MODULE_TVAFE);
-			if (s_vdac_data->cpu_id == VDAC_CPU_TL1) {
+			if (s_vdac_data->cpu_id == VDAC_CPU_TL1 ||
+				s_vdac_data->cpu_id == VDAC_CPU_TM2) {
 				/*[6][8]bypass buffer enable*/
 				vdac_hiu_reg_setb(HHI_VDAC_CNTL1_G12A, 1, 6, 1);
 				vdac_hiu_reg_setb(HHI_VDAC_CNTL1_G12A, 1, 8, 1);
 			}
 		} else {
 			ana_ref_cntl0_bit9(0, VDAC_MODULE_TVAFE);
-			if (s_vdac_data->cpu_id == VDAC_CPU_TL1) {
+			if (s_vdac_data->cpu_id == VDAC_CPU_TL1 ||
+				s_vdac_data->cpu_id == VDAC_CPU_TM2) {
 				/*[6][8]bypass buffer disable*/
 				vdac_hiu_reg_setb(HHI_VDAC_CNTL1_G12A, 0, 6, 1);
 				vdac_hiu_reg_setb(HHI_VDAC_CNTL1_G12A, 0, 8, 1);
@@ -594,6 +596,11 @@ struct meson_vdac_data meson_sm1_vdac_data = {
 	.name = "meson-sm1-vdac",
 };

+struct meson_vdac_data meson_tm2_vdac_data = {
+	.cpu_id = VDAC_CPU_TM2,
+	.name = "meson-tm2-vdac",
+};
+
 static const struct of_device_id meson_vdac_dt_match[] = {
 	{
 		.compatible = "amlogic, vdac-gxtvbb",
@@ -628,6 +635,9 @@ static const struct of_device_id meson_vdac_dt_match[] = {
 	}, {
 		.compatible = "amlogic, vdac-sm1",
 		.data		= &meson_sm1_vdac_data,
+	}, {
+		.compatible = "amlogic, vdac-tm2",
+		.data		= &meson_tm2_vdac_data,
 	},
 	{},
 };
@@ -712,7 +722,8 @@ static int amvdac_drv_suspend(struct platform_device *pdev,
 	if (s_vdac_data->cpu_id == VDAC_CPU_TXL ||
 		s_vdac_data->cpu_id == VDAC_CPU_TXLX)
 		vdac_hiu_reg_write(HHI_VDAC_CNTL0, 0);
-	else if (s_vdac_data->cpu_id == VDAC_CPU_TL1)
+	else if (s_vdac_data->cpu_id == VDAC_CPU_TL1 ||
+		s_vdac_data->cpu_id == VDAC_CPU_TM2)
 		vdac_hiu_reg_setb(HHI_VDAC_CNTL1_G12A, 1, 7, 1);
 	pr_info("%s: suspend module\n", __func__);
 	return 0;
@@ -721,7 +732,8 @@ static int amvdac_drv_suspend(struct platform_device *pdev,
 static int amvdac_drv_resume(struct platform_device *pdev)
 {
 	/*0xbc[7] for bandgap enable: 0:enable,1:disable*/
-	if (s_vdac_data->cpu_id == VDAC_CPU_TL1)
+	if (s_vdac_data->cpu_id == VDAC_CPU_TL1 ||
+		s_vdac_data->cpu_id == VDAC_CPU_TM2)
 		vdac_hiu_reg_setb(HHI_VDAC_CNTL1_G12A, 0, 7, 1);
 	pr_info("%s: resume module\n", __func__);
 	return 0;
--- a/include/linux/amlogic/media/vout/vdac_dev.h
+++ b/include/linux/amlogic/media/vout/vdac_dev.h
@@ -28,6 +28,7 @@ enum vdac_cpu_type {
 	VDAC_CPU_G12AB = 6,
 	VDAC_CPU_TL1 = 7,
 	VDAC_CPU_SM1 = 8,
+	VDAC_CPU_TM2 = 9,
 	VDAC_CPU_MAX,
 };