irq-gic: read AIAR instead of IAR when FIQ_GLUE is enable

If FIQ_GLUE is enable, uart interrupt is group0, but all
other interrupts are group1. AIAR is for group1, IAR is
for group0 and group1. We need IRQ handles group1 interrupts
only, FIQ handles group0 interrupts.

Fixes: 4c9f0407c6 ("irq-gic: support fiq")
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: I062e6cafcd8728165b6eda8b82f92f7a90672132

drivers/irqchip/irq-gic.c

@@ -338,7 +338,11 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 	void __iomem *cpu_base = gic_data_cpu_base(gic);
 
 	do {
+#ifdef CONFIG_FIQ_GLUE
+		irqstat = readl_relaxed(cpu_base + GIC_CPU_ALIAS_INTACK);
+#else
 		irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
+#endif
 		irqnr = irqstat & GICC_IAR_INT_ID_MASK;
 
 		if (unlikely(irqnr >= 1020))
@@ -379,9 +383,11 @@ static void gic_handle_cascade_irq(struct irq_desc *desc)
 	unsigned long status;
 
 	chained_irq_enter(chip, desc);
-
+#ifdef CONFIG_FIQ_GLUE
+	status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_ALIAS_INTACK);
+#else
 	status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
-
+#endif
 	gic_irq = (status & GICC_IAR_INT_ID_MASK);
 	if (gic_irq == GICC_INT_SPURIOUS)
 		goto out;

include/linux/irqchip/arm-gic.h

@@ -15,6 +15,7 @@
 #define GIC_CPU_RUNNINGPRI		0x14
 #define GIC_CPU_HIGHPRI			0x18
 #define GIC_CPU_ALIAS_BINPOINT		0x1c
+#define GIC_CPU_ALIAS_INTACK		0x20
 #define GIC_CPU_ACTIVEPRIO		0xd0
 #define GIC_CPU_IDENT			0xfc
 #define GIC_CPU_DEACTIVATE		0x1000