shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-10 04:48:04 +09:00
Code Issues Packages Projects Releases Wiki Activity

H.265: fix vpu resume issue [1/1]

Browse Source 
PD#SWPL-5533

Problem:
system crashed in vpu resume

Solution:
Only vpu open_ref_count more than zero,do resume

Verify:
g12b_w400

Change-Id: I9c2cd6242482293499ffddfea5309e5072014eba
Signed-off-by: kunpeng.tang <kunpeng.tang@amlogic.com>
This commit is contained in:
kunpeng.tang
2019-03-27 11:23:59 +08:00
committed by Dongjin Kim
parent d115248cd6
commit bb5df58fec
1 changed files with 62 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files

123
drivers/amlogic/media_modules/frame_sink/encoder/h265/vpu.c
View File

@@ -1871,72 +1871,73 @@ static s32 vpu_resume(struct platform_device *pdev)
enc_pr(LOG_DEBUG, "vpu_resume\n");
vpu_clk_config(1);
for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
if (s_bit_firmware_info[core].size == 0)
continue;
code_base = s_common_memory.phys_addr;
/* ALIGN TO 4KB */
code_size = (s_common_memory.size & ~0xfff);
if (code_size < s_bit_firmware_info[core].size * 2)
goto DONE_WAKEUP;
/*---- LOAD BOOT CODE */
for (i = 0; i < 512; i += 2) {
val = s_bit_firmware_info[core].bit_code[i];
val |= (s_bit_firmware_info[core].bit_code[i+1] << 16);
WriteVpu(code_base+(i*2), val);
}
regVal = 0;
WriteVpuRegister(W4_PO_CONF, regVal);
/* Reset All blocks */
regVal = 0x7ffffff;
WriteVpuRegister(W4_VPU_RESET_REQ, regVal);
/* Waiting reset done */
while (ReadVpuRegister(W4_VPU_RESET_STATUS)) {
if (time_after(jiffies, timeout))
if (s_vpu_open_ref_count > 0) {
for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
if (s_bit_firmware_info[core].size == 0)
continue;
code_base = s_common_memory.phys_addr;
/* ALIGN TO 4KB */
code_size = (s_common_memory.size & ~0xfff);
if (code_size < s_bit_firmware_info[core].size * 2)
goto DONE_WAKEUP;
}
WriteVpuRegister(W4_VPU_RESET_REQ, 0);
/*---- LOAD BOOT CODE */
for (i = 0; i < 512; i += 2) {
val = s_bit_firmware_info[core].bit_code[i];
val |= (s_bit_firmware_info[core].bit_code[i+1] << 16);
WriteVpu(code_base+(i*2), val);
}
/* remap page size */
remap_size = (code_size >> 12) & 0x1ff;
regVal = 0x80000000 | (W4_REMAP_CODE_INDEX<<12)
| (0 << 16) | (1<<11) | remap_size;
WriteVpuRegister(W4_VPU_REMAP_CTRL, regVal);
/* DO NOT CHANGE! */
WriteVpuRegister(W4_VPU_REMAP_VADDR, 0x00000000);
WriteVpuRegister(W4_VPU_REMAP_PADDR, code_base);
WriteVpuRegister(W4_ADDR_CODE_BASE, code_base);
WriteVpuRegister(W4_CODE_SIZE, code_size);
WriteVpuRegister(W4_CODE_PARAM, 0);
WriteVpuRegister(W4_INIT_VPU_TIME_OUT_CNT, timeout);
WriteVpuRegister(W4_HW_OPTION, hwOption);
regVal = 0;
WriteVpuRegister(W4_PO_CONF, regVal);
/* Interrupt */
regVal = (1 << W4_INT_DEC_PIC_HDR);
regVal |= (1 << W4_INT_DEC_PIC);
regVal |= (1 << W4_INT_QUERY_DEC);
regVal |= (1 << W4_INT_SLEEP_VPU);
regVal |= (1 << W4_INT_BSBUF_EMPTY);
regVal = 0xfffffefe;
WriteVpuRegister(W4_VPU_VINT_ENABLE, regVal);
Wave4BitIssueCommand(core, W4_CMD_INIT_VPU);
WriteVpuRegister(W4_VPU_REMAP_CORE_START, 1);
while (ReadVpuRegister(W4_VPU_BUSY_STATUS)) {
if (time_after(jiffies, timeout))
/* Reset All blocks */
regVal = 0x7ffffff;
WriteVpuRegister(W4_VPU_RESET_REQ, regVal);
/* Waiting reset done */
while (ReadVpuRegister(W4_VPU_RESET_STATUS)) {
if (time_after(jiffies, timeout))
goto DONE_WAKEUP;
}
WriteVpuRegister(W4_VPU_RESET_REQ, 0);
/* remap page size */
remap_size = (code_size >> 12) & 0x1ff;
regVal = 0x80000000 | (W4_REMAP_CODE_INDEX<<12)
| (0 << 16) | (1<<11) | remap_size;
WriteVpuRegister(W4_VPU_REMAP_CTRL, regVal);
/* DO NOT CHANGE! */
WriteVpuRegister(W4_VPU_REMAP_VADDR, 0x00000000);
WriteVpuRegister(W4_VPU_REMAP_PADDR, code_base);
WriteVpuRegister(W4_ADDR_CODE_BASE, code_base);
WriteVpuRegister(W4_CODE_SIZE, code_size);
WriteVpuRegister(W4_CODE_PARAM, 0);
WriteVpuRegister(W4_INIT_VPU_TIME_OUT_CNT, timeout);
WriteVpuRegister(W4_HW_OPTION, hwOption);
/* Interrupt */
regVal = (1 << W4_INT_DEC_PIC_HDR);
regVal |= (1 << W4_INT_DEC_PIC);
regVal |= (1 << W4_INT_QUERY_DEC);
regVal |= (1 << W4_INT_SLEEP_VPU);
regVal |= (1 << W4_INT_BSBUF_EMPTY);
regVal = 0xfffffefe;
WriteVpuRegister(W4_VPU_VINT_ENABLE, regVal);
Wave4BitIssueCommand(core, W4_CMD_INIT_VPU);
WriteVpuRegister(W4_VPU_REMAP_CORE_START, 1);
while (ReadVpuRegister(W4_VPU_BUSY_STATUS)) {
if (time_after(jiffies, timeout))
goto DONE_WAKEUP;
}
if (ReadVpuRegister(W4_RET_SUCCESS) == 0) {
enc_pr(LOG_ERROR,
"WAKEUP_VPU failed [0x%x]",
ReadVpuRegister(W4_RET_FAIL_REASON));
goto DONE_WAKEUP;
}
if (ReadVpuRegister(W4_RET_SUCCESS) == 0) {
enc_pr(LOG_ERROR,
"WAKEUP_VPU failed [0x%x]",
ReadVpuRegister(W4_RET_FAIL_REASON));
goto DONE_WAKEUP;
}
}
}