mirror of
https://github.com/hardkernel/linux.git
synced 2026-03-24 19:40:21 +09:00
i3c: master: svc: Prevent incomplete IBI transaction
[ Upstream commit 3a36273e5a07dda0ccec193800f3b78c3c0380af ]
If no free IBI slot is available, svc_i3c_master_handle_ibi returns
immediately. This causes the STOP condition to be missed because the
EmitStop request is sent when the transfer is not complete. To resolve
this, svc_i3c_master_handle_ibi must wait for the transfer to complete
before returning.
Fixes: dd3c52846d ("i3c: master: svc: Add Silvaco I3C master driver")
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://patch.msgid.link/20251027034715.708243-1-yschu@nuvoton.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
82a09b9965
commit
bbd0544921
@@ -358,21 +358,27 @@ static int svc_i3c_master_handle_ibi(struct svc_i3c_master *master,
|
||||
int ret, val;
|
||||
u8 *buf;
|
||||
|
||||
slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
|
||||
if (!slot)
|
||||
return -ENOSPC;
|
||||
|
||||
slot->len = 0;
|
||||
buf = slot->data;
|
||||
|
||||
/*
|
||||
* Wait for transfer to complete before returning. Otherwise, the EmitStop
|
||||
* request might be sent when the transfer is not complete.
|
||||
*/
|
||||
ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,
|
||||
SVC_I3C_MSTATUS_COMPLETE(val), 0, 1000);
|
||||
if (ret) {
|
||||
dev_err(master->dev, "Timeout when polling for COMPLETE\n");
|
||||
i3c_generic_ibi_recycle_slot(data->ibi_pool, slot);
|
||||
return ret;
|
||||
}
|
||||
|
||||
slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
|
||||
if (!slot) {
|
||||
dev_dbg(master->dev, "No free ibi slot, drop the data\n");
|
||||
writel(SVC_I3C_MDATACTRL_FLUSHRB, master->regs + SVC_I3C_MDATACTRL);
|
||||
return -ENOSPC;
|
||||
}
|
||||
|
||||
slot->len = 0;
|
||||
buf = slot->data;
|
||||
|
||||
while (SVC_I3C_MSTATUS_RXPEND(readl(master->regs + SVC_I3C_MSTATUS)) &&
|
||||
slot->len < SVC_I3C_FIFO_SIZE) {
|
||||
mdatactrl = readl(master->regs + SVC_I3C_MDATACTRL);
|
||||
|
||||
Reference in New Issue
Block a user