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osd: osd suspend fail issue
PD#164508: osd: suspend fail issue Change-Id: I673a907bea2abf37d09967ef0e0a924806ce6fae Signed-off-by: pengcheng chen <pengcheng.chen@amlogic.com>
This commit is contained in:
committed by
Yixun Lan
parent
caa103fec4
commit
bc0b7dbd2f
@@ -642,10 +642,12 @@ struct hw_para_s {
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u32 color_key[HW_OSD_COUNT];
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u32 color_key_enable[HW_OSD_COUNT];
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u32 enable[HW_OSD_COUNT];
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u32 enable_save[HW_OSD_COUNT];
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u32 powered[HW_OSD_COUNT];
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u32 reg_status_save;
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u32 reg_status_save1;
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u32 reg_status_save2;
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u32 reg_status_save3;
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#ifdef FIQ_VSYNC
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bridge_item_t fiq_handle_item;
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#endif
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@@ -7412,15 +7412,29 @@ void osd_suspend_hw(void)
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osd_reg_clr_mask(VPP_MISC, OSD_RELATIVE_BITS);
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/* VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC, OSD_RELATIVE_BITS); */
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} else {
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int i = 0;
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for (i = 0; i < osd_hw.osd_meson_dev.osd_count; i++) {
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if (osd_hw.enable[i]) {
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osd_hw.enable_save[i] = ENABLE;
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osd_hw.enable[i] = DISABLE;
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osd_hw.reg[OSD_ENABLE]
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.update_func(i);
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} else
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osd_hw.enable_save[i] = DISABLE;
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}
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osd_hw.reg_status_save =
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osd_reg_read(VIU_OSD_BLEND_CTRL);
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osd_hw.reg_status_save1 =
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osd_reg_read(OSD1_BLEND_SRC_CTRL);
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osd_hw.reg_status_save2 =
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osd_reg_read(OSD2_BLEND_SRC_CTRL);
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osd_hw.reg_status_save3 =
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osd_reg_read(VPP_RDARB_REQEN_SLV);
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osd_reg_clr_mask(VIU_OSD_BLEND_CTRL, 0xf0000);
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osd_reg_clr_mask(OSD1_BLEND_SRC_CTRL, 0xf0f);
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osd_reg_clr_mask(OSD2_BLEND_SRC_CTRL, 0xf0f);
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osd_reg_clr_mask(VPP_RDARB_REQEN_SLV, 0xffff);
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}
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osd_log_info("osd_suspended\n");
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@@ -7454,12 +7468,23 @@ void osd_resume_hw(void)
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}
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notify_to_amvideo();
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} else {
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int i = 0;
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for (i = 0; i < osd_hw.osd_meson_dev.osd_count; i++) {
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if (osd_hw.enable_save[i]) {
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osd_hw.enable[i] = ENABLE;
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osd_hw.reg[OSD_ENABLE]
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.update_func(i);
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}
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}
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osd_reg_set_mask(VIU_OSD_BLEND_CTRL,
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osd_hw.reg_status_save);
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osd_reg_set_mask(OSD1_BLEND_SRC_CTRL,
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osd_hw.reg_status_save1);
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osd_reg_set_mask(OSD2_BLEND_SRC_CTRL,
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osd_hw.reg_status_save2);
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osd_reg_set_mask(VPP_RDARB_REQEN_SLV,
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osd_hw.reg_status_save3);
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}
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osd_log_info("osd_resumed\n");
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}
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@@ -1414,5 +1414,6 @@
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#define VPP_POST_BLEND_BLEND_DUMMY_DATA 0x3968
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#define VPP_POST_BLEND_DUMMY_ALPHA 0x3969
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#define VPP_RDARB_MODE 0x3978
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#define VPP_RDARB_REQEN_SLV 0x3979
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#define VPU_RDARB_MODE_L2C1 0x279d
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#endif
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