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UPSTREAM: arm64/sme: Standardise bitfield names for SVCR

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The bitfield definitions for SVCR have a SYS_ added to the names of the
constant which will be a problem for automatic generation. Remove the
prefixes, no functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220510161208.631259-5-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit e65fc01bf2)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 233587962
Bug: 233588291
Change-Id: I88f88a2d429b1818a069e4c8b71ad0d5023982f0
This commit is contained in:
Mark Brown
2022-05-10 17:12:00 +01:00
committed by Quentin Perret
parent f1d91fbef8
commit bc2fd13bd4
4 changed files with 8 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/include/asm/fpsimd.h
View File

@@ -55,12 +55,12 @@ extern void fpsimd_save_and_flush_cpu_state(void);
static inline bool thread_sm_enabled(struct thread_struct *thread)
{
return system_supports_sme() && (thread->svcr & SYS_SVCR_EL0_SM_MASK);
return system_supports_sme() && (thread->svcr & SVCR_EL0_SM_MASK);
}
static inline bool thread_za_enabled(struct thread_struct *thread)
{
return system_supports_sme() && (thread->svcr & SYS_SVCR_EL0_ZA_MASK);
return system_supports_sme() && (thread->svcr & SVCR_EL0_ZA_MASK);
}
/* Maximum VL that SVE/SME VL-agnostic software can transparently support */

2
arch/arm64/include/asm/processor.h
View File

@@ -195,7 +195,7 @@ static inline unsigned int thread_get_sme_vl(struct thread_struct *thread)
static inline unsigned int thread_get_cur_vl(struct thread_struct *thread)
{
if (system_supports_sme() && (thread->svcr & SYS_SVCR_EL0_SM_MASK))
if (system_supports_sme() && (thread->svcr & SVCR_EL0_SM_MASK))
return thread_get_sme_vl(thread);
else
return thread_get_sve_vl(thread);

4
arch/arm64/include/asm/sysreg.h
View File

@@ -477,8 +477,8 @@
#define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
#define SYS_SVCR_EL0 sys_reg(3, 3, 4, 2, 2)
#define SYS_SVCR_EL0_ZA_MASK 2
#define SYS_SVCR_EL0_SM_MASK 1
#define SVCR_EL0_ZA_MASK 2
#define SVCR_EL0_SM_MASK 1
#define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
#define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)

6
arch/arm64/kernel/fpsimd.c
View File

@@ -1890,7 +1890,7 @@ void __efi_fpsimd_begin(void)
svcr = read_sysreg_s(SYS_SVCR_EL0);
if (!system_supports_fa64())
ffr = svcr & SYS_SVCR_EL0_SM_MASK;
ffr = svcr & SVCR_EL0_SM_MASK;
__this_cpu_write(efi_sm_state, ffr);
}
@@ -1901,7 +1901,7 @@ void __efi_fpsimd_begin(void)
if (system_supports_sme())
sysreg_clear_set_s(SYS_SVCR_EL0,
SYS_SVCR_EL0_SM_MASK, 0);
SVCR_EL0_SM_MASK, 0);
} else {
fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state));
@@ -1936,7 +1936,7 @@ void __efi_fpsimd_end(void)
if (__this_cpu_read(efi_sm_state)) {
sysreg_clear_set_s(SYS_SVCR_EL0,
0,
SYS_SVCR_EL0_SM_MASK);
SVCR_EL0_SM_MASK);
if (!system_supports_fa64())
ffr = efi_sm_state;
}