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ASoC: rockchip: sai: Allow mclk shift around 1 Hz

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This patch allow mclk shift around +/- 1 Hz compared to
requested freq.

we could not always achieve the precise freq as required,
e.g. request: 98304000, but got: 98303999

there is no big deal and any side effect on the above case,
so, we allow a tiny shift for mclk.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Id181a3aa9017b1994786b71c3b56454a2e78b6aa
This commit is contained in:
Sugar Zhang
2023-08-29 15:41:43 +08:00
committed by Tao Huang
parent c4afd40f7f
commit bca24656b6
1 changed files with 5 additions and 3 deletions
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8
sound/soc/rockchip/rockchip_sai.c
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@@ -22,6 +22,7 @@
#define DRV_NAME "rockchip-sai"
#define CLK_SHIFT_RATE_HZ_MAX 1 /* 1 Hz */
#define FW_RATIO_MAX 8
#define FW_RATIO_MIN 1
#define MAXBURST_PER_FIFO 8
@@ -496,9 +497,10 @@ static int rockchip_sai_hw_params(struct snd_pcm_substream *substream,
if (sai->is_clk_auto)
clk_set_rate(sai->mclk, bclk_rate);
mclk_rate = clk_get_rate(sai->mclk);
if (mclk_rate < bclk_rate) {
dev_err(sai->dev, "Mismatch mclk: %u, expected %u at least\n",
mclk_rate, bclk_rate);
if (mclk_rate < bclk_rate - CLK_SHIFT_RATE_HZ_MAX ||
mclk_rate > bclk_rate + CLK_SHIFT_RATE_HZ_MAX) {
dev_err(sai->dev, "Mismatch mclk: %u, expected %u (+/- %dHz)\n",
mclk_rate, bclk_rate, CLK_SHIFT_RATE_HZ_MAX);
return -EINVAL;
}