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media: rockchip: isp: sync with kernel-5.10

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Merge from kernel-5.10
  media: rockchip: isp: fix isp33 unite error for fastboot
  media: rockchip: isp: fix unite mode for fast
  media: rockchip: isp: output stream burst 16 for isp33
  media: rockchip: isp: write burst adjust to 8 for isp33
  media: rockchip: isp: fix free bay3d buf fd to get again fail
  media: rockchip: isp: wait aiq params for isp33 fast
  media: rockchip: isp: fix multi switch to online no work for fast
  media: rockchip: isp: isp33 change input to 4 align
  media: rockchip: isp: fix isp33 multi online resume
  media: rockchip: isp: drop 2 frame if rockit switch resolution
  media: rockchip: isp: disable isp33 dma write gather
  media: rockchip: isp: fix isp33 multi sensor resume
  media: rockchip: isp: isp33 add api to get params
  media: rockchip: isp: fix isp33 unite switch online for fast
  media: rockchip: isp: w3a overflow check for isp33
  media: rockchip: isp: fix isp33 params sram config
  media: rockchip: isp: fix memory leak
  media: rockchip: isp: add sync for multi online mode
  media: rockchip: isp: limit bp crop and scl for isp33
  media: rockchip: isp: fix hold at register irq if mcu still running
  media: rockchip: isp: enable bay3d FST_FRAME if change bypass
  media: rockchip: isp: fix 4k unite effect
  media: rockchip: isp: add api for raw buf cnt and hdr wrap
  media: rockchip: isp: fix resume for multi online mode
  media: rockchip: isp: frame start irq to send dvbm event
  media: rockchip: isp: fix hist for isp33 unite mode
  media: rockchip: isp: fix buf update for multi online mode
  media: rockchip: isp: resume early for isp33
  media: rockchip: isp: fix rd_mode for vicap to send buf
  media: rockchip: isp: fix fast stop no to clean flag
  media: rockchip: isp: fix isp2enc wrap for isp33 fast
  media: rockchip: isp: support online hdr wrap for isp33
  media: rockchip: isp: support unite online for isp33
  media: rockchip: isp: support two sensor online for isp33
  media: rockchip: isp: support mirror for wrap mode
  media: rockchip: isp: more mode for vicap to isp
  media: rockchip: isp: add isp2enc frame count to rockit
  media: rockchip: isp: add rv1103b config
  media: rockchip: isp: add isp33
  media: rockchip: isp: fix rockit switch resolution
  media: rockchip: isp: fix params buffersize for tb case
  media: rockchip: isp: fix isp32 bp no output if suspend
  media: rockchip: isp: rockit buf add offset

Change-Id: I7d3720165e9fb045e88be34c2f58fe83c0f700bc
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This commit is contained in:
Cai YiWei
2024-10-31 15:57:25 +08:00
committed by Tao Huang
parent 4d9d171391
commit bcff29a30f
35 changed files with 13024 additions and 369 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/media/platform/rockchip/isp/Kconfig
View File

@@ -50,6 +50,16 @@ config VIDEO_ROCKCHIP_ISP_VERSION_V39_DBG
depends on VIDEO_ROCKCHIP_ISP_VERSION_V39
default n
config VIDEO_ROCKCHIP_ISP_VERSION_V33
bool "isp33 for rv1103b"
depends on CPU_RV1103B
default y
config VIDEO_ROCKCHIP_ISP_VERSION_V33_DBG
bool "isp33 params debug for rv1103b"
depends on VIDEO_ROCKCHIP_ISP_VERSION_V33
default n
config VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
bool "Rockchip Image Signal Processing Thunderboot helper"
depends on ROCKCHIP_THUNDER_BOOT

6
drivers/media/platform/rockchip/isp/Makefile
View File

@@ -51,6 +51,12 @@ video_rkisp-$(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39) += \
isp_pdaf.o \
isp_sditf.o
video_rkisp-$(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V33) += \
capture_v33.o \
isp_params_v33.o \
isp_stats_v33.o \
isp_rockit.o
video_rkisp-$(CONFIG_ROCKCHIP_DVBM) += \
isp_dvbm.o

76
drivers/media/platform/rockchip/isp/capture.c
View File

@@ -372,6 +372,7 @@ void rkisp_stream_vir_cpy_image(struct work_struct *work)
struct rkisp_buffer *src_buf = NULL;
struct vb2_buffer *src_vb = NULL;
struct rkisp_device *isp_dev = vir->ispdev;
struct rkisp_stream *src_stream = NULL;
const struct vb2_mem_ops *g_ops = isp_dev->hw_dev->mem_ops;
void *src = NULL, *dst = NULL, *mem = NULL;
u32 payload_size = 0;
@@ -420,14 +421,19 @@ void rkisp_stream_vir_cpy_image(struct work_struct *work)
payload_size = vir->out_fmt.plane_fmt[i].sizeimage;
dst = vb2_plane_vaddr(&vir->curr_buf->vb.vb2_buf, i);
mem = src_vb->planes[i].mem_priv;
src = vb2_plane_vaddr(&src_buf->vb.vb2_buf, i);
if (src_vb->memory)
src = vb2_plane_vaddr(&src_buf->vb.vb2_buf, i);
else
src = src_buf->vaddr[i];
if (!src || !dst)
break;
/* sync cache */
if (mem)
g_ops->finish(mem);
if (mem) {
if (src_vb->memory)
g_ops->finish(mem);
else
dma_sync_sgtable_for_cpu(isp_dev->hw_dev->dev, mem, DMA_BIDIRECTIONAL);
}
vb2_set_plane_payload(&vir->curr_buf->vb.vb2_buf, i, payload_size);
memcpy(dst, src, payload_size);
}
@@ -438,8 +444,15 @@ void rkisp_stream_vir_cpy_image(struct work_struct *work)
vir->curr_buf = NULL;
end:
if (src_buf)
vb2_buffer_done(&src_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
if (src_buf) {
if (src_buf->vb.vb2_buf.memory) {
vb2_buffer_done(&src_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
} else {
src_stream = &isp_dev->cap_dev.stream[vir->conn_id];
if (src_stream)
rkisp_rockit_buf_done(src_stream, ROCKIT_DVBM_END, src_buf);
}
}
src_buf = NULL;
spin_lock_irqsave(&vir->vbq_lock, lock_flags);
@@ -533,8 +546,10 @@ int rkisp_stream_frame_start(struct rkisp_device *dev, u32 isp_mis)
struct rkisp_stream *stream;
int i;
if (isp_mis)
rkisp_dvbm_event(dev, CIF_ISP_V_START);
/* frame start irq no handle for unite or multi-sensor online mode */
if (!dev->hw_dev->is_single && isp_mis)
return 0;
rkisp_bridge_update_mi(dev, isp_mis);
for (i = 0; i < RKISP_MAX_STREAM; i++) {
@@ -972,6 +987,10 @@ int rkisp_fh_open(struct file *filp)
if (!stream->ispdev->is_probe_end)
return -EINVAL;
ret = rkisp_cond_poll_timeout(!stream->ispdev->is_thunderboot,
5000, 1000 * USEC_PER_MSEC);
if (ret)
return ret;
ret = v4l2_fh_open(filp);
if (!ret) {
@@ -1102,7 +1121,9 @@ static int rkisp_get_cmsk(struct rkisp_stream *stream, struct rkisp_cmsk_cfg *cf
unsigned long lock_flags = 0;
u32 i, win_en, mode;
if ((dev->isp_ver != ISP_V30 && dev->isp_ver != ISP_V32) ||
if ((dev->isp_ver != ISP_V30 &&
dev->isp_ver != ISP_V32 &&
dev->isp_ver != ISP_V33) ||
stream->id == RKISP_STREAM_FBC ||
stream->id == RKISP_STREAM_MPDS ||
stream->id == RKISP_STREAM_BPDS) {
@@ -1151,7 +1172,9 @@ static int rkisp_set_cmsk(struct rkisp_stream *stream, struct rkisp_cmsk_cfg *cf
u32 align = (dev->isp_ver == ISP_V30) ? 8 : 2;
bool warn = false;
if ((dev->isp_ver != ISP_V30 && dev->isp_ver != ISP_V32) ||
if ((dev->isp_ver != ISP_V30 &&
dev->isp_ver != ISP_V32 &&
dev->isp_ver != ISP_V33) ||
stream->id == RKISP_STREAM_FBC ||
stream->id == RKISP_STREAM_MPDS ||
stream->id == RKISP_STREAM_BPDS) {
@@ -1243,7 +1266,7 @@ static int rkisp_get_mirror_flip(struct rkisp_stream *stream,
{
struct rkisp_device *dev = stream->ispdev;
if (dev->isp_ver != ISP_V32)
if (dev->isp_ver != ISP_V32 && dev->isp_ver != ISP_V33)
return -EINVAL;
cfg->mirror = dev->cap_dev.is_mirror;
@@ -1256,16 +1279,15 @@ static int rkisp_set_mirror_flip(struct rkisp_stream *stream,
{
struct rkisp_device *dev = stream->ispdev;
if (dev->isp_ver != ISP_V32)
if (dev->isp_ver != ISP_V32 && dev->isp_ver != ISP_V33)
return -EINVAL;
if (dev->cap_dev.wrap_line) {
v4l2_warn(&dev->v4l2_dev, "wrap_line mode can not set the mirror");
dev->cap_dev.is_mirror = 0;
} else {
dev->cap_dev.is_mirror = cfg->mirror;
if (dev->cap_dev.wrap_line && cfg->flip) {
cfg->flip = 0;
v4l2_warn(&dev->v4l2_dev, "no support flip for wrap mode\n");
}
dev->cap_dev.is_mirror = cfg->mirror;
stream->is_flip = cfg->flip;
stream->is_mf_upd = true;
return 0;
@@ -1275,7 +1297,8 @@ static int rkisp_get_wrap_line(struct rkisp_stream *stream, struct rkisp_wrap_in
{
struct rkisp_device *dev = stream->ispdev;
if (dev->isp_ver != ISP_V32 && stream->id != RKISP_STREAM_MP)
if (stream->id != RKISP_STREAM_MP &&
dev->isp_ver != ISP_V32 && dev->isp_ver != ISP_V33)
return -EINVAL;
arg->width = dev->cap_dev.wrap_width;
@@ -1299,7 +1322,7 @@ static int rkisp_set_fps(struct rkisp_stream *stream, int *fps)
{
struct rkisp_device *dev = stream->ispdev;
if (dev->isp_ver != ISP_V32)
if (dev->isp_ver != ISP_V32 && dev->isp_ver != ISP_V33)
return -EINVAL;
return rkisp_rockit_fps_set(fps, stream);
@@ -1309,7 +1332,7 @@ static int rkisp_get_fps(struct rkisp_stream *stream, int *fps)
{
struct rkisp_device *dev = stream->ispdev;
if (dev->isp_ver != ISP_V32)
if (dev->isp_ver != ISP_V32 && dev->isp_ver != ISP_V33)
return -EINVAL;
return rkisp_rockit_fps_get(fps, stream);
@@ -1781,7 +1804,7 @@ static void rkisp_stream_fast(struct work_struct *work)
struct v4l2_subdev *sd = ispdev->active_sensor->sd;
int ret;
if (ispdev->isp_ver != ISP_V32)
if (ispdev->isp_ver != ISP_V32 && ispdev->isp_ver != ISP_V33)
return;
mutex_lock(&ispdev->hw_dev->dev_lock);
@@ -1799,8 +1822,7 @@ static void rkisp_stream_fast(struct work_struct *work)
if (ispdev->hw_dev->dev_num > 1)
ispdev->hw_dev->is_single = false;
ispdev->is_pre_on = true;
ispdev->is_rdbk_auto = true;
ispdev->pipe.open(&ispdev->pipe, &stream->vnode.vdev.entity, true);
rkisp_csi_config_patch(ispdev, true);
v4l2_subdev_call(sd, video, s_stream, true);
}
@@ -1927,6 +1949,8 @@ int rkisp_register_stream_vdevs(struct rkisp_device *dev)
ret = rkisp_register_stream_v32(dev);
} else if (dev->isp_ver == ISP_V39) {
ret = rkisp_register_stream_v39(dev);
} else if (dev->isp_ver == ISP_V33) {
ret = rkisp_register_stream_v33(dev);
}
INIT_WORK(&cap_dev->fast_work, rkisp_stream_fast);
@@ -1947,6 +1971,8 @@ void rkisp_unregister_stream_vdevs(struct rkisp_device *dev)
rkisp_unregister_stream_v32(dev);
else if (dev->isp_ver == ISP_V39)
rkisp_unregister_stream_v39(dev);
else if (dev->isp_ver == ISP_V33)
rkisp_unregister_stream_v33(dev);
}
void rkisp_mi_isr(u32 mis_val, struct rkisp_device *dev)
@@ -1963,6 +1989,8 @@ void rkisp_mi_isr(u32 mis_val, struct rkisp_device *dev)
rkisp_mi_v32_isr(mis_val, dev);
else if (dev->isp_ver == ISP_V39)
rkisp_mi_v39_isr(mis_val, dev);
else if (dev->isp_ver == ISP_V33)
rkisp_mi_v33_isr(mis_val, dev);
}
void rkisp_mipi_v3x_isr(unsigned int phy, unsigned int packet,

55
drivers/media/platform/rockchip/isp/capture_v32.c
View File

@@ -348,6 +348,12 @@ static const struct capture_fmt luma_fmts[] = {
},
};
static struct stream_config rkisp_luma_stream_config = {
.fmts = luma_fmts,
.fmt_size = ARRAY_SIZE(luma_fmts),
.frame_end_id = 0,
};
static struct stream_config rkisp_sp_stream_config_lite = {
/* constraints */
.max_rsz_width = CIF_ISP_INPUT_W_MAX_V32_L,
@@ -410,12 +416,6 @@ static struct stream_config rkisp_sp_stream_config_lite = {
},
};
static struct stream_config rkisp_luma_stream_config = {
.fmts = luma_fmts,
.fmt_size = ARRAY_SIZE(luma_fmts),
.frame_end_id = 0,
};
static struct stream_config rkisp_bp_stream_config = {
.fmts = bp_fmts,
.fmt_size = ARRAY_SIZE(bp_fmts),
@@ -853,6 +853,7 @@ static int sp_config_mi(struct rkisp_stream *stream)
{
struct rkisp_device *dev = stream->ispdev;
struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt;
struct capture_fmt *fmt = &stream->out_isp_fmt;
struct ispsd_out_fmt *input_isp_fmt =
rkisp_get_ispsd_out_fmt(&dev->isp_sdev);
u32 sp_in_fmt, val, mask;
@@ -867,7 +868,8 @@ static int sp_config_mi(struct rkisp_stream *stream)
* NOTE: plane_fmt[0].sizeimage is total size of all planes for single
* memory plane formats, so calculate the size explicitly.
*/
val = stream->u.sp.y_stride;
val = out_fmt->plane_fmt[0].bytesperline;
val /= DIV_ROUND_UP(fmt->bpp[0], 8);
rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false);
val *= out_fmt->height;
rkisp_unite_write(dev, stream->config->mi.y_pic_size, val, false);
@@ -1287,7 +1289,6 @@ static int set_mirror_flip(struct rkisp_stream *stream)
val = ISP32_MP_WR_V_FLIP;
if (dev->cap_dev.wrap_line) {
stream->is_flip = false;
v4l2_warn(&dev->v4l2_dev, "flip not support width wrap function\n");
return -EINVAL;
}
}
@@ -1529,9 +1530,10 @@ static int mi_frame_end(struct rkisp_stream *stream, u32 state)
/* STREAM_VIR or STREAM_MP wrap buf from rockit */
if (stream->id == RKISP_STREAM_VIR ||
(stream->id == RKISP_STREAM_MP && dev->cap_dev.wrap_line &&
!stream->dummy_buf.mem_priv && stream->dummy_buf.dma_addr))
!stream->dummy_buf.mem_priv && stream->dummy_buf.dma_addr)) {
set_mirror_flip(stream);
return 0;
}
if (dev->cap_dev.is_done_early &&
(state == FRAME_IRQ || state == FRAME_WORK)) {
/* skip mainpath wrap mode */
@@ -1586,19 +1588,18 @@ static int mi_frame_end(struct rkisp_stream *stream, u32 state)
stream->dbg.timestamp = ns;
stream->dbg.id = i;
if (vb2_buf->memory) {
if (vir->streaming && vir->conn_id == stream->id) {
spin_lock_irqsave(&vir->vbq_lock, lock_flags);
list_add_tail(&buf->queue,
&dev->cap_dev.vir_cpy.queue);
spin_unlock_irqrestore(&vir->vbq_lock, lock_flags);
if (!completion_done(&dev->cap_dev.vir_cpy.cmpl))
complete(&dev->cap_dev.vir_cpy.cmpl);
} else {
rkisp_stream_buf_done(stream, buf);
}
if (vir->streaming && vir->conn_id == stream->id) {
spin_lock_irqsave(&vir->vbq_lock, lock_flags);
list_add_tail(&buf->queue,
&dev->cap_dev.vir_cpy.queue);
spin_unlock_irqrestore(&vir->vbq_lock, lock_flags);
if (!completion_done(&dev->cap_dev.vir_cpy.cmpl))
complete(&dev->cap_dev.vir_cpy.cmpl);
} else {
rkisp_rockit_buf_done(stream, ROCKIT_DVBM_END);
if (vb2_buf->memory)
rkisp_stream_buf_done(stream, buf);
else
rkisp_rockit_buf_done(stream, ROCKIT_DVBM_END, buf);
}
}
@@ -1840,7 +1841,7 @@ static void rkisp_destroy_dummy_buf(struct rkisp_stream *stream)
if (!dev->cap_dev.wrap_line || stream->id != RKISP_STREAM_MP)
return;
rkisp_dvbm_deinit();
rkisp_dvbm_deinit(dev);
rkisp_free_buffer(dev, &stream->dummy_buf);
stream->dummy_buf.dma_addr = 0;
}
@@ -1935,10 +1936,8 @@ end:
mutex_unlock(&dev->hw_dev->dev_lock);
if (dev->is_pre_on && stream->id == RKISP_STREAM_MP) {
dev->is_rdbk_auto = false;
dev->is_pre_on = false;
v4l2_subdev_call(dev->active_sensor->sd, video, s_stream, false);
dev->pipe.close(&dev->pipe);
dev->params_vdev.first_cfg_params = false;
v4l2_pipeline_pm_put(&stream->vnode.vdev.entity);
}
}
@@ -2309,9 +2308,6 @@ void rkisp_unregister_stream_v32(struct rkisp_device *dev)
stream = &cap_dev->stream[RKISP_STREAM_LUMA];
rkisp_unregister_stream_vdev(stream);
rkisp_rockit_dev_deinit();
} else {
stream = &cap_dev->stream[RKISP_STREAM_VIR];
rkisp_unregister_stream_vdev(stream);
}
}
@@ -2370,6 +2366,7 @@ void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev)
stream->dbg.delay = ns - dev->isp_sdev.frm_timestamp;
stream->dbg.timestamp = ns;
stream->dbg.id = seq;
set_mirror_flip(stream);
} else {
mi_frame_end(stream, FRAME_IRQ);
}

1972
drivers/media/platform/rockchip/isp/capture_v33.c Normal file
View File

File diff suppressed because it is too large Load Diff

29
drivers/media/platform/rockchip/isp/capture_v3x.h
View File

@@ -24,7 +24,23 @@ static inline void rkisp_mi_v30_isr(u32 mis_val, struct rkisp_device *dev) {}
int rkisp_register_stream_v32(struct rkisp_device *dev);
void rkisp_unregister_stream_v32(struct rkisp_device *dev);
void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev);
#else
static inline int rkisp_register_stream_v32(struct rkisp_device *dev) { return -EINVAL; }
static inline void rkisp_unregister_stream_v32(struct rkisp_device *dev) {}
static inline void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev) {}
#endif
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V33)
int rkisp_register_stream_v33(struct rkisp_device *dev);
void rkisp_unregister_stream_v33(struct rkisp_device *dev);
void rkisp_mi_v33_isr(u32 mis_val, struct rkisp_device *dev);
#else
static inline int rkisp_register_stream_v33(struct rkisp_device *dev) { return -EINVAL; }
static inline void rkisp_unregister_stream_v33(struct rkisp_device *dev) {}
static inline void rkisp_mi_v33_isr(u32 mis_val, struct rkisp_device *dev) {}
#endif
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32) || IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V33)
void rkisp_rockit_buf_state_clear(struct rkisp_stream *stream);
int rkisp_rockit_buf_free(struct rkisp_stream *stream);
void rkisp_rockit_dev_init(struct rkisp_device *dev);
@@ -32,12 +48,8 @@ void rkisp_rockit_dev_deinit(void);
void rkisp_rockit_frame_start(struct rkisp_device *dev);
int rkisp_rockit_fps_set(int *dst_fps, struct rkisp_stream *stream);
int rkisp_rockit_fps_get(int *dst_fps, struct rkisp_stream *stream);
int rkisp_rockit_buf_done(struct rkisp_stream *stream, int cmd);
int rkisp_rockit_buf_done(struct rkisp_stream *stream, int cmd, struct rkisp_buffer *curr_buf);
#else
static inline int rkisp_register_stream_v32(struct rkisp_device *dev) { return -EINVAL; }
static inline void rkisp_unregister_stream_v32(struct rkisp_device *dev) {}
static inline void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev) {}
static inline void rkisp_rockit_buf_state_clear(struct rkisp_stream *stream) { return; }
static inline int rkisp_rockit_buf_free(struct rkisp_stream *stream) { return -EINVAL; }
static inline void rkisp_rockit_dev_init(struct rkisp_device *dev) { return; }
@@ -45,7 +57,8 @@ static inline void rkisp_rockit_dev_deinit(void) {}
static inline void rkisp_rockit_frame_start(struct rkisp_device *dev) {}
static inline int rkisp_rockit_fps_set(int *dst_fps, struct rkisp_stream *stream) { return -EINVAL; }
static inline int rkisp_rockit_fps_get(int *dst_fps, struct rkisp_stream *stream) { return -EINVAL; }
static inline int rkisp_rockit_buf_done(struct rkisp_stream *stream, int cmd) { return -EINVAL; }
static inline int rkisp_rockit_buf_done(struct rkisp_stream *stream, int cmd,
struct rkisp_buffer *curr_buf) { return -EINVAL; }
#endif
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39)
@@ -63,12 +76,12 @@ static inline void rkisp_stream_ldc_end_v39(struct rkisp_device *dev) {}
#if IS_ENABLED(CONFIG_ROCKCHIP_DVBM)
int rkisp_dvbm_get(struct rkisp_device *dev);
int rkisp_dvbm_init(struct rkisp_stream *stream);
void rkisp_dvbm_deinit(void);
void rkisp_dvbm_deinit(struct rkisp_device *dev);
int rkisp_dvbm_event(struct rkisp_device *dev, u32 event);
#else
static inline int rkisp_dvbm_get(struct rkisp_device *dev) { return -EINVAL; }
static inline int rkisp_dvbm_init(struct rkisp_stream *stream) { return -EINVAL; }
static inline void rkisp_dvbm_deinit(void) {}
static inline void rkisp_dvbm_deinit(struct rkisp_device *dev) {}
static inline int rkisp_dvbm_event(struct rkisp_device *dev, u32 event) { return -EINVAL; }
#endif

4
drivers/media/platform/rockchip/isp/common.c
View File

@@ -227,8 +227,6 @@ int rkisp_buf_get_fd(struct rkisp_device *dev,
if (!buf || !buf->mem_priv)
return -EINVAL;
if (try_fd && buf->is_need_dmafd)
return 0;
if (try_fd) {
buf->is_need_dbuf = true;
buf->is_need_dmafd = true;
@@ -532,7 +530,7 @@ u64 rkisp_time_get_ns(struct rkisp_device *dev)
{
u64 ns;
if (dev->isp_ver == ISP_V32)
if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V33)
ns = ktime_get_boottime_ns();
else
ns = ktime_get_ns();

1
drivers/media/platform/rockchip/isp/common.h
View File

@@ -146,6 +146,7 @@ extern bool rkisp_irq_dbg;
extern bool rkisp_buf_dbg;
extern u64 rkisp_debug_reg;
extern unsigned int rkisp_vicap_buf[DEV_MAX];
extern unsigned int rkisp_hdr_wrap_line[DEV_MAX];
extern struct platform_driver rkisp_plat_drv;
static inline

83
drivers/media/platform/rockchip/isp/csi.c
View File

@@ -524,7 +524,7 @@ int rkisp_csi_get_hdr_cfg(struct rkisp_device *dev, void *arg)
return v4l2_subdev_call(sd, core, ioctl, RKMODULE_GET_HDR_CFG, cfg);
}
int rkisp_csi_config_patch(struct rkisp_device *dev)
int rkisp_csi_config_patch(struct rkisp_device *dev, bool is_pre_cfg)
{
int val = 0, ret = 0;
struct v4l2_subdev *mipi_sensor;
@@ -541,7 +541,8 @@ int rkisp_csi_config_patch(struct rkisp_device *dev)
ret = rkisp_csi_get_hdr_cfg(dev, &hdr_cfg);
if (dev->isp_inp & INP_CIF) {
struct rkisp_vicap_mode mode;
int buf_cnt = 0;
struct rkisp_init_buf init_buf = { 0 };
u32 op_mode;
memset(&mode, 0, sizeof(mode));
mode.name = dev->name;
@@ -563,46 +564,79 @@ int rkisp_csi_config_patch(struct rkisp_device *dev)
if (dev->isp_inp == INP_CIF && dev->isp_ver > ISP_V21) {
/* read back mode default if more sensor link to isp */
if (!dev->hw_dev->is_single)
if (!dev->hw_dev->is_single && !dev->is_m_online)
dev->is_rdbk_auto = true;
mode.rdbk_mode = dev->is_rdbk_auto ? RKISP_VICAP_RDBK_AUTO : RKISP_VICAP_ONLINE;
if (dev->is_m_online && dev->unite_div == ISP_UNITE_DIV2)
mode.rdbk_mode = RKISP_VICAP_ONLINE_UNITE;
else if (dev->is_m_online)
mode.rdbk_mode = RKISP_VICAP_ONLINE_MULTI;
else if (dev->is_rdbk_auto)
mode.rdbk_mode = RKISP_VICAP_RDBK_AUTO;
else
mode.rdbk_mode = RKISP_VICAP_ONLINE;
} else {
mode.rdbk_mode = RKISP_VICAP_RDBK_AIQ;
}
/* vicap pre capture raw for thunderboot mode */
if (is_pre_cfg)
mode.rdbk_mode = RKISP_VICAP_RDBK_AUTO;
mode.dev_id = dev->dev_id;
v4l2_subdev_call(mipi_sensor, core, ioctl, RKISP_VICAP_CMD_MODE, &mode);
dev->vicap_in = mode.input;
op_mode = dev->hdr.op_mode;
/* vicap direct to isp */
if (dev->isp_ver >= ISP_V30 && !mode.rdbk_mode) {
switch (dev->hdr.op_mode) {
if (dev->isp_ver >= ISP_V30 &&
mode.rdbk_mode <= RKISP_VICAP_ONLINE_UNITE) {
switch (op_mode) {
case HDR_RDBK_FRAME3:
dev->hdr.op_mode = HDR_LINEX3_DDR;
op_mode = HDR_LINEX3_DDR;
break;
case HDR_RDBK_FRAME2:
dev->hdr.op_mode = HDR_LINEX2_DDR;
op_mode = HDR_LINEX2_DDR;
break;
default:
dev->hdr.op_mode = HDR_NORMAL;
op_mode = HDR_NORMAL;
dev->hdr_wrap_line = 0;
}
if (dev->hdr.op_mode != HDR_NORMAL) {
buf_cnt = 1;
if (op_mode != HDR_NORMAL ||
mode.rdbk_mode == RKISP_VICAP_ONLINE_UNITE) {
init_buf.buf_cnt = 1;
init_buf.hdr_wrap_line = dev->hdr_wrap_line;
}
} else if (mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
dev->hdr_wrap_line = 0;
if (dev->vicap_buf_cnt)
buf_cnt = dev->vicap_buf_cnt;
init_buf.buf_cnt = dev->vicap_buf_cnt;
else
buf_cnt = RKISP_VICAP_BUF_CNT;
init_buf.buf_cnt = RKISP_VICAP_BUF_CNT;
}
if (buf_cnt)
if (init_buf.buf_cnt) {
if (!dev->is_pre_on || is_pre_cfg)
dev->rd_mode = op_mode;
v4l2_subdev_call(mipi_sensor, core, ioctl,
RKISP_VICAP_CMD_INIT_BUF, &buf_cnt);
RKISP_VICAP_CMD_INIT_BUF, &init_buf);
}
if (dev->is_pre_on && !is_pre_cfg) {
if (dev->isp_ver == ISP_V33 && dev->cap_dev.wrap_line) {
val = ISP33_SW_ISP2ENC_PATH_EN | ISP33_PP_ENC_PIPE_EN;
rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, val, false);
}
return 0;
}
dev->hdr.op_mode = op_mode;
} else {
dev->hdr.op_mode = hdr_cfg.hdr_mode;
}
if (!dev->hw_dev->is_mi_update)
if (dev->isp_ver < ISP_V30) {
if (!dev->hw_dev->is_mi_update)
rkisp_unite_write(dev, CSI2RX_CTRL0,
SW_IBUF_OP_MODE(dev->hdr.op_mode), true);
} else {
rkisp_unite_write(dev, CSI2RX_CTRL0,
SW_IBUF_OP_MODE(dev->hdr.op_mode), true);
SW_IBUF_OP_MODE(dev->hdr.op_mode), false);
}
/* hdr merge */
switch (dev->hdr.op_mode) {
case HDR_RDBK_FRAME2:
@@ -633,11 +667,18 @@ int rkisp_csi_config_patch(struct rkisp_device *dev)
rkisp_unite_set_bits(dev, CSI2RX_MASK_STAT, 0, val, true);
}
val = 0;
if (IS_HDR_RDBK(dev->hdr.op_mode))
rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, SW_MPIP_DROP_FRM_DIS, true);
val |= SW_MPIP_DROP_FRM_DIS;
if (dev->isp_ver == ISP_V33 && dev->cap_dev.wrap_line) {
val |= ISP33_SW_ISP2ENC_PATH_EN;
if (IS_HDR_RDBK(dev->hdr.op_mode))
val |= ISP33_PP_ENC_PIPE_EN;
}
if (dev->isp_ver >= ISP_V30)
rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP3X_SW_ACK_FRM_PRO_DIS, true);
val |= ISP3X_SW_ACK_FRM_PRO_DIS;
if (val)
rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, val, false);
/* line counter from isp out, default from mp out */
if (dev->isp_ver == ISP_V32_L || dev->isp_ver == ISP_V39)
rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP32L_ISP2ENC_CNT_MUX, true);

2
drivers/media/platform/rockchip/isp/csi.h
View File

@@ -78,7 +78,7 @@ int rkisp_register_csi_subdev(struct rkisp_device *dev,
struct v4l2_device *v4l2_dev);
void rkisp_unregister_csi_subdev(struct rkisp_device *dev);
int rkisp_csi_get_hdr_cfg(struct rkisp_device *dev, void *arg);
int rkisp_csi_config_patch(struct rkisp_device *dev);
int rkisp_csi_config_patch(struct rkisp_device *dev, bool is_pre_cfg);
void rkisp_csi_sof(struct rkisp_device *dev, u8 id);
void rkisp_get_remote_mipi_sensor(struct rkisp_device *dev,
struct v4l2_subdev **sensor_sd, u32 function);

93
drivers/media/platform/rockchip/isp/dev.c
View File

@@ -79,6 +79,10 @@ static bool rkisp_clk_dbg;
module_param_named(clk_dbg, rkisp_clk_dbg, bool, 0644);
MODULE_PARM_DESC(clk_dbg, "rkisp clk set by user");
static bool rkisp_m_online[DEV_MAX];
module_param_array_named(m_online, rkisp_m_online, bool, NULL, 0644);
MODULE_PARM_DESC(m_online, "rkisp multi sensor online mode");
static char rkisp_version[RKISP_VERNO_LEN];
module_param_string(version, rkisp_version, RKISP_VERNO_LEN, 0444);
MODULE_PARM_DESC(version, "version number");
@@ -99,6 +103,10 @@ unsigned int rkisp_vicap_buf[DEV_MAX];
module_param_array_named(vicap_raw_buf, rkisp_vicap_buf, uint, NULL, 0644);
MODULE_PARM_DESC(vicap_raw_buf, "rkisp and vicap auto readback mode raw buf count");
unsigned int rkisp_hdr_wrap_line[DEV_MAX];
module_param_array_named(hdr_wrap_line, rkisp_hdr_wrap_line, uint, NULL, 0644);
MODULE_PARM_DESC(hdr_wrap_line, "rkisp and vicap online hdr wrap line");
static DEFINE_MUTEX(rkisp_dev_mutex);
static LIST_HEAD(rkisp_device_list);
@@ -269,7 +277,7 @@ end:
if (hw_dev->unite == ISP_UNITE_TWO)
rkisp_set_clk_rate(hw_dev->clks[5], hw_dev->clk_rate_tbl[i].clk_rate * 1000000UL);
/* aclk equal to core clk */
if (dev->isp_ver == ISP_V32)
if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V33)
rkisp_set_clk_rate(hw_dev->clks[1], hw_dev->clk_rate_tbl[i].clk_rate * 1000000UL);
dev_info(hw_dev->dev, "set isp clk = %luHz\n", clk_get_rate(hw_dev->clks[0]));
@@ -289,6 +297,7 @@ static int rkisp_pipeline_open(struct rkisp_pipeline *p,
if (atomic_inc_return(&p->power_cnt) > 1)
return 0;
dev->hdr_wrap_line = 0;
if (hw->is_assigned_clk)
rkisp_clk_dbg = true;
if (!(dev->isp_inp & (INP_RAWRD0 | INP_RAWRD2))) {
@@ -298,6 +307,14 @@ static int rkisp_pipeline_open(struct rkisp_pipeline *p,
if (rkisp_vicap_buf[dev->dev_id] > RKISP_VICAP_BUF_CNT_MAX)
rkisp_vicap_buf[dev->dev_id] = RKISP_VICAP_BUF_CNT_MAX;
dev->vicap_buf_cnt = rkisp_vicap_buf[dev->dev_id];
dev->is_m_online = rkisp_m_online[dev->dev_id];
if (hw->isp_ver != ISP_V33 || hw->is_single)
dev->is_m_online = false;
if (hw->isp_ver == ISP_V33) {
if (dev->unite_div != ISP_UNITE_DIV1)
rkisp_hdr_wrap_line[dev->dev_id] = 0;
dev->hdr_wrap_line = rkisp_hdr_wrap_line[dev->dev_id];
}
}
dev->cap_dev.wait_line = rkisp_wait_line;
@@ -316,7 +333,7 @@ static int rkisp_pipeline_open(struct rkisp_pipeline *p,
dev->hw_dev->monitor.is_en = rkisp_monitor;
if (dev->isp_inp & (INP_CSI | INP_RAWRD0 | INP_RAWRD1 | INP_RAWRD2 | INP_CIF))
rkisp_csi_config_patch(dev);
rkisp_csi_config_patch(dev, false);
return 0;
err:
atomic_dec(&p->power_cnt);
@@ -335,6 +352,7 @@ static int rkisp_pipeline_close(struct rkisp_pipeline *p)
if (dev->hw_dev->is_runing && (dev->isp_ver >= ISP_V30) && !rkisp_clk_dbg)
dev->hw_dev->is_dvfs = true;
dev->is_rdbk_auto = false;
dev->is_m_online = false;
return 0;
}
@@ -358,12 +376,17 @@ static int rkisp_pipeline_set_stream(struct rkisp_pipeline *p, bool on)
ret = v4l2_subdev_call(&dev->isp_sdev.sd, video, s_stream, true);
if (ret < 0)
goto err;
if (dev->is_m_online && !dev->is_pre_on &&
atomic_read(&dev->hw_dev->refcnt) == 1) {
i = 1;
v4l2_subdev_call(p->subdevs[0], core, ioctl, RKISP_VICAP_CMD_HW_LINK, &i);
}
/* phy -> sensor */
for (i = 0; i < p->num_subdevs; ++i) {
if (((dev->vicap_in.merge_num > 1) &&
(p->subdevs[i]->entity.function == MEDIA_ENT_F_CAM_SENSOR)) ||
(dev->isp_inp & INP_CIF && IS_HDR_RDBK(dev->rd_mode) &&
(!dev->is_rdbk_auto)))
((dev->isp_inp & (INP_CIF | INP_RAWRD2)) == (INP_CIF | INP_RAWRD2)) ||
dev->is_pre_on)
continue;
ret = v4l2_subdev_call(p->subdevs[i], video, s_stream, on);
if (on && ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV)
@@ -384,8 +407,7 @@ static int rkisp_pipeline_set_stream(struct rkisp_pipeline *p, bool on)
for (i = p->num_subdevs - 1; i >= 0; --i) {
if (((dev->vicap_in.merge_num > 1) &&
(p->subdevs[i]->entity.function == MEDIA_ENT_F_CAM_SENSOR)) ||
(dev->isp_inp & INP_CIF && IS_HDR_RDBK(dev->rd_mode) &&
(!dev->is_rdbk_auto)))
((dev->isp_inp & (INP_CIF | INP_RAWRD2)) == (INP_CIF | INP_RAWRD2)))
continue;
v4l2_subdev_call(p->subdevs[i], video, s_stream, on);
}
@@ -569,6 +591,9 @@ static int _set_pipeline_default_fmt(struct rkisp_device *dev, bool is_init)
}
if (dev->isp_ver == ISP_V39)
rkisp_set_stream_def_fmt(dev, RKISP_STREAM_LDC, width, height, V4L2_PIX_FMT_NV12);
if (dev->isp_ver == ISP_V33)
rkisp_set_stream_def_fmt(dev, RKISP_STREAM_BP,
width, height, V4L2_PIX_FMT_NV12);
return 0;
}
@@ -1082,12 +1107,13 @@ static int rkisp_pm_prepare(struct device *dev)
return 0;
}
static void rkisp_pm_complete(struct device *dev)
static int rkisp_resume(struct device *dev)
{
struct rkisp_device *isp_dev = dev_get_drvdata(dev);
struct rkisp_hw_dev *hw = isp_dev->hw_dev;
struct rkisp_pipeline *p = &isp_dev->pipe;
struct rkisp_stream *stream;
struct rkisp_device *isp_tmp;
int i, on = 1, rd_mode = isp_dev->rd_mode;
u32 val;
@@ -1100,7 +1126,7 @@ static void rkisp_pm_complete(struct device *dev)
if (mipi_sensor)
v4l2_subdev_call(mipi_sensor, core, s_power, 1);
}
return;
return 0;
}
if (isp_dev->is_rtt_suspend) {
@@ -1182,21 +1208,66 @@ static void rkisp_pm_complete(struct device *dev)
if (isp_dev->is_first_double)
stream->skip_frame = 1;
}
if (hw->cur_dev_id == isp_dev->dev_id)
if (hw->cur_dev_id == isp_dev->dev_id) {
if (atomic_read(&hw->refcnt) == 2) {
/* isp0 online, isp1 offline, isp0 to running first */
isp_tmp = hw->isp[!isp_dev->dev_id];
if (isp_dev->dev_id && !(IS_HDR_RDBK(isp_tmp->rd_mode)))
hw->is_idle = false;
}
rkisp_rdbk_trigger_event(isp_dev, T_CMD_QUEUE, NULL);
}
if (rkisp_link_sensor(isp_dev->isp_inp)) {
for (i = 0; i < p->num_subdevs; i++)
v4l2_subdev_call(p->subdevs[i], core, s_power, 1);
for (i = 0; i < p->num_subdevs; i++)
v4l2_subdev_call(p->subdevs[i], video, s_stream, on);
} else if (isp_dev->isp_inp & INP_CIF && !(IS_HDR_RDBK(isp_dev->rd_mode))) {
} else if (isp_dev->isp_inp & INP_CIF && !IS_HDR_RDBK(isp_dev->rd_mode)) {
if (!hw->is_single) {
int on = 1;
if (atomic_read(&hw->refcnt) == 2) {
/* isp0 and isp1 online, isp1 to running first */
isp_tmp = hw->isp[!isp_dev->dev_id];
if (!IS_HDR_RDBK(isp_tmp->rd_mode) && !isp_dev->dev_id)
on = 0;
} else if (isp_dev->unite_div == ISP_UNITE_DIV2) {
isp_dev->unite_index = ISP_UNITE_LEFT;
isp_dev->params_vdev.rdbk_times = 2;
}
if (on) {
hw->cur_dev_id = isp_dev->dev_id;
hw->is_idle = false;
rkisp_online_update_reg(isp_dev, false, true);
rkisp_vicap_hw_link(isp_dev, on);
}
}
v4l2_subdev_call(p->subdevs[0], core, ioctl, RKISP_VICAP_CMD_QUICK_STREAM, &on);
}
return 0;
}
static int rkisp_pm_resume(struct device *dev)
{
struct rkisp_device *isp_dev = dev_get_drvdata(dev);
if (isp_dev->isp_ver == ISP_V33)
return rkisp_resume(dev);
return 0;
}
static void rkisp_pm_complete(struct device *dev)
{
struct rkisp_device *isp_dev = dev_get_drvdata(dev);
if (isp_dev->isp_ver == ISP_V33)
return;
rkisp_resume(dev);
}
static const struct dev_pm_ops rkisp_plat_pm_ops = {
.prepare = rkisp_pm_prepare,
.resume = rkisp_pm_resume,
.complete = rkisp_pm_complete,
SET_RUNTIME_PM_OPS(rkisp_runtime_suspend, rkisp_runtime_resume, NULL)
};

8
drivers/media/platform/rockchip/isp/dev.h
View File

@@ -296,6 +296,7 @@ struct rkisp_device {
bool is_hw_link;
bool is_bigmode;
bool is_rdbk_auto;
bool is_m_online;
bool is_pre_on;
bool is_first_double;
bool is_probe_end;
@@ -305,8 +306,12 @@ struct rkisp_device {
bool is_suspend_one_frame;
bool is_aiisp_en;
bool is_aiisp_upd;
bool is_frm_rd;
bool is_multi_one_sync;
bool is_wait_aiq;
struct rkisp_vicap_input vicap_in;
u32 hdr_wrap_line;
u8 multi_mode;
u8 multi_index;
@@ -315,6 +320,9 @@ struct rkisp_device {
u8 unite_div;
};
void rkisp_vicap_hw_link(struct rkisp_device *dev, int on);
void rkisp_online_update_reg(struct rkisp_device *dev, bool is_init, bool is_reset);
static inline void
rkisp_unite_write(struct rkisp_device *dev, u32 reg, u32 val, bool is_direct)
{

29
drivers/media/platform/rockchip/isp/dmarx.c
View File

@@ -482,6 +482,8 @@ static int dmarx_frame_end(struct rkisp_stream *stream)
{
struct rkisp_buffer *buf = NULL;
unsigned long lock_flags = 0;
u32 val, reg;
int on = 1;
spin_lock_irqsave(&stream->vbq_lock, lock_flags);
if (stream->curr_buf) {
@@ -518,14 +520,31 @@ static int dmarx_frame_end(struct rkisp_stream *stream)
dev->rd_mode = HDR_NORMAL;
}
dev->hdr.op_mode = dev->rd_mode;
rkisp_unite_write(dev, CSI2RX_CTRL0,
SW_IBUF_OP_MODE(dev->hdr.op_mode), true);
rkisp_unite_set_bits(dev, CSI2RX_MASK_STAT,
0, ISP21_MIPI_DROP_FRM, true);
rkisp_unite_clear_bits(dev, CIF_ISP_IMSC, CIF_ISP_FRAME_IN, true);
val = SW_IBUF_OP_MODE(dev->hdr.op_mode);
rkisp_unite_write(dev, CSI2RX_CTRL0, val, false);
val = ISP21_MIPI_DROP_FRM;
rkisp_unite_set_bits(dev, CSI2RX_MASK_STAT, 0, val, false);
rkisp_unite_clear_bits(dev, CIF_ISP_IMSC, CIF_ISP_FRAME_IN, false);
if (dev->isp_ver == ISP_V33) {
val = ISP33_PP_ENC_PIPE_EN;
rkisp_unite_clear_bits(dev, CTRL_SWS_CFG, val, false);
if (dev->hdr_wrap_line) {
val = stream->out_fmt.plane_fmt[0].bytesperline * dev->hdr_wrap_line;
rkisp_unite_write(dev, ISP32_MI_RAW0_RD_SIZE, val, false);
}
if (dev->unite_div == ISP_UNITE_DIV2) {
mi_raw_length(stream);
reg = stream->config->mi.y_base_ad_init;
rkisp_unite_write(dev, reg, rx_buf->dma, false);
dev->unite_index = ISP_UNITE_LEFT;
dev->params_vdev.rdbk_times = 2;
}
}
dev_info(dev->dev,
"switch online seq:%d mode:0x%x\n",
rx_buf->sequence, dev->rd_mode);
if (dev->hw_dev->is_single)
v4l2_subdev_call(sd, core, ioctl, RKISP_VICAP_CMD_HW_LINK, &on);
}
rx_buf->runtime_us = dev->isp_sdev.dbg.interval / 1000;
v4l2_subdev_call(sd, video, s_rx_buffer, rx_buf, NULL);

158
drivers/media/platform/rockchip/isp/hw.c
View File

@@ -128,6 +128,22 @@ static void default_sw_reg_flag(struct rkisp_device *dev)
ISP3X_RAWHIST_BIG1_BASE, ISP3X_RAWHIST_BIG2_BASE, ISP3X_RAWHIST_BIG3_BASE,
ISP3X_RAWAF_CTRL, ISP3X_RAWAWB_CTRL,
};
u32 v33_reg[] = {
ISP3X_VI_ISP_PATH, ISP3X_IMG_EFF_CTRL, ISP3X_CMSK_CTRL0,
ISP3X_CCM_CTRL, ISP3X_CPROC_CTRL, ISP3X_DUAL_CROP_CTRL,
ISP3X_GAMMA_OUT_CTRL, ISP39_MAIN_SCALE_CTRL, ISP33_BP_SCALE_CTRL,
ISP32_SELF_SCALE_CTRL, ISP3X_MI_WR_CTRL, ISP3X_MI_BP_WR_CTRL,
ISP32_MI_WR_WRAP_CTRL, ISP3X_LSC_CTRL, ISP3X_DEBAYER_CONTROL,
ISP3X_CAC_CTRL, ISP3X_YNR_GLOBAL_CTRL, ISP3X_CNR_CTRL,
ISP3X_SHARP_EN, ISP33_BAY3D_CTRL0, ISP3X_GIC_CONTROL,
ISP3X_BLS_CTRL, ISP3X_DPCC0_MODE, ISP3X_DPCC1_MODE,
ISP3X_DPCC2_MODE, ISP3X_HDRMGE_CTRL, ISP3X_DRC_CTRL0,
ISP33_ENH_CTRL, ISP3X_LDCH_STS, ISP33_HIST_CTRL,
ISP33_HSV_CTRL, ISP3X_GAIN_CTRL, ISP39_W3A_CTRL0,
ISP3X_RAWAE_LITE_CTRL, ISP3X_RAWAE_BIG1_BASE,
ISP3X_RAWHIST_LITE_CTRL, ISP3X_RAWHIST_BIG1_BASE,
ISP3X_RAWAWB_CTRL,
};
u32 i, j, *flag, *reg, size;
switch (dev->isp_ver) {
@@ -152,6 +168,10 @@ static void default_sw_reg_flag(struct rkisp_device *dev)
reg = v39_reg;
size = ARRAY_SIZE(v39_reg);
break;
case ISP_V33:
reg = v33_reg;
size = ARRAY_SIZE(v33_reg);
break;
default:
return;
}
@@ -351,7 +371,7 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
ISP_RAWHIST_LITE_BASE, ISP_RAWHIST_BIG1_BASE,
ISP_RAWHIST_BIG2_BASE, ISP_RAWHIST_BIG3_BASE,
ISP_RAWAF_BASE, ISP_RAWAWB_BASE, ISP_LDCH_BASE,
ISP3X_CAC_BASE,
ISP3X_CAC_BASE, ISP33_BAY3D_CTRL0, ISP33_ENH_CTRL
};
struct backup_reg backup[] = {
{
@@ -454,11 +474,15 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
for (j = 0; j < RKISP_ISP_SW_REG_SIZE; j += 4) {
/* skip table RAM */
if ((j > ISP3X_LSC_CTRL && j < ISP3X_LSC_XGRAD_01) ||
(j > ISP32_CAC_OFFSET && j < ISP3X_CAC_RO_CNT) ||
(j > ISP32_CAC_OFFSET && j < ISP3X_CAC_RO_CNT && dev->isp_ver != ISP_V33) ||
(j > ISP3X_3DLUT_UPDATE && j < ISP3X_GAIN_BASE) ||
(j == 0x4840 || j == 0x4a80 || j == 0x4b40 || j == 0x5660) ||
(dev->isp_ver == ISP_V39 &&
(j > ISP39_DHAZ_HIST_IIR0 && j < ISP39_DHAZ_LINE_CNT)))
(j > ISP39_DHAZ_HIST_IIR0 && j < ISP39_DHAZ_LINE_CNT)) ||
(dev->isp_ver == ISP_V33 &&
((j > ISP33_ENH_IIR0 && j < ISP33_ENH_ERR_FLAG) ||
(j > ISP33_HIST_IIR0 && j < ISP33_HIST_STAB) ||
(j >= ISP33_SHARP_NOISE_CURVE0 && j <= ISP33_SHARP_NOISE_CURVE8))))
continue;
/* skip mmu range */
if (dev->isp_ver < ISP_V30 &&
@@ -492,25 +516,27 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
}
writel(val, base + backup[j].base);
}
if (dev->isp_ver == ISP_V32) {
if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V33) {
reg = reg_buf + ISP32_MI_WR_CTRL2_SHD;
reg1 = reg_buf + ISP3X_MI_BP_WR_CTRL;
if ((*reg & ISP32_BP_EN_IN_SHD) != (*reg1 & ISP3X_BP_ENABLE)) {
val = *reg & ISP32_BP_EN_IN_SHD;
val |= *reg1 & ~ISP3X_BP_ENABLE;
if (!!(*reg & ISP32_BP_EN_IN_SHD) != !!(*reg1 & ISP3X_BP_ENABLE)) {
val = !!(*reg & ISP32_BP_EN_IN_SHD);
val |= (*reg1 & ~ISP3X_BP_ENABLE);
writel(val, base + ISP3X_MI_BP_WR_CTRL);
}
reg1 = reg_buf + ISP32_MI_MPDS_WR_CTRL;
if ((*reg & ISP32_MPDS_EN_IN_SHD) != (*reg1 & ISP32_DS_ENABLE)) {
val = *reg & ISP32_MPDS_EN_IN_SHD;
val |= *reg1 & ~ISP32_DS_ENABLE;
writel(val, base + ISP32_MI_MPDS_WR_CTRL);
}
reg1 = reg_buf + ISP32_MI_BPDS_WR_CTRL;
if ((*reg & ISP32_BPDS_EN_IN_SHD) != (*reg1 & ISP32_DS_ENABLE)) {
val = *reg & ISP32_BPDS_EN_IN_SHD;
val |= *reg1 & ~ISP32_DS_ENABLE;
writel(val, base + ISP32_MI_BPDS_WR_CTRL);
if (dev->isp_ver == ISP_V32) {
reg1 = reg_buf + ISP32_MI_MPDS_WR_CTRL;
if (!!(*reg & ISP32_MPDS_EN_IN_SHD) != !!(*reg1 & ISP32_DS_ENABLE)) {
val = !!(*reg & ISP32_MPDS_EN_IN_SHD);
val |= (*reg1 & ~ISP32_DS_ENABLE);
writel(val, base + ISP32_MI_MPDS_WR_CTRL);
}
reg1 = reg_buf + ISP32_MI_BPDS_WR_CTRL;
if (!!(*reg & ISP32_BPDS_EN_IN_SHD) != !!(*reg1 & ISP32_DS_ENABLE)) {
val = !!(*reg & ISP32_BPDS_EN_IN_SHD);
val |= (*reg1 & ~ISP32_DS_ENABLE);
writel(val, base + ISP32_MI_BPDS_WR_CTRL);
}
}
}
@@ -520,7 +546,7 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
writel(*reg | CIF_DUAL_CROP_CFG_UPD, base + DUAL_CROP_CTRL);
reg = reg_buf + SELF_RESIZE_CTRL;
if (*reg & 0xf) {
if (dev->isp_ver == ISP_V32_L || dev->isp_ver == ISP_V39)
if (dev->isp_ver == ISP_V32_L || dev->isp_ver == ISP_V39 || dev->isp_ver == ISP_V33)
writel(ISP32_SCALE_FORCE_UPD | ISP32_SCALE_GEN_UPD,
base + ISP32_SELF_SCALE_UPDATE);
else
@@ -528,28 +554,35 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
}
reg = reg_buf + MAIN_RESIZE_CTRL;
if (*reg & 0xf) {
if (dev->isp_ver == ISP_V39)
if (dev->isp_ver == ISP_V39 || dev->isp_ver == ISP_V33)
writel(ISP32_SCALE_FORCE_UPD | ISP32_SCALE_GEN_UPD,
base + ISP39_MAIN_SCALE_UPDATE);
else
writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + MAIN_RESIZE_CTRL);
}
reg = reg_buf + ISP32_BP_RESIZE_CTRL;
if (*reg & 0xf)
writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + ISP32_BP_RESIZE_CTRL);
if (*reg & 0xf) {
if (dev->isp_ver == ISP_V33)
writel(ISP32_SCALE_FORCE_UPD | ISP32_SCALE_GEN_UPD,
base + ISP33_BP_SCALE_UPDATE);
else
writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + ISP32_BP_RESIZE_CTRL);
}
/* update mi and isp, base_reg will update to shd_reg */
writel(CIF_MI_INIT_SOFT_UPD, base + MI_WR_INIT);
/* config base_reg */
for (j = 0; j < ARRAY_SIZE(backup); j++)
writel(backup[j].val, base + backup[j].base);
if (dev->isp_ver == ISP_V32) {
if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V33) {
reg = reg_buf + ISP3X_MI_BP_WR_CTRL;
writel(*reg, base + ISP3X_MI_BP_WR_CTRL);
reg = reg_buf + ISP32_MI_MPDS_WR_CTRL;
writel(*reg, base + ISP32_MI_MPDS_WR_CTRL);
reg = reg_buf + ISP32_MI_BPDS_WR_CTRL;
writel(*reg, base + ISP32_MI_BPDS_WR_CTRL);
if (dev->isp_ver == ISP_V32) {
reg = reg_buf + ISP32_MI_MPDS_WR_CTRL;
writel(*reg, base + ISP32_MI_MPDS_WR_CTRL);
reg = reg_buf + ISP32_MI_BPDS_WR_CTRL;
writel(*reg, base + ISP32_MI_BPDS_WR_CTRL);
}
}
/* base_reg = shd_reg, write is base but read is shd */
val = rkisp_read_reg_cache(isp, ISP_MPFBC_HEAD_PTR);
@@ -557,7 +590,7 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
val = rkisp_read_reg_cache(isp, MI_SWS_3A_WR_BASE);
writel(val, base + MI_SWS_3A_WR_BASE);
/* force for cac to read lut */
if (dev->isp_ver >= ISP_V33) {
if (dev->isp_ver == ISP_V39) {
val = rkisp_read_reg_cache(isp, ISP3X_CAC_BASE);
writel(val, base + ISP3X_CAC_BASE);
}
@@ -584,6 +617,17 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
writel(*reg, dev->base_addr + ISP39_W3A_AWB_ADDR);
reg = reg_buf + ISP39_W3A_PDAF_ADDR_SHD;
writel(*reg, dev->base_addr + ISP39_W3A_PDAF_ADDR);
} else if (dev->isp_ver == ISP_V33) {
reg = reg_buf + ISP33_BAY3D_CTRL0;
if (*reg & 1)
writel(*reg | BIT(31), dev->base_addr + ISP33_BAY3D_CTRL0);
/* w3a addr will update by ISP_CFG_UPD */
reg = reg_buf + ISP39_W3A_AEBIG_ADDR_SHD;
writel(*reg, dev->base_addr + ISP39_W3A_AEBIG_ADDR);
reg = reg_buf + ISP39_W3A_AE0_ADDR_SHD;
writel(*reg, dev->base_addr + ISP39_W3A_AE0_ADDR);
reg = reg_buf + ISP39_W3A_AWB_ADDR_SHD;
writel(*reg, dev->base_addr + ISP39_W3A_AWB_ADDR);
}
reg = reg_buf + ISP_CTRL;
@@ -594,17 +638,19 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
if (dev->unite == ISP_UNITE_TWO)
writel(*reg, dev->base_next_addr + ISP_CTRL);
if (dev->isp_ver == ISP_V39) {
if (dev->isp_ver == ISP_V39 || dev->isp_ver == ISP_V33) {
reg = reg_buf + ISP39_W3A_AEBIG_ADDR;
writel(*reg, dev->base_addr + ISP39_W3A_AEBIG_ADDR);
reg = reg_buf + ISP39_W3A_AE0_ADDR;
writel(*reg, dev->base_addr + ISP39_W3A_AE0_ADDR);
reg = reg_buf + ISP39_W3A_AF_ADDR;
writel(*reg, dev->base_addr + ISP39_W3A_AF_ADDR);
reg = reg_buf + ISP39_W3A_AWB_ADDR;
writel(*reg, dev->base_addr + ISP39_W3A_AWB_ADDR);
reg = reg_buf + ISP39_W3A_PDAF_ADDR;
writel(*reg, dev->base_addr + ISP39_W3A_PDAF_ADDR);
if (dev->isp_ver == ISP_V39) {
reg = reg_buf + ISP39_W3A_AF_ADDR;
writel(*reg, dev->base_addr + ISP39_W3A_AF_ADDR);
reg = reg_buf + ISP39_W3A_PDAF_ADDR;
writel(*reg, dev->base_addr + ISP39_W3A_PDAF_ADDR);
}
}
}
}
@@ -805,6 +851,17 @@ static struct isp_irqs_data rv1126_isp_irqs[] = {
{"mipi_irq", mipi_irq_hdl}
};
static const struct isp_match_data rv1103b_isp_match_data = {
.clks = rv1106_isp_clks,
.num_clks = ARRAY_SIZE(rv1106_isp_clks),
.isp_ver = ISP_V33,
.clk_rate_tbl = rv1106_isp_clk_rate,
.num_clk_rate_tbl = ARRAY_SIZE(rv1106_isp_clk_rate),
.irqs = rv1106_isp_irqs,
.num_irqs = ARRAY_SIZE(rv1106_isp_irqs),
.unite = false,
};
static const struct isp_match_data rv1106_isp_match_data = {
.clks = rv1106_isp_clks,
.num_clks = ARRAY_SIZE(rv1106_isp_clks),
@@ -910,6 +967,12 @@ static const struct of_device_id rkisp_hw_of_match[] = {
.data = &rk3588_isp_unite_match_data,
},
#endif
#ifdef CONFIG_CPU_RV1103B
{
.compatible = "rockchip,rv1103b-rkisp",
.data = &rv1103b_isp_match_data,
},
#endif
#ifdef CONFIG_CPU_RV1106
{
.compatible = "rockchip,rv1106-rkisp",
@@ -1023,6 +1086,30 @@ void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure)
writel(ISP39_W3A_PDAF2DDR_HOLD_DIS | ISP39_W3A_3A_HOLD_DIS,
dev->base_addr + ISP39_W3A_CTRL0);
writel(0, dev->base_addr + ISP39_VI3A_CTRL0);
} else if (dev->isp_ver == ISP_V33) {
writel(0, dev->base_addr + ISP32_BLS_ISP_OB_PREDGAIN);
writel(ISP39_ADRC_CMPS_BYP_EN, dev->base_addr + ISP3X_DRC_CTRL0);
writel(ISP39_W3A_PDAF2DDR_HOLD_DIS | ISP39_W3A_3A_HOLD_DIS,
dev->base_addr + ISP39_W3A_CTRL0);
writel(0, dev->base_addr + ISP39_LDCH_OUT_SIZE);
/* debayer reg default */
writel(0x09aa9988, dev->base_addr + ISP3X_DEBAYER_G_INTERP);
writel(0, dev->base_addr + ISP3X_DEBAYER_G_INTERP_FILTER1);
writel(0, dev->base_addr + ISP3X_DEBAYER_G_INTERP_FILTER2);
writel(0x040d6381, dev->base_addr + ISP3X_DEBAYER_OFFSET);
writel(0x041c021e, dev->base_addr + ISP3X_DEBAYER_C_FILTER);
writel(0x041e021f, dev->base_addr + ISP32_DEBAYER_C_FILTER_GUIDE_GAUS);
writel(0x40400004, dev->base_addr + ISP32_DEBAYER_C_FILTER_CE_GAUS);
writel(0x00100010, dev->base_addr + ISP32_DEBAYER_C_FILTER_ALPHA_GAUS);
writel(0x00100010, dev->base_addr + ISP32_DEBAYER_C_FILTER_LOG_OFFSET);
writel(0x00100010, dev->base_addr + ISP32_DEBAYER_C_FILTER_ALPHA);
writel(0x00100010, dev->base_addr + ISP32_DEBAYER_C_FILTER_EDGE);
writel(0x00014001, dev->base_addr + ISP39_DEBAYER_G_FILTER_MODE_OFFSET);
writel(0x000a1018, dev->base_addr + ISP39_DEBAYER_G_FILTER_FILTER);
writel(0x08000800, dev->base_addr + ISP39_DEBAYER_G_FILTER_VSIGMA0);
writel(0x02000400, dev->base_addr + ISP39_DEBAYER_G_FILTER_VSIGMA1);
writel(0x00cd0155, dev->base_addr + ISP39_DEBAYER_G_FILTER_VSIGMA2);
writel(0x00800092, dev->base_addr + ISP39_DEBAYER_G_FILTER_VSIGMA3);
}
}
@@ -1031,7 +1118,8 @@ static void isp_config_clk(struct rkisp_hw_dev *dev, int on)
u32 val = !on ? 0 :
CIF_ICCL_ISP_CLK | CIF_ICCL_CP_CLK | CIF_ICCL_MRSZ_CLK |
CIF_ICCL_SRSZ_CLK | CIF_ICCL_JPEG_CLK | CIF_ICCL_MI_CLK |
CIF_ICCL_IE_CLK | CIF_ICCL_MIPI_CLK | CIF_ICCL_DCROP_CLK;
CIF_ICCL_IE_CLK | CIF_ICCL_MIPI_CLK | CIF_ICCL_DCROP_CLK |
CIF_ICCL_SIMP_CLK | CIF_ICCL_SMIA_CLK;
if ((dev->isp_ver == ISP_V20 || dev->isp_ver >= ISP_V30) && on)
val |= ICCL_MPFBC_CLK;
@@ -1477,7 +1565,7 @@ static int __maybe_unused rkisp_runtime_resume(struct device *dev)
}
static const struct dev_pm_ops rkisp_hw_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
SET_RUNTIME_PM_OPS(rkisp_runtime_suspend, rkisp_runtime_resume, NULL)
};

15
drivers/media/platform/rockchip/isp/isp_dvbm.c
View File

@@ -17,7 +17,7 @@ int rkisp_dvbm_get(struct rkisp_device *dev)
int ret = -EINVAL;
g_dvbm = NULL;
if (dev->isp_ver != ISP_V32)
if (dev->isp_ver != ISP_V32 && dev->isp_ver != ISP_V33)
goto end;
if (!np_dvbm || !of_device_is_available(np_dvbm)) {
@@ -61,10 +61,13 @@ int rkisp_dvbm_init(struct rkisp_stream *stream)
return 0;
}
void rkisp_dvbm_deinit(void)
void rkisp_dvbm_deinit(struct rkisp_device *dev)
{
if (g_dvbm)
rk_dvbm_unlink(g_dvbm);
if (!g_dvbm || !dev) {
pr_err("g_dvbm %p or devv %p is NULL\n", g_dvbm, dev);
return;
}
rk_dvbm_unlink(g_dvbm);
}
int rkisp_dvbm_event(struct rkisp_device *dev, u32 event)
@@ -72,8 +75,8 @@ int rkisp_dvbm_event(struct rkisp_device *dev, u32 event)
enum dvbm_cmd cmd;
u32 seq;
if (!g_dvbm || dev->isp_ver != ISP_V32 ||
!dev->cap_dev.wrap_line)
if (!g_dvbm || !dev->cap_dev.wrap_line ||
(dev->isp_ver != ISP_V32 && dev->isp_ver != ISP_V33))
return -EINVAL;
rkisp_dmarx_get_frame(dev, &seq, NULL, NULL, true);

23
drivers/media/platform/rockchip/isp/isp_external.h
View File

@@ -4,11 +4,13 @@
#ifndef _RKISP_EXTERNAL_H
#define _RKISP_EXTERNAL_H
#include <linux/iopoll.h>
#define RKISP_VICAP_CMD_MODE \
_IOWR('V', BASE_VIDIOC_PRIVATE + 0, struct rkisp_vicap_mode)
#define RKISP_VICAP_CMD_INIT_BUF \
_IOW('V', BASE_VIDIOC_PRIVATE + 1, int)
_IOW('V', BASE_VIDIOC_PRIVATE + 1, struct rkisp_init_buf)
#define RKISP_VICAP_CMD_RX_BUFFER_FREE \
_IOW('V', BASE_VIDIOC_PRIVATE + 2, struct rkisp_rx_buf)
@@ -22,17 +24,30 @@
#define RKISP_VICAP_CMD_SET_STREAM \
_IOW('V', BASE_VIDIOC_PRIVATE + 5, int)
#define RKISP_VICAP_CMD_HW_LINK \
_IOW('V', BASE_VIDIOC_PRIVATE + 6, int)
#define RKISP_VICAP_BUF_CNT 3
#define RKISP_VICAP_BUF_CNT_MAX 8
#define RKISP_RX_BUF_POOL_MAX (RKISP_VICAP_BUF_CNT_MAX * 3)
#define rkisp_cond_poll_timeout(cond, sleep_us, timeout_us) \
({ \
int __val; \
read_poll_timeout((int), __val, cond, sleep_us, timeout_us, false, 0); \
})
struct rkisp_vicap_input {
u8 merge_num;
u8 index;
u8 multi_sync;
};
enum rkisp_vicap_link {
RKISP_VICAP_ONLINE,
RKISP_VICAP_ONLINE_ONE_FRAME,
RKISP_VICAP_ONLINE_MULTI,
RKISP_VICAP_ONLINE_UNITE,
RKISP_VICAP_RDBK_AIQ,
RKISP_VICAP_RDBK_AUTO,
RKISP_VICAP_RDBK_AUTO_ONE_FRAME,
@@ -43,6 +58,12 @@ struct rkisp_vicap_mode {
enum rkisp_vicap_link rdbk_mode;
struct rkisp_vicap_input input;
int dev_id;
};
struct rkisp_init_buf {
u32 buf_cnt;
u32 hdr_wrap_line;
};
enum rx_buf_type {

67
drivers/media/platform/rockchip/isp/isp_params.c
View File

@@ -15,6 +15,7 @@
#include "isp_params_v3x.h"
#include "isp_params_v32.h"
#include "isp_params_v39.h"
#include "isp_params_v33.h"
#include "regs.h"
#define PARAMS_NAME DRIVER_NAME "-input-params"
@@ -99,6 +100,8 @@ static int rkisp_get_params(struct rkisp_isp_params_vdev *params_vdev, void *arg
if (params_vdev->dev->isp_ver == ISP_V39)
ret = rkisp_get_params_v39(params_vdev, arg);
else if (params_vdev->dev->isp_ver == ISP_V33)
ret = rkisp_get_params_v33(params_vdev, arg);
return ret;
}
@@ -113,6 +116,7 @@ static long rkisp_params_ioctl_default(struct file *file, void *fh,
ret = rkisp_expander_config(params->dev, arg, true);
break;
case RKISP_CMD_GET_PARAMS_V39:
case RKISP_CMD_GET_PARAMS_V33:
ret = rkisp_get_params(params, arg);
break;
default:
@@ -216,7 +220,13 @@ static void rkisp_params_vb2_buf_queue(struct vb2_buffer *vb)
list_add_tail(&params_buf->queue, &params_vdev->params);
spin_unlock_irqrestore(&params_vdev->config_lock, flags);
if (params_vdev->dev->is_first_double) {
if (dev->is_wait_aiq) {
dev_info(dev->dev, "sync params for rtt\n");
dev->is_wait_aiq = false;
dev->skip_frame = 0;
rkisp_rdbk_trigger_event(dev, T_CMD_END, NULL);
}
if (dev->is_first_double) {
struct isp32_isp_params_cfg *params = params_buf->vaddr[0];
struct rkisp_buffer *buf;
@@ -232,9 +242,18 @@ static void rkisp_params_vb2_buf_queue(struct vb2_buffer *vb)
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
}
spin_unlock_irqrestore(&params_vdev->config_lock, flags);
dev_info(params_vdev->dev->dev,
"first params:%d for rtt resume\n", params->frame_id);
params_vdev->dev->is_first_double = false;
dev_info(dev->dev, "params seq:%d for rtt\n", params->frame_id);
dev->is_first_double = false;
if (dev->isp_ver == ISP_V33) {
dev->skip_frame = 1;
dev->is_wait_aiq = true;
}
dev->sw_rd_cnt = 0;
if (dev->hw_dev->unite == ISP_UNITE_ONE) {
dev->unite_index = ISP_UNITE_LEFT;
dev->sw_rd_cnt += dev->hw_dev->is_multi_overflow ? 3 : 1;
}
params_vdev->rdbk_times = dev->sw_rd_cnt + 1;
rkisp_trigger_read_back(params_vdev->dev, false, false, false);
}
}
@@ -275,6 +294,7 @@ static void rkisp_params_vb2_stop_streaming(struct vb2_queue *vq)
params_vdev->rdbk_times = 0;
if (!(dev->isp_state & ISP_START))
rkisp_params_stream_stop(params_vdev);
dev->fpn_cfg.en = 0;
if (dev->fpn_cfg.buf) {
vfree(dev->fpn_cfg.buf);
@@ -318,6 +338,10 @@ static int rkisp_params_fh_open(struct file *filp)
if (!params->dev->is_probe_end)
return -EINVAL;
ret = rkisp_cond_poll_timeout(!params->dev->is_thunderboot,
5000, 1000 * USEC_PER_MSEC);
if (ret)
return ret;
ret = v4l2_fh_open(filp);
if (!ret) {
@@ -386,21 +410,23 @@ rkisp_params_init_vb2_queue(struct vb2_queue *q,
static int rkisp_init_params_vdev(struct rkisp_isp_params_vdev *params_vdev)
{
int ret;
struct rkisp_device *dev = params_vdev->dev;
int ret = -EINVAL;
if (params_vdev->dev->isp_ver <= ISP_V13)
if (dev->isp_ver <= ISP_V13)
ret = rkisp_init_params_vdev_v1x(params_vdev);
else if (params_vdev->dev->isp_ver == ISP_V21)
else if (dev->isp_ver == ISP_V21)
ret = rkisp_init_params_vdev_v21(params_vdev);
else if (params_vdev->dev->isp_ver == ISP_V20)
else if (dev->isp_ver == ISP_V20)
ret = rkisp_init_params_vdev_v2x(params_vdev);
else if (params_vdev->dev->isp_ver == ISP_V30)
else if (dev->isp_ver == ISP_V30)
ret = rkisp_init_params_vdev_v3x(params_vdev);
else if (params_vdev->dev->isp_ver == ISP_V32 ||
params_vdev->dev->isp_ver == ISP_V32_L)
else if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V32_L)
ret = rkisp_init_params_vdev_v32(params_vdev);
else
else if (dev->isp_ver == ISP_V39)
ret = rkisp_init_params_vdev_v39(params_vdev);
else if (dev->isp_ver == ISP_V33)
ret = rkisp_init_params_vdev_v33(params_vdev);
params_vdev->vdev_fmt.fmt.meta.dataformat = V4L2_META_FMT_RK_ISP1_PARAMS;
return ret;
@@ -408,19 +434,22 @@ static int rkisp_init_params_vdev(struct rkisp_isp_params_vdev *params_vdev)
static void rkisp_uninit_params_vdev(struct rkisp_isp_params_vdev *params_vdev)
{
if (params_vdev->dev->isp_ver <= ISP_V13)
struct rkisp_device *dev = params_vdev->dev;
if (dev->isp_ver <= ISP_V13)
rkisp_uninit_params_vdev_v1x(params_vdev);
else if (params_vdev->dev->isp_ver == ISP_V21)
else if (dev->isp_ver == ISP_V21)
rkisp_uninit_params_vdev_v21(params_vdev);
else if (params_vdev->dev->isp_ver == ISP_V20)
else if (dev->isp_ver == ISP_V20)
rkisp_uninit_params_vdev_v2x(params_vdev);
else if (params_vdev->dev->isp_ver == ISP_V30)
else if (dev->isp_ver == ISP_V30)
rkisp_uninit_params_vdev_v3x(params_vdev);
else if (params_vdev->dev->isp_ver == ISP_V32 ||
params_vdev->dev->isp_ver == ISP_V32_L)
else if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V32_L)
rkisp_uninit_params_vdev_v32(params_vdev);
else
else if (dev->isp_ver == ISP_V39)
rkisp_uninit_params_vdev_v39(params_vdev);
else if (dev->isp_ver == ISP_V33)
rkisp_uninit_params_vdev_v33(params_vdev);
}
void rkisp_params_cfg(struct rkisp_isp_params_vdev *params_vdev, u32 frame_id)

2
drivers/media/platform/rockchip/isp/isp_params.h
View File

@@ -9,6 +9,7 @@
#include <linux/rk-isp3-config.h>
#include <linux/rk-isp32-config.h>
#include <linux/rk-isp39-config.h>
#include <linux/rk-isp33-config.h>
#include <linux/rk-preisp.h>
#include "common.h"
@@ -66,6 +67,7 @@ struct rkisp_isp_params_vdev {
struct isp3x_isp_params_cfg *isp3x_params;
struct isp32_isp_params_cfg *isp32_params;
struct isp39_isp_params_cfg *isp39_params;
struct isp33_isp_params_cfg *isp33_params;
};
struct v4l2_format vdev_fmt;
bool streamon;

13
drivers/media/platform/rockchip/isp/isp_params_v32.c
View File

@@ -4985,7 +4985,18 @@ rkisp_params_first_cfg_v32(struct rkisp_isp_params_vdev *params_vdev)
static void rkisp_save_first_param_v32(struct rkisp_isp_params_vdev *params_vdev, void *param)
{
memcpy(params_vdev->isp32_params, param, params_vdev->vdev_fmt.fmt.meta.buffersize);
u32 size;
if (!params_vdev->dev->is_rtt_first) {
size = params_vdev->vdev_fmt.fmt.meta.buffersize;
memcpy(params_vdev->isp32_params, param, size);
} else {
/* left and right params for unit fast case */
size = sizeof(struct isp32_isp_params_cfg);
memcpy(params_vdev->isp32_params, param, size);
if (params_vdev->dev->unite_div == ISP_UNITE_DIV2)
memcpy(params_vdev->isp32_params + 1, param, size);
}
rkisp_alloc_internal_buf(params_vdev, params_vdev->isp32_params);
}

7222
drivers/media/platform/rockchip/isp/isp_params_v33.c Normal file
View File

File diff suppressed because it is too large Load Diff

171
drivers/media/platform/rockchip/isp/isp_params_v33.h Normal file
View File

@@ -0,0 +1,171 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2024 Rockchip Electronics Co., Ltd. */
#ifndef _RKISP_ISP_PARAM_V33_H
#define _RKISP_ISP_PARAM_V33_H
#include "common.h"
#include "isp_params.h"
#define ISP33_RAWHISTBIG_ROW_NUM 15
#define ISP33_RAWHISTBIG_COLUMN_NUM 15
#define ISP33_RAWHISTBIG_WEIGHT_REG_SIZE \
(ISP33_RAWHISTBIG_ROW_NUM * ISP33_RAWHISTBIG_COLUMN_NUM)
struct rkisp_isp_params_vdev;
struct rkisp_isp_params_ops_v33 {
void (*dpcc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_dpcc_cfg *arg, u32 id);
void (*dpcc_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*bls_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_bls_cfg *arg, u32 id);
void (*bls_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*lsc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp3x_lsc_cfg *arg, u32 id);
void (*lsc_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*awbgain_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_awb_gain_cfg *arg, u32 id);
void (*awbgain_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*debayer_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp33_debayer_cfg *arg, u32 id);
void (*debayer_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*ccm_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp33_ccm_cfg *arg, u32 id);
void (*ccm_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*goc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp3x_gammaout_cfg *arg, u32 id);
void (*goc_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*cproc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_cproc_cfg *arg, u32 id);
void (*cproc_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*ie_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*rawae0_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawaebig_meas_cfg *arg, u32 id);
void (*rawae0_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*rawae3_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawaebig_meas_cfg *arg, u32 id);
void (*rawae3_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*rawawb_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp33_rawawb_meas_cfg *arg, u32 id);
void (*rawawb_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*rawhst0_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawhistbig_cfg *arg, u32 id);
void (*rawhst0_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*rawhst3_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawhistbig_cfg *arg, u32 id);
void (*rawhst3_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*hdrdrc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp33_drc_cfg *arg,
enum rkisp_params_type type, u32 id);
void (*hdrdrc_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*hdrmge_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_hdrmge_cfg *arg,
enum rkisp_params_type type, u32 id);
void (*hdrmge_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*gic_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp33_gic_cfg *arg, u32 id);
void (*gic_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*enh_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp33_enh_cfg *arg, u32 id);
void (*enh_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*hist_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp33_hist_cfg *arg, u32 id);
void (*hist_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*hsv_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp33_hsv_cfg *arg, u32 id);
void (*hsv_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*ldch_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_ldch_cfg *arg, u32 id);
void (*ldch_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*ynr_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp33_ynr_cfg *arg, u32 id);
void (*ynr_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*cnr_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp33_cnr_cfg *arg, u32 id);
void (*cnr_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*sharp_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp33_sharp_cfg *arg, u32 id);
void (*sharp_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*bay3d_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp33_bay3d_cfg *arg, u32 id);
void (*bay3d_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*gain_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp3x_gain_cfg *arg, u32 id);
void (*gain_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*cac_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp33_cac_cfg *arg, u32 id);
void (*cac_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*csm_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp21_csm_cfg *arg, u32 id);
void (*cgc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp21_cgc_cfg *arg, u32 id);
};
struct rkisp_isp_params_val_v33 {
struct rkisp_dummy_buffer buf_ldch[ISP_UNITE_MAX][ISP3X_MESH_BUF_NUM];
u32 buf_ldch_idx[ISP_UNITE_MAX];
struct rkisp_dummy_buffer buf_info[RKISP_INFO2DDR_BUF_MAX];
u32 buf_info_owner;
u32 buf_info_cnt;
int buf_info_idx;
struct rkisp_dummy_buffer buf_3dnr_wgt;
struct rkisp_dummy_buffer buf_3dnr_iir;
struct rkisp_dummy_buffer buf_3dnr_ds;
struct rkisp_dummy_buffer buf_gain;
u32 bay3d_ds_size;
u32 bay3d_iir_size;
u32 bay3d_wgt_size;
u32 gain_size;
u32 hist_blk_num;
u32 enh_row;
u32 enh_col;
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V33)
int rkisp_init_params_vdev_v33(struct rkisp_isp_params_vdev *params_vdev);
void rkisp_uninit_params_vdev_v33(struct rkisp_isp_params_vdev *params_vdev);
#else
static inline int rkisp_init_params_vdev_v33(struct rkisp_isp_params_vdev *params_vdev) { return -EINVAL; }
static inline void rkisp_uninit_params_vdev_v33(struct rkisp_isp_params_vdev *params_vdev) {}
#endif
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V33_DBG)
int rkisp_get_params_v33(struct rkisp_isp_params_vdev *params_vdev, void *arg);
#else
static inline int rkisp_get_params_v33(struct rkisp_isp_params_vdev *params_vdev, void *arg)
{
pr_err("enable CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V33_DBG in kernel config\n");
return -EINVAL;
}
#endif
#endif /* _RKISP_ISP_PARAM_V33_H */

147
drivers/media/platform/rockchip/isp/isp_rockit.c
View File

@@ -22,6 +22,7 @@ struct rkisp_rockit_buffer {
struct list_head queue;
int buf_id;
u32 buff_addr;
void *vaddr;
};
static struct rkisp_stream *rkisp_rockit_get_stream(struct rockit_cfg *input_rockit_cfg)
@@ -52,6 +53,10 @@ static struct rkisp_stream *rkisp_rockit_get_stream(struct rockit_cfg *input_roc
return NULL;
}
if (ispdev->isp_ver == ISP_V33 &&
(input_rockit_cfg->nick_id == 3 || input_rockit_cfg->nick_id == 4))
return NULL;
switch (input_rockit_cfg->nick_id) {
case 0:
stream = &ispdev->cap_dev.stream[RKISP_STREAM_MP];
@@ -117,6 +122,7 @@ int rkisp_rockit_buf_queue(struct rockit_cfg *input_rockit_cfg)
if (input_rockit_cfg->is_alloc) {
struct dma_buf_attachment *dba;
struct sg_table *sgt;
struct iosys_map map;
for (i = 0; i < ROCKIT_BUF_NUM_MAX; i++) {
if (!stream_cfg->buff_id[i] && !stream_cfg->rkisp_buff[i]) {
@@ -147,6 +153,15 @@ int rkisp_rockit_buf_queue(struct rockit_cfg *input_rockit_cfg)
stream_cfg->buff_id[i] = 0;
return PTR_ERR(sgt);
}
isprk_buf->vaddr = NULL;
if (dma_buf_vmap(input_rockit_cfg->buf, &map) == 0)
isprk_buf->vaddr = map.vaddr;
if (rkisp_buf_dbg) {
u64 *data = isprk_buf->vaddr;
if (data)
*data = RKISP_DATA_CHECK;
}
isprk_buf->buff_addr = sg_dma_address(sgt->sgl);
get_dma_buf(input_rockit_cfg->buf);
isprk_buf->mpi_buf = input_rockit_cfg->mpibuf;
@@ -154,9 +169,6 @@ int rkisp_rockit_buf_queue(struct rockit_cfg *input_rockit_cfg)
isprk_buf->dba = dba;
isprk_buf->sgt = sgt;
stream_cfg->rkisp_buff[i] = isprk_buf;
for (i = 0; i < stream->out_isp_fmt.mplanes; i++)
isprk_buf->isp_buf.buff_addr[i] = isprk_buf->buff_addr;
}
if (ispdev->cap_dev.wrap_line && stream->id == RKISP_STREAM_MP) {
@@ -193,13 +205,36 @@ int rkisp_rockit_buf_queue(struct rockit_cfg *input_rockit_cfg)
}
if (stream->out_isp_fmt.mplanes == 1) {
for (i = 0; i < stream->out_isp_fmt.cplanes - 1; i++) {
height = stream->out_fmt.height;
bytesperline = stream->out_fmt.plane_fmt[i].bytesperline;
offset = (i == 0) ? bytesperline * height :
stream->out_fmt.plane_fmt[i].sizeimage;
isprk_buf->isp_buf.buff_addr[i + 1] =
isprk_buf->isp_buf.buff_addr[i] + offset;
u32 y_offs = input_rockit_cfg->y_offset;
u32 u_offs = input_rockit_cfg->u_offset;
u32 vir_w = input_rockit_cfg->vir_width;
u32 dma_addr = isprk_buf->buff_addr;
if (vir_w)
stream->out_fmt.plane_fmt[0].bytesperline = vir_w;
else
vir_w = stream->out_fmt.plane_fmt[0].bytesperline;
height = stream->out_fmt.height;
if (u_offs) {
offset = u_offs;
if (stream->out_isp_fmt.output_format == ISP32_MI_OUTPUT_YUV420)
stream->out_fmt.plane_fmt[1].sizeimage = vir_w * height / 2;
else
stream->out_fmt.plane_fmt[1].sizeimage = vir_w * height;
stream->out_fmt.plane_fmt[0].sizeimage = vir_w * height +
stream->out_fmt.plane_fmt[1].sizeimage;
} else {
offset = vir_w * height;
}
isprk_buf->isp_buf.buff_addr[0] = dma_addr + y_offs;
isprk_buf->isp_buf.buff_addr[1] = dma_addr + offset;
isprk_buf->isp_buf.vaddr[0] = NULL;
isprk_buf->isp_buf.vaddr[1] = NULL;
isprk_buf->isp_buf.vb.vb2_buf.planes[0].mem_priv = NULL;
if (isprk_buf->vaddr) {
isprk_buf->isp_buf.vaddr[0] = isprk_buf->vaddr + y_offs;
isprk_buf->isp_buf.vaddr[1] = isprk_buf->vaddr + offset;
isprk_buf->isp_buf.vb.vb2_buf.planes[0].mem_priv = isprk_buf->sgt;
}
}
@@ -214,7 +249,7 @@ int rkisp_rockit_buf_queue(struct rockit_cfg *input_rockit_cfg)
return 0;
}
int rkisp_rockit_buf_done(struct rkisp_stream *stream, int cmd)
int rkisp_rockit_buf_done(struct rkisp_stream *stream, int cmd, struct rkisp_buffer *curr_buf)
{
struct rkisp_device *dev = stream->ispdev;
struct rkisp_rockit_buffer *isprk_buf = NULL;
@@ -230,24 +265,36 @@ int rkisp_rockit_buf_done(struct rkisp_stream *stream, int cmd)
stream_cfg = &rockit_cfg->rkisp_dev_cfg[dev_id].rkisp_stream_cfg[stream->id];
if (cmd == ROCKIT_DVBM_END) {
isprk_buf =
container_of(stream->curr_buf, struct rkisp_rockit_buffer, isp_buf);
container_of(curr_buf, struct rkisp_rockit_buffer, isp_buf);
rockit_cfg->mpibuf = isprk_buf->mpi_buf;
rockit_cfg->frame.u64PTS = stream->curr_buf->vb.vb2_buf.timestamp;
rockit_cfg->frame.u64PTS = curr_buf->vb.vb2_buf.timestamp;
rockit_cfg->frame.u32TimeRef = stream->curr_buf->vb.sequence;
rockit_cfg->frame.u32TimeRef = curr_buf->vb.sequence;
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"%s stream:%d seq:%d buf:0x%x done\n",
__func__, stream->id,
stream->curr_buf->vb.sequence,
stream->curr_buf->buff_addr[0]);
"stream:%d seq:%d rockit buf done:0x%x\n",
stream->id,
curr_buf->vb.sequence,
curr_buf->buff_addr[0]);
if (rkisp_buf_dbg) {
u64 *data = isprk_buf->vaddr;
if (data && *data == RKISP_DATA_CHECK)
v4l2_info(&dev->v4l2_dev,
"rockit seq:%d data no update:%llx %llx\n",
curr_buf->vb.sequence,
*data, *(data + 1));
}
} else {
if (stream->ispdev->cap_dev.wrap_line &&
stream->id == RKISP_STREAM_MP) {
if (dev->is_first_double || stream_cfg->is_discard ||
stream->ops->is_stream_stopped(stream))
if (dev->skip_frame || stream_cfg->is_discard ||
stream->skip_frame || stream->ops->is_stream_stopped(stream)) {
if (stream->skip_frame)
stream->skip_frame--;
return 0;
}
} else if (stream_cfg->dst_fps) {
if (!stream_cfg->is_discard && !stream->curr_buf) {
rockit_cfg->is_qbuf = true;
@@ -267,6 +314,9 @@ int rkisp_rockit_buf_done(struct rkisp_stream *stream, int cmd)
rockit_cfg->frame.u64PTS = ns;
rockit_cfg->frame.u32TimeRef = seq;
if (dev->isp_ver == ISP_V33)
rockit_cfg->frame.ispEncCnt =
ISP33_ISP2ENC_FRM_CNT(rkisp_read(dev, ISP3X_ISP_DEBUG1, true));
}
rockit_cfg->is_color = !rkisp_read(dev, ISP3X_IMG_EFF_CTRL, true);
@@ -309,8 +359,12 @@ int rkisp_rockit_pause_stream(struct rockit_cfg *input_rockit_cfg)
return -EINVAL;
}
rockit_isp_ops.rkisp_stream_stop(stream);
v4l2_dbg(1, rkisp_debug, &stream->ispdev->v4l2_dev,
"%s stream:%d\n", __func__, stream->id);
rockit_isp_ops.rkisp_stream_stop(stream);
if (stream->ispdev->cap_dev.wrap_line && stream->id == RKISP_STREAM_MP)
rkisp_dvbm_deinit(stream->ispdev);
return 0;
}
EXPORT_SYMBOL(rkisp_rockit_pause_stream);
@@ -320,7 +374,7 @@ int rkisp_rockit_config_stream(struct rockit_cfg *input_rockit_cfg,
{
struct rkisp_stream *stream = NULL;
struct rkisp_buffer *isp_buf, *buf_temp;
int offset, i, ret;
int offset, ret;
unsigned long lock_flags = 0;
u32 reg, val, bytesperline;
@@ -330,6 +384,11 @@ int rkisp_rockit_config_stream(struct rockit_cfg *input_rockit_cfg,
pr_err("the stream is NULL");
return -EINVAL;
}
v4l2_dbg(1, rkisp_debug, &stream->ispdev->v4l2_dev,
"%s stream:%d %dx%d wrap:%d\n",
__func__, stream->id, width, height, wrap_line);
stream->ispdev->cap_dev.wrap_line = wrap_line;
stream->out_fmt.width = width;
stream->out_fmt.height = height;
@@ -364,14 +423,33 @@ int rkisp_rockit_config_stream(struct rockit_cfg *input_rockit_cfg,
stream->next_buf = NULL;
}
list_for_each_entry_safe(isp_buf, buf_temp, &stream->buf_queue, queue) {
struct rkisp_rockit_buffer *isprk_buf =
container_of(isp_buf, struct rkisp_rockit_buffer, isp_buf);
if (stream->out_isp_fmt.mplanes == 1) {
for (i = 0; i < stream->out_isp_fmt.cplanes - 1; i++) {
height = stream->out_fmt.height;
bytesperline = stream->out_fmt.plane_fmt[i].bytesperline;
offset = (i == 0) ? bytesperline * height :
stream->out_fmt.plane_fmt[i].sizeimage;
isp_buf->buff_addr[i + 1] = isp_buf->buff_addr[i] + offset;
u32 y_offs = input_rockit_cfg->y_offset;
u32 u_offs = input_rockit_cfg->u_offset;
u32 vir_w = input_rockit_cfg->vir_width;
u32 dma_addr = isprk_buf->buff_addr;
if (vir_w)
stream->out_fmt.plane_fmt[0].bytesperline = vir_w;
else
vir_w = stream->out_fmt.plane_fmt[0].bytesperline;
height = stream->out_fmt.height;
if (u_offs) {
offset = u_offs;
if (stream->out_isp_fmt.output_format == ISP32_MI_OUTPUT_YUV420)
stream->out_fmt.plane_fmt[1].sizeimage = vir_w * height / 2;
else
stream->out_fmt.plane_fmt[1].sizeimage = vir_w * height;
stream->out_fmt.plane_fmt[0].sizeimage = vir_w * height +
stream->out_fmt.plane_fmt[1].sizeimage;
} else {
offset = vir_w * height;
}
isp_buf->buff_addr[0] = dma_addr + y_offs;
isp_buf->buff_addr[1] = dma_addr + offset;
}
}
spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
@@ -392,12 +470,15 @@ int rkisp_rockit_resume_stream(struct rockit_cfg *input_rockit_cfg)
return -EINVAL;
}
stream->streaming = true;
v4l2_dbg(1, rkisp_debug, &stream->ispdev->v4l2_dev,
"%s stream:%d\n", __func__, stream->id);
ret = rockit_isp_ops.rkisp_stream_start(stream);
if (ret < 0) {
pr_err("stream id %d start failed\n", stream->id);
return -EINVAL;
}
stream->skip_frame = 2;
if (stream->ispdev->isp_state == ISP_STOP) {
stream->ispdev->isp_state = ISP_START;
rkisp_rdbk_trigger_event(stream->ispdev, T_CMD_QUEUE, NULL);
@@ -507,6 +588,12 @@ int rkisp_rockit_buf_free(struct rkisp_stream *stream)
if (stream_cfg->rkisp_buff[i]) {
isprk_buf = (struct rkisp_rockit_buffer *)stream_cfg->rkisp_buff[i];
if (isprk_buf->dba) {
if (isprk_buf->vaddr) {
struct iosys_map map = IOSYS_MAP_INIT_VADDR(isprk_buf->vaddr);
dma_buf_vunmap(isprk_buf->dmabuf, &map);
isprk_buf->vaddr = NULL;
}
if (isprk_buf->sgt) {
dma_buf_unmap_attachment(isprk_buf->dba,
isprk_buf->sgt,
@@ -695,7 +782,7 @@ void rkisp_rockit_frame_start(struct rkisp_device *dev)
stream = &dev->cap_dev.stream[i];
if (!stream->streaming)
continue;
rkisp_rockit_buf_done(stream, ROCKIT_DVBM_START);
rkisp_rockit_buf_done(stream, ROCKIT_DVBM_START, stream->curr_buf);
rkisp_rockit_ctrl_fps(stream);
}
}

64
drivers/media/platform/rockchip/isp/isp_stats.c
View File

@@ -15,6 +15,7 @@
#include "isp_stats_v3x.h"
#include "isp_stats_v32.h"
#include "isp_stats_v39.h"
#include "isp_stats_v33.h"
#define STATS_NAME DRIVER_NAME "-statistics"
#define RKISP_ISP_STATS_REQ_BUFS_MIN 2
@@ -91,6 +92,10 @@ static int rkisp_stats_fh_open(struct file *filp)
if (!stats->dev->is_probe_end)
return -EINVAL;
ret = rkisp_cond_poll_timeout(!stats->dev->is_thunderboot,
5000, 1000 * USEC_PER_MSEC);
if (ret)
return ret;
ret = v4l2_fh_open(filp);
if (!ret) {
@@ -150,7 +155,7 @@ static void rkisp_stats_vb2_buf_queue(struct vb2_buffer *vb)
unsigned long flags;
stats_buf->vaddr[0] = vb2_plane_vaddr(vb, 0);
if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V39) {
if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V39 || dev->isp_ver == ISP_V33) {
struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
stats_buf->buff_addr[0] = sg_dma_address(sgt->sgl);
@@ -164,6 +169,22 @@ static void rkisp_stats_vb2_buf_queue(struct vb2_buffer *vb)
if (dev->isp_ver == ISP_V32 && dev->is_pre_on) {
struct rkisp32_isp_stat_buffer *buf = stats_dev->stats_buf[0].vaddr;
if (dev->isp_state & ISP_START && stats_buf->vaddr[0] &&
buf && !buf->frame_id && buf->meas_type) {
dev_info(dev->dev,
"tb stat seq:%d meas_type:0x%x\n",
buf->frame_id, buf->meas_type);
memcpy(stats_buf->vaddr[0], buf, size);
buf->meas_type = 0;
vb2_set_plane_payload(vb, 0, size);
vbuf->sequence = buf->frame_id;
spin_unlock_irqrestore(&stats_dev->rd_lock, flags);
vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
return;
}
} else if (dev->isp_ver == ISP_V33 && dev->is_pre_on) {
struct rkisp33_stat_buffer *buf = stats_dev->stats_buf[0].vaddr;
if (dev->isp_state & ISP_START && stats_buf->vaddr[0] &&
buf && !buf->frame_id && buf->meas_type) {
dev_info(dev->dev,
@@ -259,7 +280,8 @@ static int rkisp_stats_init_vb2_queue(struct vb2_queue *q,
q->drv_priv = stats_vdev;
q->ops = &rkisp_stats_vb2_ops;
if (stats_vdev->dev->isp_ver == ISP_V32 ||
stats_vdev->dev->isp_ver == ISP_V39) {
stats_vdev->dev->isp_ver == ISP_V39 ||
stats_vdev->dev->isp_ver == ISP_V33) {
q->mem_ops = stats_vdev->dev->hw_dev->mem_ops;
if (stats_vdev->dev->hw_dev->is_dma_contig)
q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
@@ -293,41 +315,47 @@ static void rkisp_stats_readout_task(unsigned long data)
static void rkisp_init_stats_vdev(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
stats_vdev->rd_buf_idx = 0;
stats_vdev->wr_buf_idx = 0;
memset(stats_vdev->stats_buf, 0, sizeof(stats_vdev->stats_buf));
stats_vdev->vdev_fmt.fmt.meta.dataformat = V4L2_META_FMT_RK_ISP1_STAT_3A;
if (stats_vdev->dev->isp_ver <= ISP_V13)
if (dev->isp_ver <= ISP_V13)
rkisp_init_stats_vdev_v1x(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V21)
else if (dev->isp_ver == ISP_V21)
rkisp_init_stats_vdev_v21(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V20)
else if (dev->isp_ver == ISP_V20)
rkisp_init_stats_vdev_v2x(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V30)
else if (dev->isp_ver == ISP_V30)
rkisp_init_stats_vdev_v3x(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V32 ||
stats_vdev->dev->isp_ver == ISP_V32_L)
else if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V32_L)
rkisp_init_stats_vdev_v32(stats_vdev);
else
else if (dev->isp_ver == ISP_V39)
rkisp_init_stats_vdev_v39(stats_vdev);
else if (dev->isp_ver == ISP_V33)
rkisp_init_stats_vdev_v33(stats_vdev);
}
static void rkisp_uninit_stats_vdev(struct rkisp_isp_stats_vdev *stats_vdev)
{
if (stats_vdev->dev->isp_ver <= ISP_V13)
struct rkisp_device *dev = stats_vdev->dev;
if (dev->isp_ver <= ISP_V13)
rkisp_uninit_stats_vdev_v1x(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V21)
else if (dev->isp_ver == ISP_V21)
rkisp_uninit_stats_vdev_v21(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V20)
else if (dev->isp_ver == ISP_V20)
rkisp_uninit_stats_vdev_v2x(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V30)
else if (dev->isp_ver == ISP_V30)
rkisp_uninit_stats_vdev_v3x(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V32 ||
stats_vdev->dev->isp_ver == ISP_V32_L)
else if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V32_L)
rkisp_uninit_stats_vdev_v32(stats_vdev);
else
else if (dev->isp_ver == ISP_V39)
rkisp_uninit_stats_vdev_v39(stats_vdev);
else if (dev->isp_ver == ISP_V33)
rkisp_uninit_stats_vdev_v33(stats_vdev);
}
void rkisp_stats_rdbk_enable(struct rkisp_isp_stats_vdev *stats_vdev, bool en)
@@ -348,6 +376,8 @@ void rkisp_stats_first_ddr_config(struct rkisp_isp_stats_vdev *stats_vdev)
rkisp_stats_first_ddr_config_v32(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V39)
rkisp_stats_first_ddr_config_v39(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V33)
rkisp_stats_first_ddr_config_v33(stats_vdev);
}
void rkisp_stats_next_ddr_config(struct rkisp_isp_stats_vdev *stats_vdev)
@@ -356,6 +386,8 @@ void rkisp_stats_next_ddr_config(struct rkisp_isp_stats_vdev *stats_vdev)
rkisp_stats_next_ddr_config_v32(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V39)
rkisp_stats_next_ddr_config_v39(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V33)
rkisp_stats_next_ddr_config_v33(stats_vdev);
}
void rkisp_stats_isr(struct rkisp_isp_stats_vdev *stats_vdev,

5
drivers/media/platform/rockchip/isp/isp_stats_v32.c
View File

@@ -548,7 +548,6 @@ rkisp_stats_send_meas(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp_isp_readout_work *meas_work)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_hw_dev *hw = dev->hw_dev;
struct rkisp_isp_params_vdev *params_vdev = &dev->params_vdev;
struct rkisp_buffer *cur_buf = stats_vdev->cur_buf;
struct rkisp32_isp_stat_buffer *cur_stat_buf = NULL;
@@ -573,7 +572,7 @@ rkisp_stats_send_meas(struct rkisp_isp_stats_vdev *stats_vdev,
}
/* buffer done when frame of right handle */
if (hw->unite == ISP_UNITE_ONE) {
if (dev->unite_div > ISP_UNITE_DIV1) {
if (dev->unite_index == ISP_UNITE_LEFT) {
cur_buf = NULL;
is_dummy = false;
@@ -584,7 +583,7 @@ rkisp_stats_send_meas(struct rkisp_isp_stats_vdev *stats_vdev,
}
}
if (hw->unite != ISP_UNITE_ONE || dev->unite_index == ISP_UNITE_RIGHT) {
if (dev->unite_div < ISP_UNITE_DIV2 || dev->unite_index == ISP_UNITE_RIGHT) {
/* config buf for next frame */
stats_vdev->cur_buf = NULL;
if (stats_vdev->nxt_buf) {

562
drivers/media/platform/rockchip/isp/isp_stats_v33.c Normal file
View File

@@ -0,0 +1,562 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2024 Rockchip Electronics Co., Ltd. */
#include <linux/delay.h>
#include <linux/kfifo.h>
#include <linux/rk-isp32-config.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ioctl.h>
#include <media/videobuf2-core.h>
#include "dev.h"
#include "regs.h"
#include "common.h"
#include "isp_stats.h"
#include "isp_stats_v33.h"
#include "isp_params_v33.h"
#define ISP33_3A_MEAS_DONE BIT(31)
static void isp3_module_done(struct rkisp_isp_stats_vdev *stats_vdev, u32 reg, u32 value)
{
void __iomem *base = stats_vdev->dev->hw_dev->base_addr;
writel(value, base + reg);
}
static u32 isp3_stats_read(struct rkisp_isp_stats_vdev *stats_vdev, u32 addr)
{
return rkisp_read(stats_vdev->dev, addr, true);
}
static void isp3_stats_write(struct rkisp_isp_stats_vdev *stats_vdev,
u32 addr, u32 value)
{
rkisp_write(stats_vdev->dev, addr, value, true);
}
static int
rkisp_stats_get_sharp_stats(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp33_stat_buffer *pbuf)
{
struct isp33_sharp_stat *sharp;
u32 i, val;
if (!pbuf)
return 0;
val = isp3_stats_read(stats_vdev, ISP3X_SHARP_EN);
if (val & 0x1) {
sharp = &pbuf->stat.sharp;
for (i = 0; i < ISP33_SHARP_NOISE_CURVE_NUM / 2; i++) {
val = isp3_stats_read(stats_vdev, ISP33_SHARP_NOISE_CURVE0 + i * 4);
sharp->noise_curve[i * 2] = val & 0x7ff;
sharp->noise_curve[i * 2 + 1] = (val >> 16) & 0x7ff;
}
val = isp3_stats_read(stats_vdev, ISP33_SHARP_NOISE_CURVE8);
sharp->noise_curve[i * 2] = val & 0x7ff;
pbuf->meas_type |= ISP33_STAT_SHARP;
}
return 0;
}
static int
rkisp_stats_get_bay3d_stats(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp33_stat_buffer *pbuf)
{
struct isp33_bay3d_stat *bay3d;
u32 i, val;
if (!pbuf)
return 0;
val = isp3_stats_read(stats_vdev, ISP33_BAY3D_CTRL0);
if (val & 0x1) {
bay3d = &pbuf->stat.bay3d;
val = isp3_stats_read(stats_vdev, ISP33_BAY3D_TNRSUM);
bay3d->sigma_num = val;
for (i = 0; i < ISP33_BAY3D_TNRSIG_NUM / 2; i++) {
val = isp3_stats_read(stats_vdev, ISP33_BAY3D_TNRYO0 + i * 4);
bay3d->sigma_y[i * 2] = val & 0xfff;
bay3d->sigma_y[i * 2 + 1] = (val >> 16) & 0xfff;
}
pbuf->meas_type |= ISP33_STAT_BAY3D;
}
return 0;
}
static int
rkisp_stats_get_hist_stats(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp33_stat_buffer *pbuf)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_isp_params_vdev *params = &dev->params_vdev;
struct rkisp_isp_params_val_v33 *priv_val = params->priv_val;
struct isp33_isp_params_cfg *params_rec = params->isp33_params + dev->unite_index;
struct isp33_hist_cfg *arg_rec = &params_rec->others.hist_cfg;
struct isp33_hist_stat *hist;
int val, i, j, timeout;
val = isp3_stats_read(stats_vdev, ISP33_HIST_CTRL);
if (val & 0x1) {
val = isp3_stats_read(stats_vdev, ISP33_HIST_STAB);
arg_rec->stab_frame_cnt0 = val & 0xf;
arg_rec->stab_frame_cnt1 = (val & 0xf0) >> 4;
for (i = 0; i < priv_val->hist_blk_num; i++) {
val = ISP33_IIR_RD_ID(i) | ISP33_IIR_RD_P;
isp3_stats_write(stats_vdev, ISP33_HIST_RW, val);
timeout = 5;
while (timeout--) {
val = isp3_stats_read(stats_vdev, ISP33_HIST_RW);
if (val & ISP33_IIR_RDATA_VAL)
break;
udelay(2);
}
if (timeout < 0) {
v4l2_warn(&dev->v4l2_dev, "%s hist read:%d timeout\n", __func__, i);
return 0;
}
for (j = 0; j < ISP33_HIST_IIR_NUM / 2; j++) {
val = isp3_stats_read(stats_vdev, ISP33_HIST_IIR0 + 4 * j);
arg_rec->iir[i][2 * j] = val & 0x3FF;
arg_rec->iir[i][2 * j + 1] = val >> 16;
}
}
if (dev->is_frm_rd)
arg_rec->iir_wr = true;
if (pbuf) {
hist = &pbuf->stat.hist;
memcpy(hist->iir, arg_rec->iir, sizeof(hist->iir));
pbuf->meas_type |= ISP33_STAT_HIST;
}
}
return 0;
}
static int
rkisp_stats_get_enh_stats(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp33_stat_buffer *pbuf)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_isp_params_vdev *params = &dev->params_vdev;
struct rkisp_isp_params_val_v33 *priv_val = params->priv_val;
struct isp33_isp_params_cfg *params_rec = params->isp33_params + dev->unite_index;
struct isp33_enh_cfg *arg_rec = &params_rec->others.enh_cfg;
struct isp33_enh_stat *enh;
int val, i, j, timeout;
val = isp3_stats_read(stats_vdev, ISP33_ENH_CTRL);
if (val & 0x1) {
enh = &pbuf->stat.enh;
val = isp3_stats_read(stats_vdev, ISP33_ENH_PRE_FRAME);
arg_rec->pre_wet_frame_cnt0 = val & 0xf;
arg_rec->pre_wet_frame_cnt1 = (val & 0xf0) >> 4;
for (i = 0; i < priv_val->enh_row; i++) {
val = ISP33_IIR_RD_ID(i) | ISP33_IIR_RD_P;
isp3_stats_write(stats_vdev, ISP33_ENH_IIR_RW, val);
timeout = 5;
while (timeout--) {
val = isp3_stats_read(stats_vdev, ISP33_ENH_IIR_RW);
if (val & ISP33_IIR_RDATA_VAL)
break;
udelay(2);
}
if (timeout < 0) {
v4l2_warn(&dev->v4l2_dev, "%s enh read:%d timeout\n", __func__, i);
return 0;
}
for (j = 0; j < priv_val->enh_col / 4; j++) {
val = isp3_stats_read(stats_vdev, ISP33_ENH_IIR0 + 4 * j);
arg_rec->iir[i][4 * j] = val & 0xFF;
arg_rec->iir[i][4 * j + 1] = (val & 0xff00) >> 8;
arg_rec->iir[i][4 * j + 2] = (val & 0xff0000) >> 16;
arg_rec->iir[i][4 * j + 3] = (val & 0xff000000) >> 24;
}
}
if (dev->is_frm_rd)
arg_rec->iir_wr = true;
if (pbuf) {
enh = &pbuf->stat.enh;
memcpy(enh->iir, arg_rec->iir, sizeof(enh->iir));
pbuf->meas_type |= ISP33_STAT_ENH;
}
}
return 0;
}
static int
rkisp_stats_update_buf(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_buffer *buf;
unsigned long flags;
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize / dev->unite_div;
u32 val, addr = 0, offset = 0;
int i, ret = 0;
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
if (!stats_vdev->nxt_buf && !list_empty(&stats_vdev->stat)) {
buf = list_first_entry(&stats_vdev->stat,
struct rkisp_buffer, queue);
list_del(&buf->queue);
stats_vdev->nxt_buf = buf;
}
spin_unlock_irqrestore(&stats_vdev->rd_lock, flags);
if (stats_vdev->nxt_buf) {
addr = stats_vdev->nxt_buf->buff_addr[0];
if (!dev->hw_dev->is_single) {
stats_vdev->cur_buf = stats_vdev->nxt_buf;
stats_vdev->nxt_buf = NULL;
}
} else if (stats_vdev->stats_buf[0].mem_priv) {
addr = stats_vdev->stats_buf[0].dma_addr;
} else {
ret = -EINVAL;
}
if (addr) {
for (i = 0; i < dev->unite_div; i++) {
val = addr + i * size;
rkisp_idx_write(dev, ISP39_W3A_AEBIG_ADDR, val, i, false);
offset = sizeof(struct isp33_rawae_stat) +
sizeof(struct isp33_rawhist_stat);
val += offset;
rkisp_idx_write(dev, ISP39_W3A_AE0_ADDR, val, i, false);
val += offset;
rkisp_idx_write(dev, ISP39_W3A_AWB_ADDR, val, i, false);
}
v4l2_dbg(4, rkisp_debug, &dev->v4l2_dev,
"%s BASE:0x%x SHD AEBIG:0x%x AE0:0x%x AWB:0x%x\n",
__func__, addr,
isp3_stats_read(stats_vdev, ISP39_W3A_AEBIG_ADDR_SHD),
isp3_stats_read(stats_vdev, ISP39_W3A_AE0_ADDR_SHD),
isp3_stats_read(stats_vdev, ISP39_W3A_AWB_ADDR_SHD));
}
return ret;
}
static void
rkisp_stats_info2ddr(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp33_stat_buffer *pbuf)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_isp_params_val_v33 *priv_val;
struct rkisp_dummy_buffer *buf;
int idx, buf_fd = -1;
u32 reg = 0, ctrl, mask;
if (dev->is_aiisp_en)
return;
priv_val = dev->params_vdev.priv_val;
if (!priv_val->buf_info_owner && priv_val->buf_info_idx >= 0) {
priv_val->buf_info_idx = -1;
rkisp_clear_bits(dev, ISP3X_GAIN_CTRL, ISP3X_GAIN_2DDR_EN, false);
rkisp_clear_bits(dev, ISP3X_RAWAWB_CTRL, ISP32_RAWAWB_2DDR_PATH_EN, false);
return;
}
if (priv_val->buf_info_owner == RKISP_INFO2DRR_OWNER_GAIN) {
reg = ISP3X_GAIN_CTRL;
ctrl = ISP3X_GAIN_2DDR_EN;
mask = ISP3X_GAIN_2DDR_EN;
} else {
reg = ISP3X_RAWAWB_CTRL;
ctrl = ISP32_RAWAWB_2DDR_PATH_EN;
mask = ISP32_RAWAWB_2DDR_PATH_EN | ISP32_RAWAWB_2DDR_PATH_DS;
}
idx = priv_val->buf_info_idx;
if (idx >= 0) {
buf = &priv_val->buf_info[idx];
rkisp_finish_buffer(dev, buf);
v4l2_dbg(4, rkisp_debug, &dev->v4l2_dev,
"%s data:0x%x 0x%x:0x%x\n", __func__,
*(u32 *)buf->vaddr, reg, rkisp_read(dev, reg, true));
if (*(u32 *)buf->vaddr != RKISP_INFO2DDR_BUF_INIT && pbuf &&
(reg != ISP3X_RAWAWB_CTRL ||
!(rkisp_read(dev, reg, true) & ISP32_RAWAWB_2DDR_PATH_ERR))) {
pbuf->stat.info2ddr.buf_fd = buf->dma_fd;
pbuf->stat.info2ddr.owner = priv_val->buf_info_owner;
pbuf->meas_type |= ISP33_STAT_INFO2DDR;
buf_fd = buf->dma_fd;
} else if (reg == ISP3X_RAWAWB_CTRL &&
rkisp_read(dev, reg, true) & ISP32_RAWAWB_2DDR_PATH_ERR) {
v4l2_warn(&dev->v4l2_dev, "rawawb2ddr path error idx:%d\n", idx);
} else {
u32 v0 = rkisp_read(dev, reg, false);
u32 v1 = rkisp_read_reg_cache(dev, reg);
if ((v0 & mask) != (v1 & mask))
rkisp_write(dev, reg, v0 | (v1 & mask), false);
}
if (buf_fd == -1)
return;
}
/* get next unused buf to hw */
for (idx = 0; idx < priv_val->buf_info_cnt; idx++) {
buf = &priv_val->buf_info[idx];
if (*(u32 *)buf->vaddr == RKISP_INFO2DDR_BUF_INIT)
break;
}
if (idx == priv_val->buf_info_cnt) {
rkisp_clear_bits(dev, reg, ctrl, false);
priv_val->buf_info_idx = -1;
} else {
buf = &priv_val->buf_info[idx];
rkisp_write(dev, ISP3X_MI_GAIN_WR_BASE, buf->dma_addr, false);
if (dev->hw_dev->is_single)
rkisp_write(dev, ISP3X_MI_WR_CTRL2, ISP3X_GAINSELF_UPD, true);
if (priv_val->buf_info_idx < 0)
rkisp_set_bits(dev, reg, 0, ctrl, false);
priv_val->buf_info_idx = idx;
}
}
static void
rkisp_stats_send_meas_v33(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp_isp_readout_work *meas_work)
{
struct rkisp_isp_params_vdev *params_vdev = &stats_vdev->dev->params_vdev;
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_buffer *cur_buf = stats_vdev->cur_buf;
struct rkisp33_stat_buffer *cur_stat_buf = NULL;
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize;
u32 val, w3a_int, cur_frame_id = meas_work->frame_id;
bool is_dummy = false;
unsigned long flags;
w3a_int = isp3_stats_read(stats_vdev, ISP39_W3A_INT_STAT);
if (w3a_int)
isp3_stats_write(stats_vdev, ISP39_W3A_INT_STAT, w3a_int);
if (!stats_vdev->rdbk_drop) {
if (!cur_buf && stats_vdev->stats_buf[0].mem_priv) {
rkisp_finish_buffer(stats_vdev->dev, &stats_vdev->stats_buf[0]);
cur_stat_buf = stats_vdev->stats_buf[0].vaddr;
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
is_dummy = true;
} else if (cur_buf) {
cur_stat_buf = cur_buf->vaddr[0];
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
}
/* buffer done when frame of right handle */
if (dev->unite_div > ISP_UNITE_DIV1) {
if (dev->unite_index == ISP_UNITE_LEFT) {
cur_buf = NULL;
is_dummy = false;
} else if (cur_stat_buf) {
cur_stat_buf = (void *)cur_stat_buf + size / 2;
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
}
}
if (dev->unite_div < ISP_UNITE_DIV2 || dev->unite_index == ISP_UNITE_RIGHT) {
/* config buf for next frame */
stats_vdev->cur_buf = NULL;
if (stats_vdev->nxt_buf) {
stats_vdev->cur_buf = stats_vdev->nxt_buf;
stats_vdev->nxt_buf = NULL;
}
rkisp_stats_update_buf(stats_vdev);
}
} else {
cur_buf = NULL;
}
if (w3a_int & ISP39_W3A_INT_ERR_MASK) {
val = isp3_stats_read(stats_vdev, ISP3X_RAWAE_BIG1_BASE);
if (val & ISP33_3A_MEAS_DONE)
isp3_module_done(stats_vdev, ISP3X_RAWAE_BIG1_BASE, val);
val = isp3_stats_read(stats_vdev, ISP3X_RAWAE_LITE_BASE);
if (val & ISP33_3A_MEAS_DONE)
isp3_module_done(stats_vdev, ISP3X_RAWAE_LITE_BASE, val);
val = isp3_stats_read(stats_vdev, ISP3X_RAWHIST_BIG1_BASE);
if (val & ISP33_3A_MEAS_DONE)
isp3_module_done(stats_vdev, ISP3X_RAWHIST_BIG1_BASE, val);
val = isp3_stats_read(stats_vdev, ISP3X_RAWHIST_LITE_BASE);
if (val & ISP33_3A_MEAS_DONE)
isp3_module_done(stats_vdev, ISP3X_RAWHIST_LITE_BASE, val);
val = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_BASE);
if (val & ISP33_3A_MEAS_DONE)
isp3_module_done(stats_vdev, ISP3X_RAWAWB_BASE, val);
v4l2_warn(&dev->v4l2_dev,
"id:%d stats seq:%d error:0x%x overflow(aebig:%d ae0:%d awb:%d wcfifo(wr:%d rd:%d))\n",
dev->unite_index, cur_frame_id, w3a_int,
!!(w3a_int & ISP39_W3A_INT_AEBIG_OVF),
!!(w3a_int & ISP39_W3A_INT_AE0_OVF),
!!(w3a_int & ISP39_W3A_INT_AWB_OVF),
!!(w3a_int & ISP39_W3A_INT_WCFIFO_WR_ERR),
!!(w3a_int & ISP39_W3A_INT_WCFIFO_RD_ERR));
} else {
if (meas_work->isp3a_ris & ISP3X_3A_RAWAWB && cur_stat_buf)
cur_stat_buf->meas_type |= ISP33_STAT_RAWAWB;
if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_BIG && cur_stat_buf)
cur_stat_buf->meas_type |= ISP33_STAT_RAWAE3;
if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_BIG && cur_stat_buf)
cur_stat_buf->meas_type |= ISP33_STAT_RAWHST3;
if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_CH0 && cur_stat_buf)
cur_stat_buf->meas_type |= ISP33_STAT_RAWAE0;
if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_CH0 && cur_stat_buf)
cur_stat_buf->meas_type |= ISP33_STAT_RAWHST0;
}
if (meas_work->isp_ris & ISP3X_FRAME) {
rkisp_stats_get_bay3d_stats(stats_vdev, cur_stat_buf);
rkisp_stats_get_sharp_stats(stats_vdev, cur_stat_buf);
rkisp_stats_get_enh_stats(stats_vdev, cur_stat_buf);
rkisp_stats_get_hist_stats(stats_vdev, cur_stat_buf);
}
if (cur_stat_buf && (dev->is_first_double || dev->is_wait_aiq)) {
cur_stat_buf->meas_type |= ISP33_STAT_RTT_FST;
dev_info(dev->dev, "stats seq:%d meas_type:0x%x for fast\n",
cur_frame_id, cur_stat_buf->meas_type);
}
if (is_dummy) {
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
if (!list_empty(&stats_vdev->stat)) {
cur_buf = list_first_entry(&stats_vdev->stat, struct rkisp_buffer, queue);
list_del(&cur_buf->queue);
}
spin_unlock_irqrestore(&stats_vdev->rd_lock, flags);
if (cur_buf) {
memcpy(cur_buf->vaddr[0], stats_vdev->stats_buf[0].vaddr, size);
cur_stat_buf = cur_buf->vaddr[0];
}
}
if (cur_buf && cur_stat_buf) {
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
cur_stat_buf->stat.info2ddr.buf_fd = -1;
cur_stat_buf->stat.info2ddr.owner = 0;
rkisp_stats_info2ddr(stats_vdev, cur_stat_buf);
vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0, size);
cur_buf->vb.sequence = cur_frame_id;
cur_buf->vb.vb2_buf.timestamp = meas_work->timestamp;
vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
}
v4l2_dbg(4, rkisp_debug, &stats_vdev->dev->v4l2_dev,
"%s seq:%d params_id:%d ris:0x%x buf:%p meas_type:0x%x\n",
__func__,
cur_frame_id, params_vdev->cur_frame_id, meas_work->isp3a_ris,
cur_buf, !cur_stat_buf ? 0 : cur_stat_buf->meas_type);
}
static void
rkisp_stats_isr_v33(struct rkisp_isp_stats_vdev *stats_vdev,
u32 isp_ris, u32 isp3a_ris)
{
struct rkisp_isp_readout_work work;
u32 cur_frame_id, isp_mis_tmp = 0;
u32 temp_isp3a_ris;
rkisp_dmarx_get_frame(stats_vdev->dev, &cur_frame_id, NULL, NULL, true);
temp_isp3a_ris = isp3_stats_read(stats_vdev, ISP3X_ISP_3A_RIS);
isp_mis_tmp = temp_isp3a_ris;
if (isp_mis_tmp) {
isp3_stats_write(stats_vdev, ISP3X_ISP_3A_ICR, isp_mis_tmp);
isp_mis_tmp &= isp3_stats_read(stats_vdev, ISP3X_ISP_3A_MIS);
if (isp_mis_tmp)
v4l2_err(stats_vdev->vnode.vdev.v4l2_dev,
"isp3A icr 3A info err: 0x%x 0x%x\n",
isp_mis_tmp, isp3a_ris);
}
if (isp_ris & ISP3X_FRAME) {
work.readout = RKISP_ISP_READOUT_MEAS;
work.frame_id = cur_frame_id;
work.isp_ris = isp_ris;
work.isp3a_ris = temp_isp3a_ris;
work.timestamp = ktime_get_ns();
rkisp_stats_send_meas_v33(stats_vdev, &work);
}
}
static void
rkisp_get_stat_size_v33(struct rkisp_isp_stats_vdev *stats_vdev,
unsigned int sizes[])
{
int mult = stats_vdev->dev->unite_div;
sizes[0] = ALIGN(sizeof(struct rkisp33_stat_buffer), 16);
sizes[0] *= mult;
stats_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v33,
.send_meas = rkisp_stats_send_meas_v33,
.get_stat_size = rkisp_get_stat_size_v33,
};
void rkisp_stats_first_ddr_config_v33(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
u32 val, size = 0, div = dev->unite_div;
if (dev->isp_sdev.in_fmt.fmt_type == FMT_YUV)
return;
rkisp_get_stat_size_v33(stats_vdev, &size);
stats_vdev->stats_buf[0].is_need_vaddr = true;
stats_vdev->stats_buf[0].size = size;
if (rkisp_alloc_buffer(dev, &stats_vdev->stats_buf[0]))
v4l2_warn(&dev->v4l2_dev, "stats alloc buf fail\n");
else
memset(stats_vdev->stats_buf[0].vaddr, 0, size);
if (rkisp_stats_update_buf(stats_vdev) < 0) {
v4l2_err(&dev->v4l2_dev, "no stats buf to enable w3a\n");
return;
}
rkisp_unite_set_bits(dev, ISP3X_SWS_CFG, 0, ISP3X_3A_DDR_WRITE_EN, false);
val = ISP39_W3A_EN | ISP39_W3A_AUTO_CLR_EN | ISP39_W3A_FORCE_UPD;
rkisp_unite_write(dev, ISP39_W3A_CTRL0, val, false);
rkisp_unite_write(dev, ISP39_W3A_WR_SIZE, size / div, false);
if (stats_vdev->nxt_buf) {
stats_vdev->cur_buf = stats_vdev->nxt_buf;
stats_vdev->nxt_buf = NULL;
}
}
void rkisp_stats_next_ddr_config_v33(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_hw_dev *hw = dev->hw_dev;
if (!stats_vdev->streamon || dev->isp_sdev.in_fmt.fmt_type == FMT_YUV)
return;
/* pingpong buf */
if (hw->is_single)
rkisp_stats_update_buf(stats_vdev);
}
void rkisp_init_stats_vdev_v33(struct rkisp_isp_stats_vdev *stats_vdev)
{
stats_vdev->ops = &rkisp_isp_stats_ops_tbl;
}
void rkisp_uninit_stats_vdev_v33(struct rkisp_isp_stats_vdev *stats_vdev)
{
}

26
drivers/media/platform/rockchip/isp/isp_stats_v33.h Normal file
View File

@@ -0,0 +1,26 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2024 Rockchip Electronics Co., Ltd. */
#ifndef _RKISP_STATS_V33_H
#define _RKISP_STATS_V33_H
#include <linux/rk-isp1-config.h>
#include <linux/interrupt.h>
#include <linux/kfifo.h>
#include "common.h"
struct rkisp_isp_stats_vdev;
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V33)
void rkisp_stats_first_ddr_config_v33(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_stats_next_ddr_config_v33(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_init_stats_vdev_v33(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_uninit_stats_vdev_v33(struct rkisp_isp_stats_vdev *stats_vdev);
#else
static inline void rkisp_stats_first_ddr_config_v33(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_stats_next_ddr_config_v33(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_init_stats_vdev_v33(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_uninit_stats_vdev_v33(struct rkisp_isp_stats_vdev *stats_vdev) {}
#endif
#endif /* _RKISP_ISP_STATS_V33_H */

156
drivers/media/platform/rockchip/isp/procfs.c
View File

@@ -12,6 +12,7 @@
#include "regs_v2x.h"
#include "isp_params_v3x.h"
#include "isp_params_v32.h"
#include "isp_params_v33.h"
#include "isp_params_v39.h"
#ifdef CONFIG_PROC_FS
@@ -980,6 +981,157 @@ static void isp39_show(struct rkisp_device *dev, struct seq_file *p)
!!(val & BIT(3)), !!(val & BIT(2)), !!(val & BIT(1)), !!(val & BIT(0)));
}
static void isp33_show(struct rkisp_device *dev, struct seq_file *p)
{
struct rkisp_isp_params_val_v33 *priv = dev->params_vdev.priv_val;
u32 full_range_flg = CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA | CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA;
static const char * const effect[] = { "OFF", "BLACKWHITE" };
u32 val, tmp;
val = rkisp_read(dev, ISP3X_SWS_CFG, false);
tmp = rkisp_read(dev, ISP3X_SWS_CFG, true);
seq_printf(p, "%-10s %s wrap:%d isp2enc(path_en:%d pipe_en:%d hold:%d)\n", "ISP2ENC",
dev->cap_dev.wrap_line ? "online" : "offline",
dev->cap_dev.wrap_line,
!!(val & BIT(5)), !!(val & BIT(1)), !!(tmp & BIT(31)));
tmp = rkisp_read(dev, ISP32_MI_WR_VFLIP_CTRL, false);
val = rkisp_read(dev, ISP3X_ISP_CTRL0, false);
seq_printf(p, "%-10s mirror:%d flip(mp:%d sp:%d bp:%d)\n",
"MIR_FLIP", !!(val & BIT(5)),
!!(tmp & BIT(0)), !!(tmp & BIT(1)), !!(tmp & BIT(2)));
val = rkisp_read(dev, ISP3X_GIC_CONTROL, false);
seq_printf(p, "%-10s %s(0x%x) bypass:%d\n", "GIC", (val & 1) ? "ON" : "OFF",
val, !!(val & BIT(1)));
val = rkisp_read(dev, ISP3X_CAC_CTRL, false);
seq_printf(p, "%-10s %s(0x%x) bypass:%d\n", "CAC", (val & (BIT(0) | BIT(31))) ? "ON" : "OFF",
val, !!(val & (BIT(1) | BIT(30))));
val = rkisp_read(dev, ISP3X_ISP_CTRL0, false);
seq_printf(p, "%-10s %s(0x%x) (gain0:0x%08x 0x%08x gain1:0x%x 0x%x)\n", "AWBGAIN",
(val & BIT(7)) ? "ON" : "OFF", val,
rkisp_read(dev, ISP3X_ISP_AWB_GAIN0_G, false),
rkisp_read(dev, ISP3X_ISP_AWB_GAIN0_RB, false),
rkisp_read(dev, ISP32_ISP_AWB1_GAIN_G, false),
rkisp_read(dev, ISP32_ISP_AWB1_GAIN_RB, false));
val = rkisp_read(dev, ISP3X_CMSK_CTRL0, false);
seq_printf(p, "%-10s %s(0x%x)\n", "CMSK", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_DPCC0_MODE, false);
seq_printf(p, "%-10s %s(0x%x)\n", "DPCC0", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_DPCC1_MODE, false);
seq_printf(p, "%-10s %s(0x%x)\n", "DPCC1", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_BLS_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "BLS", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_LSC_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "LSC", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_DEBAYER_CONTROL, false);
seq_printf(p, "%-10s %s(0x%x) bypass:%d\n", "DEBAYER", (val & (BIT(0) | BIT(29))) ? "ON" : "OFF",
val, !!(val & (BIT(1) | BIT(27))));
val = rkisp_read(dev, ISP3X_CCM_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "CCM", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_GAMMA_OUT_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "GAMMA_OUT", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_CPROC_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "CPROC", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_IMG_EFF_CTRL, false);
seq_printf(p, "%-10s %s(0x%x) (effect: %s)\n", "IE",
(val & 1) ? "ON" : "OFF", val, effect[!!val]);
val = rkisp_read(dev, ISP3X_DRC_CTRL0, false);
seq_printf(p, "%-10s %s(0x%x) bypass:%d lp_en:%d\n", "DRC", (val & 1) ? "ON" : "OFF",
val, !!(val & BIT(1)), !!(val & BIT(4)));
val = rkisp_read(dev, ISP3X_HDRMGE_CTRL, false);
seq_printf(p, "%-10s %s(0x%x) wrap:%d\n", "HDRMGE", (val & 1) ? "ON" : "OFF",
val, dev->hdr_wrap_line);
val = rkisp_read(dev, ISP33_BAY3D_CTRL0, false);
tmp = rkisp_read(dev, ISP33_BAY3D_CTRL2, false);
seq_printf(p, "%-10s %s(0x%x) bypass:%d sparse:%d lp_en(me_off:%d gic:%d bf:%d avg:%d) size(iir:%d ds:%d wgt:%d)\n",
"BAY3D", (val & 1) ? "ON" : "OFF", val,
!!(val & BIT(1)), !!(val & BIT(2)), !(val & BIT(8)),
!!(tmp & BIT(20)), !!(tmp & BIT(21)), !!(tmp & BIT(22)),
priv->buf_3dnr_iir.size, priv->buf_3dnr_ds.size, priv->buf_3dnr_wgt.size);
val = rkisp_read(dev, ISP3X_YNR_GLOBAL_CTRL, false);
seq_printf(p, "%-10s %s(0x%x) bypass(hi:%d mi:%d lo:%d) lp_en:%d\n", "YNR",
(val & 1) ? "ON" : "OFF", val,
!!(val & BIT(1)), !!(val & BIT(2)), !!(val & BIT(3)), !!(val & BIT(6)));
val = rkisp_read(dev, ISP3X_CNR_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "CNR", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_SHARP_EN, false);
seq_printf(p, "%-10s %s(0x%x) lp_en:%d\n", "SHARP",
(val & 1) ? "ON" : "OFF", val, !!(val & BIT(10)));
val = rkisp_read(dev, ISP33_ENH_CTRL, false);
seq_printf(p, "%-10s %s(0x%x) bypass:%d lp_en:%d\n", "ENH", (val & 1) ? "ON" : "OFF",
val, !!(val & BIT(1)), !!(val & BIT(2)));
val = rkisp_read(dev, ISP33_HIST_CTRL, false);
seq_printf(p, "%-10s %s(0x%x) bypass:%d\n", "HIST", (val & 1) ? "ON" : "OFF",
val, !!(val & BIT(1)));
val = rkisp_read(dev, ISP33_HSV_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "HSV", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_LDCH_STS, false);
seq_printf(p, "%-10s %s(0x%x)\n", "LDCH", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_ISP_CTRL0, false);
tmp = rkisp_read(dev, ISP3X_ISP_CC_COEFF_0, false);
seq_printf(p, "%-10s %s(0x%x), y_offs:0x%x c_offs:0x%x\n"
"\t coeff Y:0x%x 0x%x 0x%x CB:0x%x 0x%x 0x%x CR:0x%x 0x%x 0x%x\n",
"CSM", (val & full_range_flg) ? "FULL" : "LIMIT", val,
(tmp >> 24) & 0x3f,
(tmp >> 16) & 0xff ? (tmp >> 16) & 0xff : 128,
tmp & 0x1ff,
rkisp_read(dev, ISP3X_ISP_CC_COEFF_1, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_2, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_3, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_4, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_5, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_6, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_7, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_8, false));
val = rkisp_read(dev, ISP3X_GAIN_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "GAIN", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_RAWAWB_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RAWAWB", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_RAWAE_LITE_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RAWAE0", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_RAWAE_BIG1_BASE, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RAWAE3", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_RAWHIST_LITE_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RAWHIST0", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_RAWHIST_BIG1_BASE, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RAWHIST3", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP32_BLS_ISP_OB_PREDGAIN, false);
seq_printf(p, "%-10s %s(0x%x)\n", "OB", val ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_ISP_DEBUG1, true);
seq_printf(p, "%-10s space full status group(0x%x) isp2enc_cnt:%d\n"
"\t ibuf2:0x%x ibuf1:0x%x ibuf0:0x%x\n"
"\t outfifo:0x%x lafifo:0x%x\n",
"DEBUG1", val, val & 0xff,
val >> 28, (val >> 24) & 0xf, (val >> 20) & 0xf,
(val >> 12) & 0xf, (val >> 8) & 0xf);
val = rkisp_read(dev, ISP3X_ISP_DEBUG2, true);
seq_printf(p, "%-10s 0x%x\n"
"\t bay3d_fifo_full iir:%d cur:%d\n"
"\t module outform vertical counter:%d, out frame counter:%d\n"
"\t isp output line counter:%d\n",
"DEBUG2", val, !!(val & BIT(31)), !!(val & BIT(30)),
(val >> 16) & 0x3fff, (val >> 14) & 0x3, val & 0x3fff);
val = rkisp_read(dev, ISP3X_ISP_DEBUG3, true);
seq_printf(p, "%-10s isp pipeline group (0x%x)\n"
"\t mge(%d %d) rawnr(%d %d) bay3d(%d %d) tmo(%d %d)\n"
"\t gic(%d %d) dbr(%d %d) debayer(%d %d) dhaz(%d %d)\n"
"\t lut3d(%d %d) ldch(%d %d) ynr(%d %d) shp(%d %d)\n"
"\t cgc(%d %d) cac(%d %d) isp_out(%d %d) isp_in(%d %d)\n",
"DEBUG3", val,
!!(val & BIT(31)), !!(val & BIT(30)), !!(val & BIT(29)), !!(val & BIT(28)),
!!(val & BIT(27)), !!(val & BIT(26)), !!(val & BIT(25)), !!(val & BIT(24)),
!!(val & BIT(23)), !!(val & BIT(22)), !!(val & BIT(21)), !!(val & BIT(20)),
!!(val & BIT(19)), !!(val & BIT(18)), !!(val & BIT(17)), !!(val & BIT(16)),
!!(val & BIT(15)), !!(val & BIT(14)), !!(val & BIT(13)), !!(val & BIT(12)),
!!(val & BIT(11)), !!(val & BIT(10)), !!(val & BIT(9)), !!(val & BIT(8)),
!!(val & BIT(7)), !!(val & BIT(6)), !!(val & BIT(5)), !!(val & BIT(4)),
!!(val & BIT(3)), !!(val & BIT(2)), !!(val & BIT(1)), !!(val & BIT(0)));
val = rkisp_read(dev, ISP32_ISP_DEBUG4, true);
seq_printf(p, "%-10s isp pipeline group (0x%x)\n"
"\t expd(%d %d) ynr(%d %d)\n",
"DEBUG4", val,
!!(val & BIT(3)), !!(val & BIT(2)), !!(val & BIT(1)), !!(val & BIT(0)));
}
static int isp_show(struct seq_file *p, void *v)
{
struct rkisp_device *dev = p->private;
@@ -1106,6 +1258,10 @@ static int isp_show(struct seq_file *p, void *v)
if (IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39))
isp39_show(dev, p);
break;
case ISP_V33:
if (IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V33))
isp33_show(dev, p);
break;
default:
break;
}

3
drivers/media/platform/rockchip/isp/regs.c
View File

@@ -462,7 +462,7 @@ void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y,
struct rkisp_device *dev = stream->ispdev;
int i = 0;
if (dev->isp_ver == ISP_V39 ||
if (dev->isp_ver == ISP_V39 || dev->isp_ver == ISP_V33 ||
(dev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP)) {
set_bilinear_scale(stream, in_y, in_c, out_y, out_c, async);
return;
@@ -489,6 +489,7 @@ void rkisp_disable_rsz(struct rkisp_stream *stream, bool async)
{
rkisp_unite_write(stream->ispdev, stream->config->rsz.ctrl, 0, false);
if (stream->ispdev->isp_ver == ISP_V39 ||
stream->ispdev->isp_ver == ISP_V33 ||
(stream->ispdev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP))
return;
update_rsz_shadow(stream, async);

14
drivers/media/platform/rockchip/isp/regs_v2x.h
View File

@@ -2678,13 +2678,21 @@ static inline void raw_rd_ctrl(void __iomem *base, u32 val)
static inline void mi_raw_length(struct rkisp_stream *stream)
{
bool is_direct = true;
u32 bytesperline = stream->out_fmt.plane_fmt[0].bytesperline;
if (stream->config->mi.length == MI_RAW0_RD_LENGTH ||
stream->config->mi.length == MI_RAW1_RD_LENGTH ||
stream->config->mi.length == MI_RAW2_RD_LENGTH)
stream->config->mi.length == MI_RAW2_RD_LENGTH) {
is_direct = false;
rkisp_unite_write(stream->ispdev, stream->config->mi.length,
stream->out_fmt.plane_fmt[0].bytesperline, is_direct);
if (stream->ispdev->isp_ver == ISP_V33 &&
!IS_HDR_RDBK(stream->ispdev->rd_mode) &&
stream->config->mi.length == MI_RAW2_RD_LENGTH &&
stream->ispdev->unite_div == ISP_UNITE_DIV2) {
bytesperline = stream->out_fmt.width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
bytesperline = ALIGN(bytesperline * stream->out_isp_fmt.bpp[0] / 8, 256);
}
}
rkisp_unite_write(stream->ispdev, stream->config->mi.length, bytesperline, is_direct);
if (stream->ispdev->isp_ver == ISP_V21 || stream->ispdev->isp_ver == ISP_V30)
rkisp_unite_set_bits(stream->ispdev, MI_RD_CTRL2, 0, BIT(30), false);
}

314
drivers/media/platform/rockchip/isp/regs_v3x.h
View File

@@ -235,6 +235,9 @@
#define ISP39_HF_FACTOR6 (ISP3X_CCM_BASE + 0x00070)
#define ISP39_HF_FACTOR7 (ISP3X_CCM_BASE + 0x00074)
#define ISP39_HF_FACTOR8 (ISP3X_CCM_BASE + 0x00078)
#define ISP33_CCM_HF_THD (ISP3X_CCM_BASE + 0x00054)
#define ISP33_CCM_HF_FACTOR0 (ISP3X_CCM_BASE + 0x00058)
#define ISP33_CCM_HF_FACTOR8 (ISP3X_CCM_BASE + 0x00078)
#define ISP3X_CPROC_BASE 0x00000800
#define ISP3X_CPROC_CTRL (ISP3X_CPROC_BASE + 0x00000)
@@ -404,6 +407,40 @@
#define ISP32_BP_RESIZE_HC_OFFS_MI_SHD (ISP32_BP_RESIZE_BASE + 0x00074)
#define ISP32_BP_RESIZE_IN_CROP_OFFSET (ISP32_BP_RESIZE_BASE + 0x00078)
#define ISP33_BP_SCALE_BASE 0x00000E00
#define ISP33_BP_SCALE_CTRL (ISP33_BP_SCALE_BASE + 0x0000)
#define ISP33_BP_SCALE_UPDATE (ISP33_BP_SCALE_BASE + 0x0004)
#define ISP33_BP_SCALE_SRC_SIZE (ISP33_BP_SCALE_BASE + 0x0008)
#define ISP33_BP_SCALE_DST_SIZE (ISP33_BP_SCALE_BASE + 0x000c)
#define ISP33_BP_SCALE_HY_FAC (ISP33_BP_SCALE_BASE + 0x0010)
#define ISP33_BP_SCALE_HC_FAC (ISP33_BP_SCALE_BASE + 0x0014)
#define ISP33_BP_SCALE_VY_FAC (ISP33_BP_SCALE_BASE + 0x0018)
#define ISP33_BP_SCALE_VC_FAC (ISP33_BP_SCALE_BASE + 0x001c)
#define ISP33_BP_SCALE_HY_OFFS (ISP33_BP_SCALE_BASE + 0x0020)
#define ISP33_BP_SCALE_HC_OFFS (ISP33_BP_SCALE_BASE + 0x0024)
#define ISP33_BP_SCALE_VY_OFFS (ISP33_BP_SCALE_BASE + 0x0028)
#define ISP33_BP_SCALE_HY_SIZE (ISP33_BP_SCALE_BASE + 0x0040)
#define ISP33_BP_SCALE_HC_SIZE (ISP33_BP_SCALE_BASE + 0x0044)
#define ISP33_BP_SCALE_HY_OFFS_MI (ISP33_BP_SCALE_BASE + 0x0048)
#define ISP33_BP_SCALE_HC_OFFS_MI (ISP33_BP_SCALE_BASE + 0x004c)
#define ISP33_BP_SCALE_IN_CROP_OFFSET (ISP33_BP_SCALE_BASE + 0x0050)
#define ISP33_BP_SCALE_CTRL_SHD (ISP33_BP_SCALE_BASE + 0x0080)
#define ISP33_BP_SCALE_SRC_SIZE_SHD (ISP33_BP_SCALE_BASE + 0x0088)
#define ISP33_BP_SCALE_DST_SIZE_SHD (ISP33_BP_SCALE_BASE + 0x008c)
#define ISP33_BP_SCALE_HY_FAC_SHD (ISP33_BP_SCALE_BASE + 0x0090)
#define ISP33_BP_SCALE_HC_FAC_SHD (ISP33_BP_SCALE_BASE + 0x0094)
#define ISP33_BP_SCALE_VY_FAC_SHD (ISP33_BP_SCALE_BASE + 0x0098)
#define ISP33_BP_SCALE_VC_FAC_SHD (ISP33_BP_SCALE_BASE + 0x009c)
#define ISP33_BP_SCALE_HY_OFFS_SHD (ISP33_BP_SCALE_BASE + 0x00a0)
#define ISP33_BP_SCALE_HC_OFFS_SHD (ISP33_BP_SCALE_BASE + 0x00a4)
#define ISP33_BP_SCALE_VY_OFFS_SHD (ISP33_BP_SCALE_BASE + 0x00a8)
#define ISP33_BP_SCALE_VC_OFFS_SHD (ISP33_BP_SCALE_BASE + 0x00ac)
#define ISP33_BP_SCALE_HY_SIZE_SHD (ISP33_BP_SCALE_BASE + 0x00c0)
#define ISP33_BP_SCALE_HC_SIZE_SHD (ISP33_BP_SCALE_BASE + 0x00c4)
#define ISP33_BP_SCALE_HY_OFFS_MI_SHD (ISP33_BP_SCALE_BASE + 0x00c8)
#define ISP33_BP_SCALE_HC_OFFS_MI_SHD (ISP33_BP_SCALE_BASE + 0x00cc)
#define ISP33_BP_SCALE_IN_CROP_OFFSET_SHD (ISP33_BP_SCALE_BASE + 0x00d0)
#define ISP3X_SELF_RESIZE_BASE 0x00001000
#define ISP3X_SELF_RESIZE_CTRL (ISP3X_SELF_RESIZE_BASE + 0x00000)
#define ISP3X_SELF_RESIZE_SCALE_HY (ISP3X_SELF_RESIZE_BASE + 0x00004)
@@ -900,6 +937,31 @@
#define ISP32_CAC_EXPO_ADJ_B (ISP3X_CAC_BASE + 0x00088)
#define ISP32_CAC_EXPO_ADJ_R (ISP3X_CAC_BASE + 0x0008c)
#define ISP32_CAC_RO_CNT (ISP3X_CAC_BASE + 0x000fc)
#define ISP33_CAC_HIGH_DIRECT (ISP3X_CAC_BASE + 0x00008)
#define ISP33_CAC_OVER_EXPO0 (ISP3X_CAC_BASE + 0x0000c)
#define ISP33_CAC_OVER_EXPO1 (ISP3X_CAC_BASE + 0x00010)
#define ISP33_CAC_FLAT (ISP3X_CAC_BASE + 0x00014)
#define ISP33_CAC_GAUSS_COEFF (ISP3X_CAC_BASE + 0x00018)
#define ISP33_CAC_RATIO (ISP3X_CAC_BASE + 0x0001c)
#define ISP33_CAC_WGT_COLOR_B (ISP3X_CAC_BASE + 0x00020)
#define ISP33_CAC_WGT_COLOR_R (ISP3X_CAC_BASE + 0x00024)
#define ISP33_CAC_WGT_COLOR_SLOPE_B (ISP3X_CAC_BASE + 0x00028)
#define ISP33_CAC_WGT_COLOR_SLOPE_R (ISP3X_CAC_BASE + 0x0002c)
#define ISP33_CAC_WGT_COLOR_LUMA0 (ISP3X_CAC_BASE + 0x00030)
#define ISP33_CAC_WGT_COLOR_LUMA1 (ISP3X_CAC_BASE + 0x00034)
#define ISP33_CAC_WGT_OVER_EXPO0 (ISP3X_CAC_BASE + 0x00038)
#define ISP33_CAC_WGT_OVER_EXPO1 (ISP3X_CAC_BASE + 0x0003c)
#define ISP33_CAC_WGT_CONTRAST0 (ISP3X_CAC_BASE + 0x00040)
#define ISP33_CAC_WGT_CONTRAST1 (ISP3X_CAC_BASE + 0x00044)
#define ISP33_CAC_WGT_CONTRAST2 (ISP3X_CAC_BASE + 0x00048)
#define ISP33_CAC_WGT_DARK_AREA0 (ISP3X_CAC_BASE + 0x0004c)
#define ISP33_CAC_WGT_DARK_AREA1 (ISP3X_CAC_BASE + 0x00050)
#define ISP33_CAC_PSF_B0 (ISP3X_CAC_BASE + 0x00054)
#define ISP33_CAC_PSF_B2 (ISP3X_CAC_BASE + 0x0005c)
#define ISP33_CAC_PSF_R0 (ISP3X_CAC_BASE + 0x00060)
#define ISP33_CAC_PSF_R2 (ISP3X_CAC_BASE + 0x00068)
#define ISP33_CAC_RO_CNT (ISP3X_CAC_BASE + 0x000f8)
#define ISP33_CAC_DEBUG (ISP3X_CAC_BASE + 0x000fc)
#define ISP3X_YNR_BASE 0x00002700
#define ISP3X_YNR_GLOBAL_CTRL (ISP3X_YNR_BASE + 0x00000)
@@ -986,6 +1048,31 @@
#define ISP39_YNR_NLM_COE (ISP3X_YNR_BASE + 0x000f4)
#define ISP39_YNR_NLM_WEIGHT (ISP3X_YNR_BASE + 0x000f8)
#define ISP39_YNR_NLM_NR_WEIGHT (ISP3X_YNR_BASE + 0x000fc)
#define ISP33_YNR_GAIN_CTRL (ISP3X_YNR_BASE + 0x00010)
#define ISP33_YNR_GAIN_ADJ_0_2 (ISP3X_YNR_BASE + 0x00014)
#define ISP33_YNR_RNR_MAX_R (ISP3X_YNR_BASE + 0x00020)
#define ISP33_YNR_RNR_CENTER_COOR (ISP3X_YNR_BASE + 0x00024)
#define ISP33_YNR_RNR_STRENGTH03 (ISP3X_YNR_BASE + 0x00028)
#define ISP33_YNR_RNR_STRENGTH16 (ISP3X_YNR_BASE + 0x00038)
#define ISP33_YNR_SGM_DX_0_1 (ISP3X_YNR_BASE + 0x00040)
#define ISP33_YNR_SGM_DX_16 (ISP3X_YNR_BASE + 0x00060)
#define ISP33_YNR_SGM_Y_0_1 (ISP3X_YNR_BASE + 0x00064)
#define ISP33_YNR_SGM_Y_16 (ISP3X_YNR_BASE + 0x00084)
#define ISP33_YNR_HI_SIGMA_GAIN (ISP3X_YNR_BASE + 0x000a0)
#define ISP33_YNR_HI_GAUS_COE (ISP3X_YNR_BASE + 0x000a4)
#define ISP33_YNR_HI_WEIGHT (ISP3X_YNR_BASE + 0x000a8)
#define ISP33_YNR_HI_GAUS1_COE_0_2 (ISP3X_YNR_BASE + 0x000ac)
#define ISP33_YNR_HI_GAUS1_COE_3_5 (ISP3X_YNR_BASE + 0x000b0)
#define ISP33_YNR_HI_TEXT (ISP3X_YNR_BASE + 0x000b4)
#define ISP33_YNR_MI_GAUS_COE (ISP3X_YNR_BASE + 0x000c0)
#define ISP33_YNR_MI_STRG_DETAIL (ISP3X_YNR_BASE + 0x000c4)
#define ISP33_YNR_MI_WEIGHT (ISP3X_YNR_BASE + 0x000c8)
#define ISP33_YNR_LO_STRG_DETAIL (ISP3X_YNR_BASE + 0x000e0)
#define ISP33_YNR_LO_LIMIT_SCALE (ISP3X_YNR_BASE + 0x000e4)
#define ISP33_YNR_LO_WEIGHT (ISP3X_YNR_BASE + 0x000e8)
#define ISP33_YNR_LO_TEXT_THRED (ISP3X_YNR_BASE + 0x000ec)
#define ISP33_YNR_FUSION_WEIT_ADJ_0_3 (ISP3X_YNR_BASE + 0x000f0)
#define ISP33_YNR_FUSION_WEIT_ADJ_8 (ISP3X_YNR_BASE + 0x000f8)
#define ISP3X_CNR_BASE 0x00002800
#define ISP3X_CNR_CTRL (ISP3X_CNR_BASE + 0x00000)
@@ -1101,6 +1188,141 @@
#define ISP39_SHARP_DETAIL_STRG_LUT6 (ISP3X_SHARP_BASE + 0x000dc)
#define ISP39_SHARP_DETAIL_STRG_LUT7 (ISP3X_SHARP_BASE + 0x000e0)
#define ISP39_SHARP_DETAIL_STRG_LUT8 (ISP3X_SHARP_BASE + 0x000e4)
#define ISP33_SHARP_TEXTURE0 (ISP3X_SHARP_BASE + 0x00004)
#define ISP33_SHARP_TEXTURE1 (ISP3X_SHARP_BASE + 0x00008)
#define ISP33_SHARP_TEXTURE2 (ISP3X_SHARP_BASE + 0x0000c)
#define ISP33_SHARP_TEXTURE3 (ISP3X_SHARP_BASE + 0x00010)
#define ISP33_SHARP_TEXTURE4 (ISP3X_SHARP_BASE + 0x00014)
#define ISP33_SHARP_HPF_KERNEL0 (ISP3X_SHARP_BASE + 0x00018)
#define ISP33_SHARP_HPF_KERNEL1 (ISP3X_SHARP_BASE + 0x0001c)
#define ISP33_SHARP_TEXFLT_KERNEL (ISP3X_SHARP_BASE + 0x00020)
#define ISP33_SHARP_DETAIL0 (ISP3X_SHARP_BASE + 0x00024)
#define ISP33_SHARP_DETAIL1 (ISP3X_SHARP_BASE + 0x00028)
#define ISP33_SHARP_LUMA_DX (ISP3X_SHARP_BASE + 0x0002c)
#define ISP33_SHARP_PBF_VSIGMA0 (ISP3X_SHARP_BASE + 0x00030)
#define ISP33_SHARP_PBF_KERNEL (ISP3X_SHARP_BASE + 0x00040)
#define ISP33_SHARP_DETAIL_KERNEL0 (ISP3X_SHARP_BASE + 0x00044)
#define ISP33_SHARP_DETAIL_KERNEL1 (ISP3X_SHARP_BASE + 0x00048)
#define ISP33_SHARP_DETAIL_KERNEL2 (ISP3X_SHARP_BASE + 0x0004c)
#define ISP33_SHARP_GAIN (ISP3X_SHARP_BASE + 0x00050)
#define ISP33_SHARP_GAIN_ADJ0 (ISP3X_SHARP_BASE + 0x00054)
#define ISP33_SHARP_GAIN_ADJ1 (ISP3X_SHARP_BASE + 0x00058)
#define ISP33_SHARP_GAIN_ADJ2 (ISP3X_SHARP_BASE + 0x0005c)
#define ISP33_SHARP_GAIN_ADJ3 (ISP3X_SHARP_BASE + 0x00060)
#define ISP33_SHARP_GAIN_ADJ4 (ISP3X_SHARP_BASE + 0x00064)
#define ISP33_SHARP_EDGE0 (ISP3X_SHARP_BASE + 0x00068)
#define ISP33_SHARP_EDGE1 (ISP3X_SHARP_BASE + 0x0006c)
#define ISP33_SHARP_EDGE_KERNEL0 (ISP3X_SHARP_BASE + 0x00070)
#define ISP33_SHARP_EDGE_KERNEL2 (ISP3X_SHARP_BASE + 0x00078)
#define ISP33_SHARP_EDGE_WGT_VAL0 (ISP3X_SHARP_BASE + 0x0007c)
#define ISP33_SHARP_EDGE_WGT_VAL5 (ISP3X_SHARP_BASE + 0x00090)
#define ISP33_SHARP_LUMA_ADJ_STRG0 (ISP3X_SHARP_BASE + 0x00094)
#define ISP33_SHARP_CENTER (ISP3X_SHARP_BASE + 0x0009c)
#define ISP33_SHARP_OUT_LIMIT (ISP3X_SHARP_BASE + 0x000a0)
#define ISP33_SHARP_TEX_X_INV_FIX0 (ISP3X_SHARP_BASE + 0x000a4)
#define ISP33_SHARP_TEX_X_INV_FIX1 (ISP3X_SHARP_BASE + 0x000a8)
#define ISP33_SHARP_TEX_X_INV_FIX2 (ISP3X_SHARP_BASE + 0x000ac)
#define ISP33_SHARP_LOCAL_STRG0 (ISP3X_SHARP_BASE + 0x000b0)
#define ISP33_SHARP_LOCAL_STRG1 (ISP3X_SHARP_BASE + 0x000b4)
#define ISP33_SHARP_LOCAL_STRG2 (ISP3X_SHARP_BASE + 0x000b8)
#define ISP33_SHARP_DETAIL_SCALE_TAB0 (ISP3X_SHARP_BASE + 0x000c0)
#define ISP33_SHARP_DETAIL_SCALE_TAB1 (ISP3X_SHARP_BASE + 0x000c4)
#define ISP33_SHARP_DETAIL_SCALE_TAB2 (ISP3X_SHARP_BASE + 0x000c8)
#define ISP33_SHARP_DETAIL_SCALE_TAB3 (ISP3X_SHARP_BASE + 0x000cc)
#define ISP33_SHARP_DETAIL_SCALE_TAB4 (ISP3X_SHARP_BASE + 0x000d0)
#define ISP33_SHARP_DETAIL_SCALE_TAB5 (ISP3X_SHARP_BASE + 0x000d4)
#define ISP33_SHARP_DETAIL_TEX_CLIP0 (ISP3X_SHARP_BASE + 0x000d8)
#define ISP33_SHARP_DETAIL_TEX_CLIP1 (ISP3X_SHARP_BASE + 0x000dc)
#define ISP33_SHARP_DETAIL_TEX_CLIP2 (ISP3X_SHARP_BASE + 0x000e0)
#define ISP33_SHARP_DETAIL_TEX_CLIP3 (ISP3X_SHARP_BASE + 0x000e4)
#define ISP33_SHARP_DETAIL_TEX_CLIP4 (ISP3X_SHARP_BASE + 0x000e8)
#define ISP33_SHARP_DETAIL_TEX_CLIP5 (ISP3X_SHARP_BASE + 0x000ec)
#define ISP33_SHARP_GRAIN_TEX_CLIP0 (ISP3X_SHARP_BASE + 0x000f0)
#define ISP33_SHARP_GRAIN_TEX_CLIP1 (ISP3X_SHARP_BASE + 0x000f4)
#define ISP33_SHARP_GRAIN_TEX_CLIP2 (ISP3X_SHARP_BASE + 0x000f8)
#define ISP33_SHARP_GRAIN_TEX_CLIP3 (ISP3X_SHARP_BASE + 0x000fc)
#define ISP33_SHARP_GRAIN_TEX_CLIP4 (ISP3X_SHARP_BASE + 0x00100)
#define ISP33_SHARP_GRAIN_TEX_CLIP5 (ISP3X_SHARP_BASE + 0x00104)
#define ISP33_SHARP_DETAIL_LUMA_CLIP0 (ISP3X_SHARP_BASE + 0x00108)
#define ISP33_SHARP_DETAIL_LUMA_CLIP1 (ISP3X_SHARP_BASE + 0x0010c)
#define ISP33_SHARP_DETAIL_LUMA_CLIP2 (ISP3X_SHARP_BASE + 0x00110)
#define ISP33_SHARP_DETAIL_LUMA_CLIP3 (ISP3X_SHARP_BASE + 0x00114)
#define ISP33_SHARP_DETAIL_LUMA_CLIP4 (ISP3X_SHARP_BASE + 0x00118)
#define ISP33_SHARP_DETAIL_LUMA_CLIP5 (ISP3X_SHARP_BASE + 0x0011c)
#define ISP33_SHARP_GRAIN_STRG (ISP3X_SHARP_BASE + 0x00120)
#define ISP33_SHARP_HUE_ADJ_TAB0 (ISP3X_SHARP_BASE + 0x00124)
#define ISP33_SHARP_DISATANCE_ADJ0 (ISP3X_SHARP_BASE + 0x00130)
#define ISP33_SHARP_DISATANCE_ADJ2 (ISP3X_SHARP_BASE + 0x00138)
#define ISP33_SHARP_NOISE_SIGMA0 (ISP3X_SHARP_BASE + 0x00148)
#define ISP33_SHARP_NOISE_SIGMA4 (ISP3X_SHARP_BASE + 0x00158)
#define ISP33_SHARP_LOSSTEXINHINR_STRG (ISP3X_SHARP_BASE + 0x0016c)
#define ISP33_SHARP_NOISE_CURVE0 (ISP3X_SHARP_BASE + 0x00170)
#define ISP33_SHARP_NOISE_CURVE8 (ISP3X_SHARP_BASE + 0x00190)
#define ISP33_SHARP_NOISE_CLIP (ISP3X_SHARP_BASE + 0x00194)
#define ISP33_BAY3D_BASE 0x00002B00
#define ISP33_BAY3D_CTRL0 (ISP33_BAY3D_BASE + 0x00000)
#define ISP33_BAY3D_CTRL1 (ISP33_BAY3D_BASE + 0x00004)
#define ISP33_BAY3D_CTRL2 (ISP33_BAY3D_BASE + 0x00008)
#define ISP33_BAY3D_CTRL3 (ISP33_BAY3D_BASE + 0x0000c)
#define ISP33_BAY3D_TRANS0 (ISP33_BAY3D_BASE + 0x00010)
#define ISP33_BAY3D_TRANS1 (ISP33_BAY3D_BASE + 0x00014)
#define ISP33_BAY3D_CURHI_SIGSCL (ISP33_BAY3D_BASE + 0x00058)
#define ISP33_BAY3D_CURHI_SIGOF (ISP33_BAY3D_BASE + 0x00068)
#define ISP33_BAY3D_CURHISPW0 (ISP33_BAY3D_BASE + 0x00070)
#define ISP33_BAY3D_CURHISPW1 (ISP33_BAY3D_BASE + 0x00074)
#define ISP33_BAY3D_IIRSX0 (ISP33_BAY3D_BASE + 0x00084)
#define ISP33_BAY3D_IIRSY0 (ISP33_BAY3D_BASE + 0x000a4)
#define ISP33_BAY3D_PREHI_SIGSCL (ISP33_BAY3D_BASE + 0x000c4)
#define ISP33_BAY3D_PREHI_WSCL (ISP33_BAY3D_BASE + 0x000c8)
#define ISP33_BAY3D_PREHIWMM (ISP33_BAY3D_BASE + 0x000cc)
#define ISP33_BAY3D_PREHISIGOF (ISP33_BAY3D_BASE + 0x000d4)
#define ISP33_BAY3D_PREHISIGSCL (ISP33_BAY3D_BASE + 0x000d8)
#define ISP33_BAY3D_PREHISPW0 (ISP33_BAY3D_BASE + 0x000dc)
#define ISP33_BAY3D_PREHISPW1 (ISP33_BAY3D_BASE + 0x000e0)
#define ISP33_BAY3D_PRELOSIGCSL (ISP33_BAY3D_BASE + 0x000e4)
#define ISP33_BAY3D_PRELOSIGOF (ISP33_BAY3D_BASE + 0x000e8)
#define ISP33_BAY3D_PREHI_NRCT (ISP33_BAY3D_BASE + 0x000f0)
#define ISP33_BAY3D_TNRSX0 (ISP33_BAY3D_BASE + 0x00100)
#define ISP33_BAY3D_TNRSY0 (ISP33_BAY3D_BASE + 0x00128)
#define ISP33_BAY3D_HIWD0 (ISP33_BAY3D_BASE + 0x00150)
#define ISP33_BAY3D_LOWD0 (ISP33_BAY3D_BASE + 0x0015c)
#define ISP33_BAY3D_GF3 (ISP33_BAY3D_BASE + 0x00168)
#define ISP33_BAY3D_GF4 (ISP33_BAY3D_BASE + 0x0016c)
#define ISP33_BAY3D_VIIR (ISP33_BAY3D_BASE + 0x00170)
#define ISP33_BAY3D_LFSCL (ISP33_BAY3D_BASE + 0x00174)
#define ISP33_BAY3D_LFSCLTH (ISP33_BAY3D_BASE + 0x00178)
#define ISP33_BAY3D_DSWGTSCL (ISP33_BAY3D_BASE + 0x0017c)
#define ISP33_BAY3D_WGTLASTSCL (ISP33_BAY3D_BASE + 0x00180)
#define ISP33_BAY3D_WGTSCL0 (ISP33_BAY3D_BASE + 0x00184)
#define ISP33_BAY3D_WGTSCL1 (ISP33_BAY3D_BASE + 0x00188)
#define ISP33_BAY3D_WGTSCL2 (ISP33_BAY3D_BASE + 0x0018c)
#define ISP33_BAY3D_WGTOFF (ISP33_BAY3D_BASE + 0x00190)
#define ISP33_BAY3D_WGT1OFF (ISP33_BAY3D_BASE + 0x00194)
#define ISP33_BAY3D_SIGORG (ISP33_BAY3D_BASE + 0x00198)
#define ISP33_BAY3D_WGTLO_L (ISP33_BAY3D_BASE + 0x0019c)
#define ISP33_BAY3D_WGTLO_H (ISP33_BAY3D_BASE + 0x001a0)
#define ISP33_BAY3D_STH_SCL (ISP33_BAY3D_BASE + 0x001a4)
#define ISP33_BAY3D_STH_LIMIT (ISP33_BAY3D_BASE + 0x001a8)
#define ISP33_BAY3D_HIKEEP (ISP33_BAY3D_BASE + 0x001ac)
#define ISP33_BAY3D_PIXMAX (ISP33_BAY3D_BASE + 0x001b0)
#define ISP33_BAY3D_SIGNUMTH (ISP33_BAY3D_BASE + 0x001b4)
#define ISP33_BAY3D_MONR (ISP33_BAY3D_BASE + 0x001b8)
#define ISP33_BAY3D_SIGSCL (ISP33_BAY3D_BASE + 0x001bc)
#define ISP33_BAY3D_DSOFF (ISP33_BAY3D_BASE + 0x001d0)
#define ISP33_BAY3D_DSSCL (ISP33_BAY3D_BASE + 0x001d4)
#define ISP33_BAY3D_ME0 (ISP33_BAY3D_BASE + 0x001d8)
#define ISP33_BAY3D_ME1 (ISP33_BAY3D_BASE + 0x001dc)
#define ISP33_BAY3D_ME2 (ISP33_BAY3D_BASE + 0x001e0)
#define ISP33_BAY3D_WGTMAX (ISP33_BAY3D_BASE + 0x001e4)
#define ISP33_BAY3D_WGT1MAX (ISP33_BAY3D_BASE + 0x001e8)
#define ISP33_BAY3D_WGTM0 (ISP33_BAY3D_BASE + 0x001ec)
#define ISP33_BAY3D_PRELOWGT (ISP33_BAY3D_BASE + 0x0020c)
#define ISP33_BAY3D_MIDBIG0 (ISP33_BAY3D_BASE + 0x00280)
#define ISP33_BAY3D_MIDBIG1 (ISP33_BAY3D_BASE + 0x00284)
#define ISP33_BAY3D_MIDBIG2 (ISP33_BAY3D_BASE + 0x00288)
#define ISP33_BAY3D_TNRSUM (ISP33_BAY3D_BASE + 0x002d4)
#define ISP33_BAY3D_TNRYO0 (ISP33_BAY3D_BASE + 0x002d8)
#define ISP3X_BAY3D_BASE 0x00002C00
#define ISP3X_BAY3D_CTRL (ISP3X_BAY3D_BASE + 0x00000)
@@ -1322,6 +1544,25 @@
#define ISP3X_GIC_SIGMA_VALUE5 (ISP3X_GIC_BASE + 0x00034)
#define ISP3X_GIC_SIGMA_VALUE6 (ISP3X_GIC_BASE + 0x00038)
#define ISP3X_GIC_SIGMA_VALUE7 (ISP3X_GIC_BASE + 0x0003c)
#define ISP33_GIC_MEDFLT_PARA (ISP3X_GIC_BASE + 0x00004)
#define ISP33_GIC_MEDFLTUV_PARA (ISP3X_GIC_BASE + 0x00008)
#define ISP33_GIC_NOISE_SCALE (ISP3X_GIC_BASE + 0x0000c)
#define ISP33_GIC_BILAT_PARA1 (ISP3X_GIC_BASE + 0x00010)
#define ISP33_GIC_BILAT_PARA2 (ISP3X_GIC_BASE + 0x00014)
#define ISP33_GIC_DISWGT_COEFF (ISP3X_GIC_BASE + 0x00018)
#define ISP33_GIC_SIGMA_Y0 (ISP3X_GIC_BASE + 0x00020)
#define ISP33_GIC_SIGMA_Y8 (ISP3X_GIC_BASE + 0x00040)
#define ISP33_GIC_LUMA_DX (ISP3X_GIC_BASE + 0x00044)
#define ISP33_GIC_THRED_Y0 (ISP3X_GIC_BASE + 0x00050)
#define ISP33_GIC_MIN_THRED_Y0 (ISP3X_GIC_BASE + 0x00060)
#define ISP33_GIC_THRED_SCALE (ISP3X_GIC_BASE + 0x00070)
#define ISP33_GIC_LOFLTGR_COEFF (ISP3X_GIC_BASE + 0x00074)
#define ISP33_GIC_LOFLTGB_COEFF (ISP3X_GIC_BASE + 0x00078)
#define ISP33_GIC_SUM_LOFLT_INV (ISP3X_GIC_BASE + 0x0007c)
#define ISP33_GIC_LOFLTTHRED_COEFF (ISP3X_GIC_BASE + 0x00080)
#define ISP33_GIC_GAIN (ISP3X_GIC_BASE + 0x00090)
#define ISP33_GIC_GAIN_SLOPE (ISP3X_GIC_BASE + 0x00094)
#define ISP33_GIC_GAIN_THRED (ISP3X_GIC_BASE + 0x00098)
#define ISP3X_BLS_BASE 0x00003000
#define ISP3X_BLS_CTRL (ISP3X_BLS_BASE + 0x00000)
@@ -1756,6 +1997,24 @@
#define ISP32_BAYNR_GAINX1213 (ISP3X_BAYNR_BASE + 0x00090)
#define ISP32_BAYNR_GAINX1415 (ISP3X_BAYNR_BASE + 0x00094)
#define ISP33_ENH_BASE 0x00003A00
#define ISP33_ENH_CTRL (ISP33_ENH_BASE + 0x00000)
#define ISP33_ENH_IIR_FLT (ISP33_ENH_BASE + 0x00004)
#define ISP33_ENH_BILAT_FLT3X3 (ISP33_ENH_BASE + 0x00008)
#define ISP33_ENH_BILAT_FLT5X5 (ISP33_ENH_BASE + 0x0000c)
#define ISP33_ENH_GLOBAL_STRG (ISP33_ENH_BASE + 0x00010)
#define ISP33_ENH_LUMA_LUT0 (ISP33_ENH_BASE + 0x00014)
#define ISP33_ENH_LUMA_LUT8 (ISP33_ENH_BASE + 0x00034)
#define ISP33_ENH_DETAIL_IDX0 (ISP33_ENH_BASE + 0x00038)
#define ISP33_ENH_DETAIL_IDX2 (ISP33_ENH_BASE + 0x00040)
#define ISP33_ENH_DETAIL_POWER (ISP33_ENH_BASE + 0x00044)
#define ISP33_ENH_DETAIL_VALUE0 (ISP33_ENH_BASE + 0x00048)
#define ISP33_ENH_PRE_FRAME (ISP33_ENH_BASE + 0x0007c)
#define ISP33_ENH_IIR0 (ISP33_ENH_BASE + 0x00080)
#define ISP33_ENH_IIR9 (ISP33_ENH_BASE + 0x000a4)
#define ISP33_ENH_IIR_RW (ISP33_ENH_BASE + 0x000a8)
#define ISP33_ENH_ERR_FLAG (ISP33_ENH_BASE + 0x000fc)
#define ISP3X_LDCH_BASE 0x00003B00
#define ISP3X_LDCH_STS (ISP3X_LDCH_BASE + 0x00000)
#define ISP32_LDCH_BIC_TABLE0 (ISP3X_LDCH_BASE + 0x00004)
@@ -1934,10 +2193,34 @@
#define ISP39_DHAZ_ADP_RD1 (ISP3X_DHAZ_BASE + 0x00188)
#define ISP39_DHAZ_LINE_CNT (ISP3X_DHAZ_BASE + 0x0018c)
#define ISP33_HIST_BASE 0x00003C00
#define ISP33_HIST_CTRL (ISP33_HIST_BASE + 0x00000)
#define ISP33_HIST_HF_STAT (ISP33_HIST_BASE + 0x00004)
#define ISP33_HIST_BLOCK_SIZE (ISP33_HIST_BASE + 0x00008)
#define ISP33_HIST_THUMB_SIZE (ISP33_HIST_BASE + 0x0000c)
#define ISP33_HIST_MAP0 (ISP33_HIST_BASE + 0x00010)
#define ISP33_HIST_MAP1 (ISP33_HIST_BASE + 0x00014)
#define ISP33_HIST_IIR (ISP33_HIST_BASE + 0x00018)
#define ISP33_HIST_POS_ALPHA0 (ISP33_HIST_BASE + 0x0001c)
#define ISP33_HIST_POS_ALPHA4 (ISP33_HIST_BASE + 0x0002c)
#define ISP33_HIST_NEG_ALPHA0 (ISP33_HIST_BASE + 0x00030)
#define ISP33_HIST_NEG_ALPHA4 (ISP33_HIST_BASE + 0x00040)
#define ISP33_HIST_IIR0 (ISP33_HIST_BASE + 0x00080)
#define ISP33_HIST_RW (ISP33_HIST_BASE + 0x000a0)
#define ISP33_HIST_STAB (ISP33_HIST_BASE + 0x000a4)
#define ISP33_HIST_UV_SCL (ISP33_HIST_BASE + 0x000a8)
#define ISP33_HIST_ERR_FLAG (ISP33_HIST_BASE + 0x000fc)
#define ISP3X_3DLUT_BASE 0x00003E00
#define ISP3X_3DLUT_CTRL (ISP3X_3DLUT_BASE + 0x00000)
#define ISP3X_3DLUT_UPDATE (ISP3X_3DLUT_BASE + 0x00004)
#define ISP33_HSV_BASE 0x00003E00
#define ISP33_HSV_CTRL (ISP33_HSV_BASE + 0x00000)
#define ISP33_HSV_UPDATE (ISP33_HSV_BASE + 0x00004)
#define ISP33_HSV_1DLUT (ISP33_HSV_BASE + 0x00008)
#define ISP33_HSV_2DLUT (ISP33_HSV_BASE + 0x0000c)
#define ISP3X_GAIN_BASE 0x00003F00
#define ISP3X_GAIN_CTRL (ISP3X_GAIN_BASE + 0x00000)
#define ISP3X_GAIN_G0 (ISP3X_GAIN_BASE + 0x00004)
@@ -2376,6 +2659,12 @@
#define ISP32L_RAWAWB_WIN_WEIGHT_2 (ISP3X_RAWAWB_BASE + 0x0668)
#define ISP32L_RAWAWB_WIN_WEIGHT_3 (ISP3X_RAWAWB_BASE + 0x066c)
#define ISP32L_RAWAWB_WIN_WEIGHT_4 (ISP3X_RAWAWB_BASE + 0x0670)
#define ISP33_RAWAWB_CCM_COEFF0_R (ISP3X_RAWAWB_BASE + 0x01c0)
#define ISP33_RAWAWB_CCM_COEFF1_R (ISP3X_RAWAWB_BASE + 0x01c4)
#define ISP33_RAWAWB_CCM_COEFF0_G (ISP3X_RAWAWB_BASE + 0x01c8)
#define ISP33_RAWAWB_CCM_COEFF1_G (ISP3X_RAWAWB_BASE + 0x01cc)
#define ISP33_RAWAWB_CCM_COEFF0_B (ISP3X_RAWAWB_BASE + 0x01d0)
#define ISP33_RAWAWB_CCM_COEFF1_B (ISP3X_RAWAWB_BASE + 0x01d4)
/* VI_ISP_PATH */
#define ISP3X_RAWAE3_SEL(x) (((x) & 3) << 16)
@@ -2396,7 +2685,9 @@
/* SWS_CFG */
#define ISP32L_ISP2ENC_CNT_MUX BIT(0)
#define ISP33_PP_ENC_PIPE_EN BIT(1)
#define ISP3X_SW_ACK_FRM_PRO_DIS BIT(3)
#define ISP33_SW_ISP2ENC_PATH_EN BIT(5)
#define ISP3X_3A_DDR_WRITE_EN BIT(24)
#define ISP3X_SW_MIPI2ISP_FIFO_DIS BIT(25)
#define ISP3X_SW_3D_DBR_START_MODE BIT(26)
@@ -2413,7 +2704,7 @@
#define ISP3X_SW_CMSK_FORCE_UPD BIT(31)
#define ISP3X_SW_CMSK_ORDER_MODE BIT(1)
#define ISP3X_SW_CMSK_ORDER_MODE BIT(6)
#define ISP3X_SW_CMSK_YUV(x, y, z) (((x) & 0xff) | ((y) & 0xff) << 8 | ((z) & 0xff) << 16)
@@ -2433,6 +2724,10 @@
#define ISP3X_BIGMODE_FORCE_EN BIT(28)
#define ISP3X_BIGMODE_MANUAL BIT(29)
#define ISP33_GIC_FST_FRAME BIT(22)
#define ISP33_ENH_FST_FRAME BIT(24)
#define ISP33_YHIST_FST_FRAME BIT(25)
/* ISP ACQ_H_OFFS */
#define ISP3X_SENSOR_MODE(x) (((x) & 3) << 30)
#define ISP3X_SENSOR_INDEX(x) (((x) & 3) << 28)
@@ -2492,6 +2787,8 @@
#define ISP3X_ISP_OUT_LINE(a) ((a) & 0x3fff)
#define ISP33_ISP2ENC_FRM_CNT(a) ((a) & 0xff)
#define ISP32_YNR_LUMA_RDBK_ST BIT(0)
#define ISP32_YNR_LUMA_RDBK_OFFS(a) (((a) & 0x3fff) << 16)
#define ISP32_YNR_LUMA_RDBK_RDY BIT(31)
@@ -2599,8 +2896,17 @@
#define ISP3X_DBR_ST BIT(31)
/* MI_RD_CTRL2 */
#define ISP3X_RAWX_RD_BURST_MASK GENMASK(23, 22)
#define ISP3X_RAWX_WR_BURST_MASK GENMASK(21, 20)
#define ISP3X_RAWX_RD_GROP_MASK GENMASK(19, 18)
#define ISP3X_RAWX_WR_GROP_MASK GENMASK(17, 16)
#define ISP39_AIISP_ST BIT(8)
#define ISP39_AIISP_EN BIT(9)
#define ISP3X_RAWX_WR_GROP_MODE(x) (((x) & 0x3) << 16)
#define ISP3X_RAWX_RD_GROP_MODE(x) (((x) & 0x3) << 18)
#define ISP3X_RAWX_WR_BURST_LEN(x) (((x) & 0x3) << 20)
#define ISP3X_RAWX_RD_BURST_LEN(x) (((x) & 0x3) << 22)
#define ISP3X_MI_NEW_WR_BURST_DIS BIT(31)
/* WR_OUTPUT_FORMAT */
#define ISP32_MI_OUTPUT_MASK GENMASK(10, 8)
@@ -2763,6 +3069,12 @@
#define ISP39_DHAZ_IIR_WR_ID(x) (((x) & 0xff) << 16)
#define ISP39_DHAZ_IIR_WR_CLEAR BIT(24)
#define ISP33_IIR_RD_ID(x) ((x) & 0x3f)
#define ISP33_IIR_RD_P BIT(8)
#define ISP33_IIR_RDATA_VAL BIT(9)
#define ISP33_IIR_WR_ID(x) (((x) & 0x3f) << 16)
#define ISP33_IIR_WR_CLEAR BIT(24)
/* HDRTMO */
/* HDRDRC */

554
drivers/media/platform/rockchip/isp/rkisp.c
View File

@@ -189,6 +189,7 @@ int rkisp_align_sensor_resolution(struct rkisp_device *dev,
u32 src_w = dev->isp_sdev.in_frm.width;
u32 src_h = dev->isp_sdev.in_frm.height;
u32 dest_w, dest_h, w, h, max_size, max_h, max_w;
u32 w_align = 16, h_align = 8;
int ret = 0;
if (!crop)
@@ -232,6 +233,12 @@ int rkisp_align_sensor_resolution(struct rkisp_device *dev,
max_h = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V39_UNITE : CIF_ISP_INPUT_H_MAX_V39;
break;
case ISP_V33:
max_w = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V33_UNITE : CIF_ISP_INPUT_W_MAX_V33;
max_h = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V33_UNITE : CIF_ISP_INPUT_H_MAX_V33;
break;
default:
max_w = CIF_ISP_INPUT_W_MAX;
max_h = CIF_ISP_INPUT_H_MAX;
@@ -241,6 +248,11 @@ int rkisp_align_sensor_resolution(struct rkisp_device *dev,
max_h = max_size / w;
h = clamp_t(u32, src_h, CIF_ISP_INPUT_H_MIN, max_h);
if (dev->isp_ver >= ISP_V33) {
w_align = 4;
h_align = 4;
}
if (dev->active_sensor)
sensor = dev->active_sensor->sd;
if (sensor) {
@@ -288,13 +300,13 @@ int rkisp_align_sensor_resolution(struct rkisp_device *dev,
crop->height = clamp_t(u32, crop->height,
CIF_ISP_INPUT_H_MIN, h - crop->top);
if ((code & RKISP_MEDIA_BUS_FMT_MASK) == RKISP_MEDIA_BUS_FMT_BAYER &&
(ALIGN_DOWN(crop->width, 16) != crop->width ||
ALIGN_DOWN(crop->height, 8) != crop->height))
(ALIGN_DOWN(crop->width, w_align) != crop->width ||
ALIGN_DOWN(crop->height, h_align) != crop->height))
v4l2_warn(&dev->v4l2_dev,
"Note: bayer raw need width 16 align, height 8 align!\n"
"Note: bayer raw need width %d align, height %d align!\n"
"suggest (%d,%d)/%dx%d, specical requirements, Ignore!\n",
ALIGN_DOWN(crop->left, 4), crop->top,
ALIGN_DOWN(crop->width, 16), ALIGN_DOWN(crop->height, 8));
w_align, h_align, ALIGN_DOWN(crop->left, 4), crop->top,
ALIGN_DOWN(crop->width, w_align), ALIGN_DOWN(crop->height, h_align));
return 0;
}
@@ -312,8 +324,8 @@ int rkisp_align_sensor_resolution(struct rkisp_device *dev,
* height 8 align
* width and height no exceeding the max limit
*/
dest_w = ALIGN_DOWN(w, 16);
dest_h = ALIGN_DOWN(h, 8);
dest_w = ALIGN_DOWN(w, w_align);
dest_h = ALIGN_DOWN(h, h_align);
/* try to center of crop
*4 align to no change bayer raw format
@@ -538,7 +550,7 @@ static void rkisp_dvfs(struct rkisp_device *dev)
if (hw->unite == ISP_UNITE_TWO)
rkisp_set_clk_rate(hw->clks[5], hw->clk_rate_tbl[i].clk_rate * 1000000UL);
/* aclk equal to core clk */
if (dev->isp_ver == ISP_V32)
if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V33)
rkisp_set_clk_rate(hw->clks[1], hw->clk_rate_tbl[i].clk_rate * 1000000UL);
dev_info(hw->dev, "set isp clk = %luHz\n", clk_get_rate(hw->clks[0]));
}
@@ -583,6 +595,128 @@ static void rkisp_multi_overflow_hdl(struct rkisp_device *dev, bool on)
rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true);
}
static void rkisp_update_list_reg(struct rkisp_device *dev)
{
struct rkisp_hw_dev *hw = dev->hw_dev;
u32 val = 0, index = 0;
/* multi sensor need to reset isp resize mode if scale up */
if (rkisp_read(dev, ISP3X_MAIN_RESIZE_CTRL, true) & 0xf0)
val |= BIT(3);
if (dev->isp_ver != ISP_V32_L &&
rkisp_read(dev, ISP3X_SELF_RESIZE_CTRL, true) & 0xf0)
val |= BIT(4);
if (rkisp_read(dev, ISP32_BP_RESIZE_CTRL, true) & 0xf0)
val |= BIT(12);
if (val) {
writel(val, hw->base_addr + CIF_IRCL);
writel(0, hw->base_addr + CIF_IRCL);
}
/* sensor mode & index */
if (dev->isp_ver >= ISP_V21) {
val = rkisp_read_reg_cache(dev, ISP_ACQ_H_OFFS);
if (hw->unite == ISP_UNITE_ONE &&
dev->isp_ver == ISP_V33 && !dev->is_frm_rd &&
dev->unite_index == ISP_UNITE_RIGHT)
index = 1;
else
index = dev->multi_index;
val |= ISP21_SENSOR_INDEX(index);
if (dev->isp_ver >= ISP_V32_L)
val |= ISP32L_SENSOR_MODE(dev->multi_mode);
else
val |= ISP21_SENSOR_MODE(dev->multi_mode);
writel(val, hw->base_addr + ISP_ACQ_H_OFFS);
if (hw->unite == ISP_UNITE_TWO)
writel(val, hw->base_next_addr + ISP_ACQ_H_OFFS);
}
rkisp_update_regs(dev, CTRL_VI_ISP_PATH, SUPER_IMP_COLOR_CR);
rkisp_update_regs(dev, DUAL_CROP_M_H_OFFS, ISP3X_DUAL_CROP_FBC_V_SIZE);
if (hw->isp_ver != ISP_V30)
rkisp_update_regs(dev, ISP_ACQ_PROP, ISP_ACQ_PROP);
rkisp_update_regs(dev, ISP_ACQ_V_OFFS, DUAL_CROP_CTRL);
rkisp_update_regs(dev, ISP39_LDCV_BIC_TABLE0, MI_WR_CTRL);
rkisp_update_regs(dev, SELF_RESIZE_SCALE_HY, ISP39_LDCV_CTRL);
rkisp_update_regs(dev, ISP32_BP_RESIZE_SCALE_HY, SELF_RESIZE_CTRL);
rkisp_update_regs(dev, MAIN_RESIZE_SCALE_HY, ISP32_BP_RESIZE_CTRL);
rkisp_update_regs(dev, ISP_GAMMA_OUT_CTRL, MAIN_RESIZE_CTRL);
rkisp_update_regs(dev, MI_RD_CTRL2, ISP_LSC_CTRL);
rkisp_update_regs(dev, MI_MP_WR_Y_BASE, MI_WR_CTRL2 - 4);
rkisp_update_regs(dev, ISP3X_CAC_PSF_PARA, ISP32_CAC_RO_CNT);
rkisp_update_regs(dev, ISP_LSC_XGRAD_01, ISP3X_CAC_CTRL);
rkisp_update_regs(dev, ISP39_W3A_CTRL1, ISP3X_RAWAWB_RAM_DATA_BASE);
rkisp_update_regs(dev, ISP32_CAC_RO_CNT, ISP39_W3A_CTRL0);
if (dev->isp_ver == ISP_V21) {
val = rkisp_read(dev, MI_WR_CTRL2, false);
rkisp_set_bits(dev, MI_WR_CTRL2, 0, val, true);
rkisp_write(dev, MI_WR_INIT, ISP21_SP_FORCE_UPD | ISP21_MP_FORCE_UPD, true);
} else {
if (dev->isp_ver >= ISP_V32_L)
rkisp_write(dev, ISP32_SELF_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true);
if (dev->isp_ver == ISP_V33 || dev->isp_ver == ISP_V39) {
rkisp_write(dev, ISP39_MAIN_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true);
if (dev->isp_ver == ISP_V33)
rkisp_write(dev, ISP33_BP_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true);
}
rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true);
}
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"sensor mode:%d index:%d | 0x%x\n",
dev->multi_mode, index, rkisp_read(dev, ISP_ACQ_H_OFFS, true));
}
void rkisp_online_update_reg(struct rkisp_device *dev, bool is_init, bool is_reset)
{
u32 val;
if (!is_init && dev->unite_index == ISP_UNITE_LEFT)
rkisp_stream_frame_start(dev, 0);
rkisp_update_list_reg(dev);
rkisp_params_cfgsram(&dev->params_vdev, true, is_reset);
val = rkisp_read(dev, ISP_CTRL, false);
val |= CIF_ISP_CTRL_ISP_CFG_UPD;
writel(val, dev->hw_dev->base_addr + ISP_CTRL);
if (!IS_HDR_RDBK(dev->rd_mode)) {
val = dev->rd_mode;
rkisp_write(dev, CSI2RX_CTRL0, SW_IBUF_OP_MODE(val), true);
}
}
static void rkisp_check_mi_ends_mask(struct rkisp_device *dev)
{
/* if output stream enable, wait it end */
u32 val = rkisp_read(dev, CIF_MI_CTRL_SHD, true);
if (val & CIF_MI_CTRL_SHD_MP_OUT_ENABLED)
dev->irq_ends_mask |= ISP_FRAME_MP;
else
dev->irq_ends_mask &= ~ISP_FRAME_MP;
if (val & CIF_MI_CTRL_SHD_SP_OUT_ENABLED)
dev->irq_ends_mask |= ISP_FRAME_SP;
else
dev->irq_ends_mask &= ~ISP_FRAME_SP;
if ((dev->isp_ver == ISP_V20 &&
rkisp_read(dev, ISP_MPFBC_CTRL, true) & SW_MPFBC_EN) ||
(dev->isp_ver == ISP_V30 &&
rkisp_read(dev, ISP3X_MPFBC_CTRL, true) & ISP3X_MPFBC_EN_SHD))
dev->irq_ends_mask |= ISP_FRAME_MPFBC;
else
dev->irq_ends_mask &= ~ISP_FRAME_MPFBC;
if ((dev->isp_ver == ISP_V30 &&
rkisp_read(dev, ISP3X_MI_BP_WR_CTRL, true) & ISP3X_BP_ENABLE) ||
((dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V33) &&
rkisp_read(dev, ISP32_MI_WR_CTRL2_SHD, true) & ISP32_BP_EN_OUT_SHD))
dev->irq_ends_mask |= ISP_FRAME_BP;
else
dev->irq_ends_mask &= ~ISP_FRAME_BP;
if (dev->isp_ver == ISP_V39 &&
rkisp_read(dev, ISP39_LDCV_CTRL, true) & ISP39_LDCV_EN_SHD)
dev->irq_ends_mask |= ISP_FRAME_LDC;
else
dev->irq_ends_mask &= ~ISP_FRAME_LDC;
}
/*
* for hdr read back mode, rawrd read back data
* this will update rawrd base addr to shadow.
@@ -665,62 +799,11 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo
rkisp_sditf_sof(dev, 0);
if (!hw->is_single) {
/* multi sensor need to reset isp resize mode if scale up */
val = 0;
if (rkisp_read(dev, ISP3X_MAIN_RESIZE_CTRL, true) & 0xf0)
val |= BIT(3);
if (dev->isp_ver != ISP_V32_L &&
rkisp_read(dev, ISP3X_SELF_RESIZE_CTRL, true) & 0xf0)
val |= BIT(4);
if (rkisp_read(dev, ISP32_BP_RESIZE_CTRL, true) & 0xf0)
val |= BIT(12);
if (val) {
writel(val, hw->base_addr + CIF_IRCL);
writel(0, hw->base_addr + CIF_IRCL);
}
/* sensor mode & index */
if (dev->isp_ver >= ISP_V21) {
val = rkisp_read_reg_cache(dev, ISP_ACQ_H_OFFS);
val |= ISP21_SENSOR_INDEX(dev->multi_index);
if (dev->isp_ver >= ISP_V32_L)
val |= ISP32L_SENSOR_MODE(dev->multi_mode);
else
val |= ISP21_SENSOR_MODE(dev->multi_mode);
writel(val, hw->base_addr + ISP_ACQ_H_OFFS);
if (hw->unite == ISP_UNITE_TWO)
writel(val, hw->base_next_addr + ISP_ACQ_H_OFFS);
}
rkisp_update_regs(dev, CTRL_VI_ISP_PATH, SUPER_IMP_COLOR_CR);
rkisp_update_regs(dev, DUAL_CROP_M_H_OFFS, ISP3X_DUAL_CROP_FBC_V_SIZE);
rkisp_update_regs(dev, ISP_ACQ_V_OFFS, DUAL_CROP_CTRL);
rkisp_update_regs(dev, ISP39_LDCV_BIC_TABLE0, MI_WR_CTRL);
rkisp_update_regs(dev, SELF_RESIZE_SCALE_HY, ISP39_LDCV_CTRL);
rkisp_update_regs(dev, ISP32_BP_RESIZE_SCALE_HY, SELF_RESIZE_CTRL);
rkisp_update_regs(dev, MAIN_RESIZE_SCALE_HY, ISP32_BP_RESIZE_CTRL);
rkisp_update_regs(dev, ISP_GAMMA_OUT_CTRL, MAIN_RESIZE_CTRL);
rkisp_update_regs(dev, MI_RD_CTRL2, ISP_LSC_CTRL);
rkisp_update_regs(dev, MI_MP_WR_Y_BASE, MI_WR_CTRL2 - 4);
rkisp_update_regs(dev, ISP39_W3A_CTRL1, ISP3X_RAWAWB_RAM_DATA_BASE);
rkisp_update_regs(dev, ISP_LSC_XGRAD_01, ISP39_W3A_CTRL0);
rkisp_update_list_reg(dev);
if (dev->isp_ver == ISP_V20 &&
(rkisp_read(dev, ISP_DHAZ_CTRL, false) & ISP_DHAZ_ENMUX ||
rkisp_read(dev, ISP_HDRTMO_CTRL, false) & ISP_HDRTMO_EN)) {
rkisp_read(dev, ISP_HDRTMO_CTRL, false) & ISP_HDRTMO_EN))
dma2frm += (dma2frm ? 0 : 1);
} else if (dev->isp_ver == ISP_V21) {
val = rkisp_read(dev, MI_WR_CTRL2, false);
rkisp_set_bits(dev, MI_WR_CTRL2, 0, val, true);
rkisp_write(dev, MI_WR_INIT, ISP21_SP_FORCE_UPD | ISP21_MP_FORCE_UPD, true);
} else {
if (dev->isp_ver == ISP_V32_L || dev->isp_ver == ISP_V39)
rkisp_write(dev, ISP32_SELF_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true);
if (dev->isp_ver == ISP_V39)
rkisp_write(dev, ISP39_MAIN_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true);
rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true);
}
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"sensor mode:%d index:%d | 0x%x\n",
dev->multi_mode, dev->multi_index, rkisp_read(dev, ISP_ACQ_H_OFFS, true));
is_upd = true;
}
@@ -848,35 +931,7 @@ run_next:
if (is_3dlut_upd)
rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 1, true);
/* if output stream enable, wait it end */
val = rkisp_read(dev, CIF_MI_CTRL_SHD, true);
if (val & CIF_MI_CTRL_SHD_MP_OUT_ENABLED)
dev->irq_ends_mask |= ISP_FRAME_MP;
else
dev->irq_ends_mask &= ~ISP_FRAME_MP;
if (val & CIF_MI_CTRL_SHD_SP_OUT_ENABLED)
dev->irq_ends_mask |= ISP_FRAME_SP;
else
dev->irq_ends_mask &= ~ISP_FRAME_SP;
if ((dev->isp_ver == ISP_V20 &&
rkisp_read(dev, ISP_MPFBC_CTRL, true) & SW_MPFBC_EN) ||
(dev->isp_ver == ISP_V30 &&
rkisp_read(dev, ISP3X_MPFBC_CTRL, true) & ISP3X_MPFBC_EN_SHD))
dev->irq_ends_mask |= ISP_FRAME_MPFBC;
else
dev->irq_ends_mask &= ~ISP_FRAME_MPFBC;
if ((dev->isp_ver == ISP_V30 &&
rkisp_read(dev, ISP3X_MI_BP_WR_CTRL, true) & ISP3X_BP_ENABLE) ||
(dev->isp_ver == ISP_V32 &&
rkisp_read(dev, ISP32_MI_WR_CTRL2_SHD, true) & ISP32_BP_EN_OUT_SHD))
dev->irq_ends_mask |= ISP_FRAME_BP;
else
dev->irq_ends_mask &= ~ISP_FRAME_BP;
if (dev->isp_ver == ISP_V39 &&
rkisp_read(dev, ISP39_LDCV_CTRL, true) & ISP39_LDCV_EN_SHD)
dev->irq_ends_mask |= ISP_FRAME_LDC;
else
dev->irq_ends_mask &= ~ISP_FRAME_LDC;
rkisp_check_mi_ends_mask(dev);
if (hw->is_frm_buf) {
val = ISP32L_WR_FRM_BUF_EN | ISP32L_RD_FRM_BUF_EN |
@@ -940,6 +995,13 @@ static void rkisp_fast_switch_rx_buf(struct rkisp_device *dev, bool is_current)
}
}
void rkisp_vicap_hw_link(struct rkisp_device *dev, int on)
{
struct v4l2_subdev *sd = dev->active_sensor->sd;
v4l2_subdev_call(sd, core, ioctl, RKISP_VICAP_CMD_HW_LINK, &on);
}
static void rkisp_rdbk_trigger_handle(struct rkisp_device *dev, u32 cmd)
{
struct rkisp_hw_dev *hw = dev->hw_dev;
@@ -961,7 +1023,7 @@ static void rkisp_rdbk_trigger_handle(struct rkisp_device *dev, u32 cmd)
if (hw->unite == ISP_UNITE_ONE) {
if (hw->is_multi_overflow && dev->sw_rd_cnt < 2)
isp->unite_index = ISP_UNITE_RIGHT;
else if (hw->is_frm_buf)
else if (!hw->is_multi_overflow)
isp->unite_index++;
if (!hw->is_multi_overflow || (dev->sw_rd_cnt & 0x1))
is_try = false;
@@ -970,6 +1032,21 @@ static void rkisp_rdbk_trigger_handle(struct rkisp_device *dev, u32 cmd)
}
hw->is_idle = true;
hw->pre_dev_id = dev->dev_id;
/* fast unite offline switch to online */
if (dev->unite_div > ISP_UNITE_DIV1 && !IS_HDR_RDBK(dev->rd_mode))
isp = dev;
else
isp = hw->isp[!dev->dev_id];
if (isp &&
isp->isp_state & ISP_START &&
!IS_HDR_RDBK(isp->rd_mode)) {
hw->is_idle = false;
hw->cur_dev_id = isp->dev_id;
spin_unlock_irqrestore(&hw->rdbk_lock, lock_flags);
rkisp_online_update_reg(isp, false, false);
rkisp_vicap_hw_link(isp, true);
return;
}
}
if (hw->is_shutdown)
hw->is_idle = false;
@@ -977,8 +1054,6 @@ static void rkisp_rdbk_trigger_handle(struct rkisp_device *dev, u32 cmd)
goto end;
if (hw->monitor.state & ISP_MIPI_ERROR && hw->monitor.is_en)
goto end;
if (!IS_HDR_RDBK(dev->rd_mode))
goto end;
if (dev->is_suspend) {
if (dev->suspend_sync)
complete(&dev->pm_cmpl);
@@ -1041,7 +1116,7 @@ static void rkisp_rdbk_trigger_handle(struct rkisp_device *dev, u32 cmd)
isp->sw_rd_cnt *= 2;
isp->sw_rd_cnt += 1;
}
} else if (hw->is_frm_buf) {
} else {
isp->sw_rd_cnt += (isp->unite_div - 1);
}
/* first frame handle twice for thunderboot
@@ -1112,12 +1187,74 @@ static void rkisp_rdbk_work(struct work_struct *work)
rkisp_rdbk_trigger_event(dev, T_CMD_END, NULL);
}
static void rkisp_multi_online_switch(struct rkisp_device *dev)
{
struct rkisp_hw_dev *hw = dev->hw_dev;
struct rkisp_device *isp = NULL;
int val = 0, id = dev->dev_id;
unsigned long lock_flags = 0;
bool is_switch = false;
bool to_online = false;
bool is_to_off = true;
dev->irq_ends = 0;
if (dev->unite_div == ISP_UNITE_DIV2) {
if (dev->unite_index == ISP_UNITE_LEFT) {
rkisp_vicap_hw_link(dev, false);
dev->unite_index = ISP_UNITE_RIGHT;
rkisp_online_update_reg(dev, false, false);
val = dev->rd_mode == HDR_NORMAL ? HDR_RDBK_FRAME1 : HDR_RDBK_FRAME2;
rkisp_write(dev, CSI2RX_CTRL0, SW_IBUF_OP_MODE(val) | SW_CSI2RX_EN, true);
return;
}
is_to_off = false;
dev->unite_index = ISP_UNITE_LEFT;
dev->params_vdev.rdbk_times = 2;
}
isp = hw->isp[!id];
if (isp && isp->isp_state & ISP_START) {
if (!IS_HDR_RDBK(isp->rd_mode)) {
is_switch = true;
to_online = true;
} else {
val = 0;
rkisp_rdbk_trigger_event(isp, T_CMD_LEN, &val);
if (val || dev->is_multi_one_sync || dev->vicap_in.multi_sync) {
is_switch = true;
if (dev->is_multi_one_sync)
dev->is_multi_one_sync = false;
}
}
}
if (is_to_off)
rkisp_vicap_hw_link(dev, false);
if (!is_switch) {
rkisp_online_update_reg(dev, false, false);
rkisp_vicap_hw_link(dev, true);
} else {
if (to_online) {
spin_lock_irqsave(&hw->rdbk_lock, lock_flags);
hw->cur_dev_id = isp->dev_id;
spin_unlock_irqrestore(&hw->rdbk_lock, lock_flags);
rkisp_online_update_reg(isp, false, false);
rkisp_vicap_hw_link(isp, true);
} else {
spin_lock_irqsave(&hw->rdbk_lock, lock_flags);
hw->is_idle = true;
spin_unlock_irqrestore(&hw->rdbk_lock, lock_flags);
rkisp_rdbk_trigger_event(isp, T_CMD_QUEUE, NULL);
}
}
}
void rkisp_check_idle(struct rkisp_device *dev, u32 irq)
{
struct rkisp_hw_dev *hw = dev->hw_dev;
unsigned long lock_flags = 0;
u32 val = 0;
if (!IS_HDR_RDBK(dev->rd_mode))
if (hw->is_single && !IS_HDR_RDBK(dev->rd_mode))
return;
spin_lock_irqsave(&dev->hw_dev->rdbk_lock, lock_flags);
@@ -1137,6 +1274,10 @@ void rkisp_check_idle(struct rkisp_device *dev, u32 irq)
}
spin_unlock_irqrestore(&dev->hw_dev->rdbk_lock, lock_flags);
/* two virtual isp online frame end switch to other isp */
if (!hw->is_single && !IS_HDR_RDBK(dev->rd_mode))
rkisp_multi_online_switch(dev);
if (dev->sw_rd_cnt)
goto end;
@@ -1167,6 +1308,9 @@ void rkisp_check_idle(struct rkisp_device *dev, u32 irq)
}
}
if (!IS_HDR_RDBK(dev->rd_mode))
return;
val = 0;
switch (dev->rd_mode) {
case HDR_RDBK_FRAME3://for rd1 rd0 rd2
@@ -1183,6 +1327,9 @@ void rkisp_check_idle(struct rkisp_device *dev, u32 irq)
end:
dev->irq_ends = 0;
if (dev->is_wait_aiq &&
(dev->unite_div < ISP_UNITE_DIV2 || dev->unite_index == ISP_UNITE_RIGHT))
return;
if (dev->hw_dev->is_dvfs)
schedule_work(&dev->rdbk_work);
else
@@ -1232,7 +1379,8 @@ static void rkisp_config_ism(struct rkisp_device *dev)
mult = 2;
rkisp_unite_write(dev, CIF_ISP_IS_V_SIZE, height / mult, false);
if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32)
if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32 ||
dev->isp_ver == ISP_V33)
return;
/* IS(Image Stabilization) is always on, working as output crop */
@@ -1266,6 +1414,14 @@ static int rkisp_reset_handle(struct rkisp_device *dev)
rkisp_trigger_read_back(dev, 1, 0, true);
else
rkisp_rdbk_trigger_event(dev, T_CMD_QUEUE, NULL);
} else if (!dev->hw_dev->is_single) {
if (dev->unite_div == ISP_UNITE_DIV2) {
dev->unite_index = ISP_UNITE_LEFT;
dev->params_vdev.rdbk_times = 2;
}
rkisp_online_update_reg(dev, false, true);
val = 1;
rkisp_vicap_hw_link(dev, val);
}
dev_info(dev->dev, "%s exit\n", __func__);
return 0;
@@ -1645,7 +1801,8 @@ static void rkisp_config_cmsk(struct rkisp_device *dev)
unsigned long lock_flags = 0;
struct rkisp_cmsk_cfg cfg;
if (dev->isp_ver != ISP_V30 && dev->isp_ver != ISP_V32)
if (dev->isp_ver != ISP_V30 && dev->isp_ver != ISP_V32 &&
dev->isp_ver != ISP_V33)
return;
spin_lock_irqsave(&dev->cmsk_lock, lock_flags);
@@ -1817,6 +1974,7 @@ static int rkisp_config_isp(struct rkisp_device *dev)
rkisp_config_color_space(dev);
rkisp_params_first_cfg(&dev->params_vdev, in_fmt,
dev->isp_sdev.quantization);
rkisp_stats_first_ddr_config(&dev->stats_vdev);
}
if (!dev->hw_dev->is_single && atomic_read(&dev->hw_dev->refcnt) <= 1) {
rkisp_update_regs(dev, CIF_ISP_ACQ_H_OFFS, CIF_ISP_ACQ_V_SIZE);
@@ -2147,15 +2305,18 @@ static int rkisp_isp_stop(struct rkisp_device *dev)
hw->is_mi_update = false;
hw->pre_dev_id = -1;
end:
dev->is_frm_rd = false;
dev->irq_ends_mask = 0;
dev->hdr.op_mode = 0;
dev->sw_rd_cnt = 0;
dev->stats_vdev.rdbk_drop = false;
dev->is_multi_one_sync = false;
rkisp_set_state(&dev->isp_state, ISP_STOP);
if (dev->isp_ver >= ISP_V20)
kfifo_reset(&dev->rdbk_kfifo);
if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32)
if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32 ||
dev->isp_ver == ISP_V33)
memset(&dev->cmsk_cfg, 0, sizeof(dev->cmsk_cfg));
if (dev->emd_vc <= CIF_ISP_ADD_DATA_VC_MAX) {
for (i = 0; i < RKISP_EMDDATA_FIFO_MAX; i++)
@@ -2173,9 +2334,6 @@ end:
static int rkisp_isp_start(struct rkisp_device *dev)
{
struct rkisp_hw_dev *hw = dev->hw_dev;
struct rkisp_sensor_info *sensor = dev->active_sensor;
void __iomem *base = dev->base_addr;
bool is_direct = true;
u32 val;
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
@@ -2203,32 +2361,15 @@ static int rkisp_isp_start(struct rkisp_device *dev)
}
}
/* Activate MIPI */
if (sensor && sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
/* clear interrupts state */
readl(base + CIF_ISP_CSI0_ERR1);
readl(base + CIF_ISP_CSI0_ERR2);
readl(base + CIF_ISP_CSI0_ERR3);
/* csi2host enable */
writel(1, base + CIF_ISP_CSI0_CTRL0);
} else if (dev->isp_ver < ISP_V12) {
val = readl(base + CIF_MIPI_CTRL);
writel(val | CIF_MIPI_CTRL_OUTPUT_ENA,
base + CIF_MIPI_CTRL);
}
}
/* Activate ISP */
val = rkisp_read_reg_cache(dev, CIF_ISP_CTRL);
val |= CIF_ISP_CTRL_ISP_CFG_UPD | CIF_ISP_CTRL_ISP_ENABLE |
CIF_ISP_CTRL_ISP_INFORM_ENABLE | CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT;
if (dev->isp_ver == ISP_V20)
val |= NOC_HURRY_PRIORITY(2) | NOC_HURRY_W_MODE(2) | NOC_HURRY_R_MODE(1);
if (atomic_read(&hw->refcnt) > 1)
is_direct = false;
else
if (atomic_read(&hw->refcnt) == 1)
hw->cur_dev_id = dev->dev_id;
rkisp_unite_write(dev, CIF_ISP_CTRL, val, is_direct);
rkisp_unite_write(dev, CIF_ISP_CTRL, val, false);
rkisp_clear_reg_cache_bits(dev, CIF_ISP_CTRL, CIF_ISP_CTRL_ISP_CFG_UPD);
dev->isp_err_cnt = 0;
@@ -2238,7 +2379,8 @@ static int rkisp_isp_start(struct rkisp_device *dev)
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"%s MI_CTRL 0x%08x ISP_CTRL 0x%08x\n", __func__,
readl(base + CIF_MI_CTRL), readl(base + CIF_ISP_CTRL));
rkisp_read(dev, CIF_MI_CTRL, false),
rkisp_read(dev, CIF_ISP_CTRL, false));
if (hw->monitor.is_en && atomic_read(&hw->refcnt) < 2) {
hw->monitor.retry = 0;
@@ -2702,6 +2844,9 @@ static void rkisp_isp_sd_try_crop(struct v4l2_subdev *sd,
case ISP_V32_L:
size = CIF_ISP_INPUT_W_MAX_V32_L * CIF_ISP_INPUT_H_MAX_V32_L;
break;
case ISP_V33:
size = CIF_ISP_INPUT_W_MAX_V33 * CIF_ISP_INPUT_H_MAX_V33;
break;
case ISP_V39:
size = CIF_ISP_INPUT_W_MAX_V39_UNITE * CIF_ISP_INPUT_H_MAX_V39_UNITE;
size /= 2;
@@ -2783,6 +2928,12 @@ static int rkisp_isp_sd_get_selection(struct v4l2_subdev *sd,
max_h = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V32_L_UNITE : CIF_ISP_INPUT_H_MAX_V32_L;
break;
case ISP_V33:
max_w = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V33_UNITE : CIF_ISP_INPUT_W_MAX_V33;
max_h = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V33_UNITE : CIF_ISP_INPUT_H_MAX_V33;
break;
case ISP_V39:
max_w = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V39_UNITE : CIF_ISP_INPUT_W_MAX_V39;
@@ -2947,7 +3098,6 @@ static void rkisp_global_update_mi(struct rkisp_device *dev)
struct rkisp_stream *stream;
int i;
rkisp_stats_first_ddr_config(&dev->stats_vdev);
if (dev->hw_dev->is_mi_update)
return;
@@ -3012,6 +3162,16 @@ static int rkisp_isp_sd_s_stream(struct v4l2_subdev *sd, int on)
rkisp_config_cif(isp_dev);
rkisp_isp_start(isp_dev);
if (!hw_dev->is_single &&
!IS_HDR_RDBK(isp_dev->rd_mode) &&
atomic_read(&hw_dev->refcnt) == 1) {
if (isp_dev->unite_div == ISP_UNITE_DIV2) {
isp_dev->unite_index = ISP_UNITE_LEFT;
isp_dev->params_vdev.rdbk_times = 2;
}
rkisp_online_update_reg(isp_dev, true, false);
hw_dev->is_idle = false;
}
rkisp_global_update_mi(isp_dev);
isp_dev->isp_state = ISP_START | ISP_FRAME_END;
rkisp_rdbk_trigger_event(isp_dev, T_CMD_QUEUE, NULL);
@@ -3052,8 +3212,9 @@ static void rkisp_rx_qbuf_online(struct rkisp_stream *stream,
u32 val = pool->buf.buff_addr[RKISP_PLANE_Y];
u32 reg = stream->config->mi.y_base_ad_init;
rkisp_write(dev, reg, val, false);
if (dev->hw_dev->unite == ISP_UNITE_TWO) {
rkisp_unite_write(dev, reg, val, false);
if (dev->hw_dev->unite == ISP_UNITE_TWO ||
(dev->unite_div == ISP_UNITE_DIV2 && stream->id == RKISP_STREAM_RAWRD0)) {
u32 offs = stream->out_fmt.width / 2 - RKMOUDLE_UNITE_EXTEND_PIXEL;
if (stream->memory)
@@ -3234,6 +3395,12 @@ end:
stream->memory = SW_CSI_RAW_WR_SIMG_MODE;
rkisp_dmarx_set_fmt(stream, stream->out_fmt);
stream->ops->config_mi(stream);
if (dev->hdr_wrap_line && stream->id != RKISP_STREAM_RAWRD2) {
u32 size = dev->hdr_wrap_line *
stream->out_fmt.plane_fmt[0].bytesperline;
rkisp_unite_write(dev, ISP32_MI_RAW0_RD_SIZE, size, false);
}
dbufs->is_first = false;
}
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
@@ -3429,6 +3596,7 @@ static int rkisp_subdev_link_setup(struct media_entity *entity,
if (dev->isp_inp & rawrd) {
dev->dmarx_dev.trigger = T_MANUAL;
dev->is_rdbk_auto = false;
dev->is_m_online = false;
} else {
dev->dmarx_dev.trigger = T_AUTO;
}
@@ -3442,6 +3610,7 @@ static int rkisp_subdev_link_setup(struct media_entity *entity,
/* read back mode only */
if (dev->isp_ver < ISP_V30 || !dev->hw_dev->is_single)
mode.rdbk_mode = RKISP_VICAP_RDBK_AIQ;
mode.dev_id = dev->dev_id;
v4l2_subdev_call(remote, core, ioctl,
RKISP_VICAP_CMD_MODE, &mode);
dev->vicap_in = mode.input;
@@ -3566,10 +3735,11 @@ static int rkisp_set_work_mode_by_vicap(struct rkisp_device *isp_dev,
{
struct rkisp_hw_dev *hw = isp_dev->hw_dev;
int rd_mode = isp_dev->rd_mode;
u32 val, mask;
isp_dev->is_suspend_one_frame = false;
if (vicap_mode->rdbk_mode == RKISP_VICAP_ONLINE) {
if (!hw->is_single)
if (vicap_mode->rdbk_mode < RKISP_VICAP_RDBK_AIQ) {
if (!hw->is_single && hw->isp_ver != ISP_V33)
return -EINVAL;
/* switch to online mode for single sensor */
switch (rd_mode) {
@@ -3582,8 +3752,10 @@ static int rkisp_set_work_mode_by_vicap(struct rkisp_device *isp_dev,
default:
isp_dev->rd_mode = HDR_NORMAL;
}
} else if (vicap_mode->rdbk_mode == RKISP_VICAP_RDBK_AUTO ||
vicap_mode->rdbk_mode == RKISP_VICAP_RDBK_AUTO_ONE_FRAME) {
if (!hw->is_single && !IS_HDR_RDBK(rd_mode) &&
vicap_mode->rdbk_mode == RKISP_VICAP_ONLINE_ONE_FRAME)
isp_dev->is_multi_one_sync = true;
} else {
/* switch to readback mode */
switch (rd_mode) {
case HDR_LINEX3_DDR:
@@ -3595,21 +3767,27 @@ static int rkisp_set_work_mode_by_vicap(struct rkisp_device *isp_dev,
default:
isp_dev->rd_mode = HDR_RDBK_FRAME1;
}
if (vicap_mode->rdbk_mode == RKISP_VICAP_RDBK_AUTO_ONE_FRAME)
if (hw->isp_ver == ISP_V32 &&
vicap_mode->rdbk_mode == RKISP_VICAP_RDBK_AUTO_ONE_FRAME)
isp_dev->is_suspend_one_frame = true;
} else {
return -EINVAL;
}
isp_dev->hdr.op_mode = isp_dev->rd_mode;
if (rd_mode != isp_dev->rd_mode && hw->cur_dev_id == isp_dev->dev_id) {
rkisp_unite_write(isp_dev, CSI2RX_CTRL0,
SW_IBUF_OP_MODE(isp_dev->rd_mode), true);
if (IS_HDR_RDBK(isp_dev->rd_mode))
rkisp_unite_set_bits(isp_dev, CTRL_SWS_CFG, 0,
SW_MPIP_DROP_FRM_DIS, true);
else
rkisp_unite_clear_bits(isp_dev, CTRL_SWS_CFG,
SW_MPIP_DROP_FRM_DIS, true);
mask = SW_MPIP_DROP_FRM_DIS;
if (isp_dev->isp_ver == ISP_V33)
mask |= ISP33_SW_ISP2ENC_PATH_EN | ISP33_PP_ENC_PIPE_EN;
if (IS_HDR_RDBK(isp_dev->rd_mode)) {
val = SW_MPIP_DROP_FRM_DIS;
if (isp_dev->isp_ver == ISP_V33 && isp_dev->cap_dev.wrap_line)
val = ISP33_SW_ISP2ENC_PATH_EN | ISP33_PP_ENC_PIPE_EN;
} else if (isp_dev->isp_ver == ISP_V33 && isp_dev->cap_dev.wrap_line) {
val = ISP33_SW_ISP2ENC_PATH_EN;
} else {
val = 0;
}
rkisp_unite_set_bits(isp_dev, CTRL_SWS_CFG, mask, val, true);
}
return 0;
}
@@ -3771,6 +3949,29 @@ static int rkisp_get_offline_raw_buf_cnt(struct rkisp_device *dev, int *cnt)
return 0;
}
static int rkisp_set_online_hdr_wrap(struct rkisp_device *dev, int *line)
{
if (dev->isp_inp & (INP_RAWRD0 | INP_RAWRD2)) {
v4l2_warn(&dev->v4l2_dev,
"hdr wrap no support for offline\n");
return -EINVAL;
}
if (dev->isp_ver != ISP_V33 || dev->unite_div != ISP_UNITE_DIV1) {
v4l2_warn(&dev->v4l2_dev,
"hdr wrap support for 1103b and no unite mode\n");
return -EINVAL;
}
dev->hdr_wrap_line = *line;
rkisp_hdr_wrap_line[dev->dev_id] = *line;
return 0;
}
static int rkisp_get_online_hdr_wrap(struct rkisp_device *dev, int *line)
{
*line = dev->hdr_wrap_line;
return 0;
}
static void rkisp_config_fpn(struct rkisp_device *dev)
{
struct rkisp_fpn_cfg *cfg = &dev->fpn_cfg;
@@ -3854,6 +4055,7 @@ static long rkisp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
struct rkisp_device *isp_dev = sd_to_isp_dev(sd);
struct rkisp_thunderboot_resmem *resmem;
struct rkisp32_thunderboot_resmem_head *tb_head_v32;
struct rkisp33_thunderboot_resmem_head *tb_head_v33;
struct rkisp_thunderboot_resmem_head *head;
struct rkisp_thunderboot_shmem *shmem;
struct isp2x_buf_idxfd *idxfd;
@@ -3886,9 +4088,21 @@ static long rkisp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
memcpy(&tb_head_v32->cfg, isp_dev->params_vdev.isp32_params,
sizeof(struct isp32_isp_params_cfg));
break;
case RKISP_CMD_GET_TB_HEAD_V33:
if (isp_dev->tb_head.complete != RKISP_TB_OK ||
(!isp_dev->is_rtt_suspend && !isp_dev->is_pre_on)) {
ret = -EINVAL;
break;
}
tb_head_v33 = arg;
memcpy(tb_head_v33, &isp_dev->tb_head,
sizeof(struct rkisp_thunderboot_resmem_head));
memcpy(&tb_head_v33->cfg, isp_dev->params_vdev.isp33_params,
sizeof(struct isp33_isp_params_cfg));
break;
case RKISP_CMD_SET_TB_HEAD_V32:
tb_head_v32 = arg;
memcpy(&isp_dev->tb_head, tb_head_v32,
case RKISP_CMD_SET_TB_HEAD_V33:
memcpy(&isp_dev->tb_head, arg,
sizeof(struct rkisp_thunderboot_resmem_head));
break;
case RKISP_CMD_GET_SHARED_BUF:
@@ -4008,6 +4222,12 @@ static long rkisp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
case RKISP_CMD_GET_OFFLINE_RAW_BUFCNT:
ret = rkisp_get_offline_raw_buf_cnt(isp_dev, arg);
break;
case RKISP_CMD_SET_ONLINE_HDR_WRAP_LINE:
ret = rkisp_set_online_hdr_wrap(isp_dev, arg);
break;
case RKISP_CMD_GET_ONLINE_HDR_WRAP_LINE:
ret = rkisp_get_online_hdr_wrap(isp_dev, arg);
break;
case RKISP_CMD_SET_FPN:
ret = rkisp_set_fpn(isp_dev, arg);
break;
@@ -4101,10 +4321,12 @@ static long rkisp_compat_ioctl32(struct v4l2_subdev *sd,
cp_t_us = true;
break;
case RKISP_CMD_SET_OFFLINE_RAW_BUFCNT:
case RKISP_CMD_SET_ONLINE_HDR_WRAP_LINE:
size = sizeof(int);
cp_f_us = true;
break;
case RKISP_CMD_GET_OFFLINE_RAW_BUFCNT:
case RKISP_CMD_GET_ONLINE_HDR_WRAP_LINE:
size = sizeof(int);
cp_t_us = true;
break;
@@ -4300,6 +4522,10 @@ void rkisp_save_tb_info(struct rkisp_device *isp_dev)
size = sizeof(struct rkisp32_thunderboot_resmem_head);
offset = size * isp_dev->dev_id;
break;
case ISP_V33:
size = sizeof(struct rkisp33_thunderboot_resmem_head);
offset = size * isp_dev->dev_id;
break;
default:
break;
}
@@ -4312,6 +4538,16 @@ void rkisp_save_tb_info(struct rkisp_device *isp_dev)
if (isp_dev->isp_ver == ISP_V32) {
struct rkisp32_thunderboot_resmem_head *tmp = resmem_va + offset;
param = &tmp->cfg;
head = &tmp->head;
v4l2_info(&isp_dev->v4l2_dev,
"tb param module en:0x%llx upd:0x%llx cfg upd:0x%llx\n",
tmp->cfg.module_en_update,
tmp->cfg.module_ens,
tmp->cfg.module_cfg_update);
} else if (isp_dev->isp_ver == ISP_V33) {
struct rkisp33_thunderboot_resmem_head *tmp = resmem_va + offset;
param = &tmp->cfg;
head = &tmp->head;
v4l2_info(&isp_dev->v4l2_dev,
@@ -4320,8 +4556,11 @@ void rkisp_save_tb_info(struct rkisp_device *isp_dev)
tmp->cfg.module_ens,
tmp->cfg.module_cfg_update);
}
if (param && (isp_dev->isp_state & ISP_STOP))
if (param && (isp_dev->isp_state & ISP_STOP)) {
params_vdev->ops->get_param_size(params_vdev,
&params_vdev->vdev_fmt.fmt.meta.buffersize);
params_vdev->ops->save_first_param(params_vdev, param);
}
} else if (size > isp_dev->resmem_size) {
v4l2_err(&isp_dev->v4l2_dev,
"resmem size:%zu no enough for head:%d\n",
@@ -4343,7 +4582,8 @@ void rkisp_chk_tb_over(struct rkisp_device *isp_dev)
if (!isp_dev->is_thunderboot)
return;
if (isp_dev->isp_ver == ISP_V32 && params_vdev->is_first_cfg)
if (params_vdev->is_first_cfg &&
(isp_dev->isp_ver == ISP_V32 || isp_dev->isp_ver == ISP_V33))
goto end;
resmem_va = phys_to_virt(isp_dev->resmem_pa);
@@ -4352,9 +4592,11 @@ void rkisp_chk_tb_over(struct rkisp_device *isp_dev)
sizeof(struct rkisp_thunderboot_resmem_head),
DMA_FROM_DEVICE);
shm_head_poll_timeout(isp_dev, !!head->complete, 5000, 400 * USEC_PER_MSEC);
if (head->complete != RKISP_TB_OK) {
v4l2_err(&isp_dev->v4l2_dev, "wait thunderboot over timeout\n");
shm_head_poll_timeout(isp_dev, !!head->complete, 5000, 1000 * USEC_PER_MSEC);
if (head->complete == RKISP_TB_RUN) {
v4l2_err(&isp_dev->v4l2_dev, "wait thunderboot over timeout, tb still running\n");
} else if (head->complete == RKISP_TB_NG) {
v4l2_err(&isp_dev->v4l2_dev, "thunderboot result error");
} else {
int i, timeout = 50;
@@ -4395,15 +4637,26 @@ end:
}
if (hw->is_thunderboot) {
rkisp_register_irq(hw);
if (head->complete != RKISP_TB_RUN) {
rkisp_register_irq(hw);
rkisp_tb_unprotect_clk();
}
rkisp_tb_set_state(tb_state);
rkisp_tb_unprotect_clk();
hw->is_thunderboot = false;
}
isp_dev->is_thunderboot = false;
if (head->complete != RKISP_TB_RUN)
isp_dev->is_thunderboot = false;
}
#endif
static void rkisp_dvbm_start_event(struct rkisp_device *dev)
{
struct rkisp_stream *stream = &dev->cap_dev.stream[0];
if (stream->streaming && !stream->ops->is_stream_stopped(stream))
rkisp_dvbm_event(dev, CIF_ISP_V_START);
}
/**************** Interrupter Handler ****************/
void rkisp_mipi_isr(unsigned int mis, struct rkisp_device *dev)
@@ -4562,6 +4815,7 @@ void rkisp_isp_isr(unsigned int isp_mis,
complete(&dev->hw_dev->monitor.cmpl);
}
rkisp_dvbm_start_event(dev);
if (IS_HDR_RDBK(dev->hdr.op_mode)) {
/* disabled frame end to read 3dlut for multi sensor
* 3dlut will update at isp readback
@@ -4573,6 +4827,10 @@ void rkisp_isp_isr(unsigned int isp_mis,
}
rkisp_stats_rdbk_enable(&dev->stats_vdev, true);
goto vs_skip;
} else if (!hw->is_single) {
rkisp_check_mi_ends_mask(dev);
if (dev->unite_index == ISP_UNITE_RIGHT)
goto vs_skip;
}
if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced) {
/* 0 = ODD 1 = EVEN */
@@ -4742,7 +5000,7 @@ vs_skip:
}
if (isp_mis & CIF_ISP_FRAME) {
if (dev->hw_dev->isp_ver == ISP_V32) {
if (dev->isp_ver == ISP_V32) {
struct rkisp_stream *s = &dev->cap_dev.stream[RKISP_STREAM_LUMA];
s->ops->frame_end(s, FRAME_IRQ);

6
drivers/media/platform/rockchip/isp/rkisp.h
View File

@@ -67,8 +67,12 @@
#define CIF_ISP_INPUT_H_MAX_V39 3504
#define CIF_ISP_INPUT_W_MAX_V39_UNITE 8192
#define CIF_ISP_INPUT_H_MAX_V39_UNITE 6144
#define CIF_ISP_INPUT_W_MAX_V33 2880
#define CIF_ISP_INPUT_H_MAX_V33 1620
#define CIF_ISP_INPUT_W_MAX_V33_UNITE 3840
#define CIF_ISP_INPUT_H_MAX_V33_UNITE 2160
#define CIF_ISP_INPUT_W_MIN 272
#define CIF_ISP_INPUT_H_MIN 272
#define CIF_ISP_INPUT_H_MIN 264
#define CIF_ISP_OUTPUT_W_MAX CIF_ISP_INPUT_W_MAX
#define CIF_ISP_OUTPUT_H_MAX CIF_ISP_INPUT_H_MAX
#define CIF_ISP_OUTPUT_W_MIN CIF_ISP_INPUT_W_MIN

7
include/soc/rockchip/rockchip_rockit.h
View File

@@ -55,6 +55,7 @@ struct ISP_VIDEO_FRAMES {
u64 u64PrivateData;
u32 u32FrameFlag; /* FRAME_FLAG_E, can be OR operation. */
u8 ispEncCnt;
};
struct rkisp_dev_cfg {
@@ -75,6 +76,10 @@ struct rockit_cfg {
int isp_num;
u32 nick_id;
u32 event;
u32 y_offset;
u32 u_offset;
u32 v_offset;
u32 vir_width;
void *node;
void *mpibuf;
void *vvi_dev[ROCKIT_ISP_NUM_MAX];
@@ -120,7 +125,7 @@ struct rockit_rkcif_cfg {
int (*rkcif_rockit_mpibuf_done)(struct rockit_rkcif_cfg *rockit_cif_cfg);
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32)
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32) || IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V33)
void *rkisp_rockit_function_register(void *function, int cmd);
int rkisp_rockit_get_ispdev(char **name);

20
include/uapi/linux/rk-isp2-config.h
View File

@@ -80,6 +80,12 @@
#define RKISP_CMD_GET_OFFLINE_RAW_BUFCNT \
_IOR('V', BASE_VIDIOC_PRIVATE + 22, int)
#define RKISP_CMD_SET_ONLINE_HDR_WRAP_LINE \
_IOW('V', BASE_VIDIOC_PRIVATE + 23, int)
#define RKISP_CMD_GET_ONLINE_HDR_WRAP_LINE \
_IOR('V', BASE_VIDIOC_PRIVATE + 24, int)
#define RKISP_CMD_SET_FPN \
_IOW('V', BASE_VIDIOC_PRIVATE + 25, struct rkisp_fpn_cfg)
@@ -411,6 +417,12 @@ struct rkisp_bay3dbuf_info {
int ds_fd;
int ds_size;
} v32;
struct {
int ds_fd;
int ds_size;
int gain_fd;
int gain_size;
} v33;
struct {
int gain_fd;
int gain_size;
@@ -430,7 +442,7 @@ struct rkisp_bay3dbuf_info {
* RKISP_CMSK_WIN_MAX_V30 for rk3588 support 8 windows, and
* support for mainpath and selfpath output stream channel.
*
* RKISP_CMSK_WIN_MAX for rv1106 support 12 windows, and
* RKISP_CMSK_WIN_MAX for rv1106/rv1103b support 12 windows, and
* support for mainpath selfpath and bypasspath output stream channel.
*
* mode: 0:mosaic mode, 1:cover mode
@@ -2077,6 +2089,8 @@ enum {
RKISP_RTT_MODE_ONE_FRAME,
};
#define MAX_PRE_BUF_NUM (4)
/**
* struct rkisp_thunderboot_resmem_head
*/
@@ -2097,8 +2111,12 @@ struct rkisp_thunderboot_resmem_head {
__u32 exp_time_reg[3];
__u32 exp_gain_reg[3];
__u32 exp_isp_dgain[3];
__u32 dcg_mode[3];
__u32 nr_buf_size;
__u32 share_mem_size;
__u32 pre_buf_num;
__u32 pre_buf_addr[MAX_PRE_BUF_NUM];
__u32 pre_buf_timestamp[MAX_PRE_BUF_NUM];
} __attribute__ ((packed));
/**

1476
include/uapi/linux/rk-isp33-config.h Normal file
View File

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