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ARM: dts: rv1106-uvc: Add support pll frac mode for audio

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This patch add pll frac freq around 1G for audio product,
which will do fine tune pll for async clk situation,
such as BT, UAC.

Because we have no much more PLLs, and much more devices
share the same PLL, so, we should setup around 1G to serve
all the devices.

PLLs in rv1106:

  APLL: CPU
  DPLL: DDR
  GPLL: DEVICES
  CPLL: DEVICES

  GPLL: 1188MHz
  CPLL: 1000MHz

* PLLs support frac mode:

  GPLL
  DPLL

So, the only way to use audio pll frac freq is to switch to
use GPLL. and switch the role of GPLL and CPLL.

  GPLL: audio frac freq (~1G)
  CPLL: 1188MHz

Tested by UAC product, so, we first address this. and, of course,
there still have chance apply this to other situation, such as IPC.
but, need more test. at this time, we just handle for UAC.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ief13456b6274802836266228d3288d91a148feff
This commit is contained in:
Sugar Zhang
2022-07-13 09:05:16 +08:00
committed by Tao Huang
parent 1fd942ea8b
commit bd0b0782e7
1 changed files with 27 additions and 0 deletions
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27
arch/arm/boot/dts/rv1106-uvc.dtsi
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@@ -7,6 +7,33 @@
};
&cru {
assigned-clocks =
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru ARMCLK>,
<&cru CLK_50M_SRC>, <&cru CLK_100M_SRC>,
<&cru CLK_150M_SRC>, <&cru CLK_200M_SRC>,
<&cru CLK_250M_SRC>, <&cru CLK_300M_SRC>,
<&cru CLK_339M_SRC>, <&cru CLK_400M_SRC>,
<&cru CLK_450M_SRC>, <&cru CLK_500M_SRC>,
<&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>,
<&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>,
<&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>,
<&cru HCLK_PMU_ROOT>;
assigned-clock-rates =
<983040000>, <1188000000>,
<1104000000>,
<50000000>, <100000000>,
<150000000>, <200000000>,
<250000000>, <300000000>,
<340000000>, <400000000>,
<450000000>, <500000000>,
<400000000>, <200000000>,
<100000000>, <300000000>,
<100000000>, <100000000>,
<200000000>;
};
&fiq_debugger {
rockchip,irq-mode-enable = <1>;
status = "okay";