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Revert "PCIe: dw: rockchip: Delaying the link training after hot reset"

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This reverts commit ae1af9a1a7fa7214501bde3a35af0fec25b455a3.

Change-Id: Iec1c3c54ea3a33aca1d010bd1c0c36c771da501e
This commit is contained in:
Dongjin Kim
2023-11-06 14:04:39 +09:00
parent fcdb66609c
commit bd1ea209fd
1 changed files with 10 additions and 36 deletions
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46
drivers/pci/controller/dwc/pcie-dw-rockchip.c
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@@ -115,10 +115,6 @@ enum rk_pcie_device_mode {
#define PME_TURN_OFF (BIT(4) | BIT(20))
#define PCIE_CLIENT_GENERAL_DEBUG 0x104
#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
#define PCIE_LTSSM_APP_DLY1_EN BIT(0)
#define PCIE_LTSSM_APP_DLY2_EN BIT(1)
#define PCIE_LTSSM_APP_DLY1_DONE BIT(2)
#define PCIE_LTSSM_APP_DLY2_DONE BIT(3)
#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
#define PCIE_CLIENT_LTSSM_STATUS 0x300
#define SMLH_LINKUP BIT(16)
@@ -141,7 +137,6 @@ enum rk_pcie_device_mode {
#define PCIE_PL_ORDER_RULE_CTRL_OFF 0x8B4
#define RK_PCIE_L2_TMOUT_US 5000
#define RK_PCIE_HOTRESET_TMOUT_US 10000
enum rk_pcie_ltssm_code {
S_L0 = 0x11,
@@ -190,8 +185,6 @@ struct rk_pcie {
u32 l1ss_ctl1;
struct dentry *debugfs;
u32 msi_vector_num;
struct workqueue_struct *hot_rst_wq;
struct work_struct hot_rst_work;
};
struct rk_pcie_of_data {
@@ -1445,37 +1438,13 @@ static void rk_pcie_config_dma_dwc(struct dma_table *table)
table->start.chnl = table->chn;
}
static void rk_pcie_hot_rst_work(struct work_struct *work)
{
struct rk_pcie *rk_pcie = container_of(work, struct rk_pcie, hot_rst_work);
u32 val, status;
int ret;
/* Setup command register */
val = dw_pcie_readl_dbi(rk_pcie->pci, PCI_COMMAND);
val &= 0xffff0000;
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
dw_pcie_writel_dbi(rk_pcie->pci, PCI_COMMAND, val);
if (rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_HOT_RESET_CTRL) & PCIE_LTSSM_APP_DLY2_EN) {
ret = readl_poll_timeout(rk_pcie->apb_base + PCIE_CLIENT_LTSSM_STATUS,
status, ((status & 0x3F) == 0), 100, RK_PCIE_HOTRESET_TMOUT_US);
if (ret)
dev_err(rk_pcie->pci->dev, "wait for detect quiet failed!\n");
rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_HOT_RESET_CTRL,
(PCIE_LTSSM_APP_DLY2_DONE) | ((PCIE_LTSSM_APP_DLY2_DONE) << 16));
}
}
static irqreturn_t rk_pcie_sys_irq_handler(int irq, void *arg)
{
struct rk_pcie *rk_pcie = arg;
u32 chn;
union int_status status;
union int_clear clears;
u32 reg;
u32 reg, val;
status.asdword = dw_pcie_readl_dbi(rk_pcie->pci, PCIE_DMA_OFFSET +
PCIE_DMA_WR_INT_STATUS);
@@ -1516,8 +1485,14 @@ static irqreturn_t rk_pcie_sys_irq_handler(int irq, void *arg)
}
reg = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_INTR_STATUS_MISC);
if (reg & BIT(2))
queue_work(rk_pcie->hot_rst_wq, &rk_pcie->hot_rst_work);
if (reg & BIT(2)) {
/* Setup command register */
val = dw_pcie_readl_dbi(rk_pcie->pci, PCI_COMMAND);
val &= 0xffff0000;
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
dw_pcie_writel_dbi(rk_pcie->pci, PCI_COMMAND, val);
}
rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_STATUS_MISC, reg);
@@ -1641,8 +1616,7 @@ static void rk_pcie_fast_link_setup(struct rk_pcie *rk_pcie)
/* LTSSM EN ctrl mode */
val = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_HOT_RESET_CTRL);
val |= (PCIE_LTSSM_ENABLE_ENHANCE | PCIE_LTSSM_APP_DLY2_EN)
| ((PCIE_LTSSM_APP_DLY2_EN | PCIE_LTSSM_ENABLE_ENHANCE) << 16);
val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16);
rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_HOT_RESET_CTRL, val);
}