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sound: add resample node for axg_s420_v03gva.dts [1/1]

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PD#SWPL-365

Problem:
System can't use resample function on GVA project.

Solution:
Add resample node in axg_s420_v03gva.dts

Verify:
Passed on s420

Change-Id: Ie48c579e9e9f6e1d61147f5410c95e5bca55b0a7
Signed-off-by: riqun.ou <riqun.ou@amlogic.com>
This commit is contained in:
riqun.ou
2018-11-08 15:47:32 +08:00
committed by Jianxin Pan
parent a0490c2ea3
commit bd3ccd7189
3 changed files with 36 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm64/boot/dts/amlogic/axg_s400_v03gva.dts
View File

@@ -854,6 +854,7 @@
unifykey-index-3 = <&keysn_3>;
unifykey-index-4 = <&keysn_4>;
unifykey-index-5 = <&keysn_5>;
unifykey-index-6 = <&keysn_6>;
keysn_0: key_0{
key-name = "usid";
@@ -887,6 +888,11 @@
key-device = "normal";
key-permit = "read","write","del";
};
keysn_6:key_6{
key-name = "gva_certs";
key-device = "normal";
key-permit = "read","write","del";
};
};//End unifykey
audio_data: audio_data {
compatible = "amlogic, audio_data";
@@ -1111,7 +1117,7 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_MPLL2
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1>;
clock-names = "gate",

30
arch/arm64/boot/dts/amlogic/axg_s420_v03gva.dts
View File

@@ -668,13 +668,14 @@
compatible = "amlogic, unifykey";
status = "ok";
unifykey-num = <6>;
unifykey-num = <7>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
unifykey-index-3 = <&keysn_3>;
unifykey-index-4 = <&keysn_4>;
unifykey-index-5 = <&keysn_5>;
unifykey-index-6 = <&keysn_6>;
keysn_0: key_0{
key-name = "usid";
@@ -708,6 +709,11 @@
key-device = "normal";
key-permit = "read","write","del";
};
keysn_6:key_6{
key-name = "gva_certs";
key-device = "normal";
key-permit = "read","write","del";
};
};//End unifykey
audio_data: audio_data {
compatible = "amlogic, audio_data";
@@ -934,7 +940,7 @@
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkc CLKID_MPLL2
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1>;
clock-names = "gate",
@@ -992,6 +998,26 @@
status = "okay";
};
audioresample: resample {
compatible = "amlogic, axg-resample";
clocks = <&clkc CLKID_MPLL3
&clkaudio CLKID_AUDIO_MCLK_F
&clkaudio CLKID_AUDIO_RESAMPLE_CTRL>;
clock-names = "resample_pll", "resample_src", "resample_clk";
/*same with toddr_src
* TDMIN_A,
* TDMIN_B,
* TDMIN_C,
* SPDIFIN,
* PDMIN,
* NONE,
* TDMIN_LB,
* LOOPBACK,
*/
resample_module = <3>;
status = "okay";
};
}; /* end of audiobus */
&pinctrl_periphs {

1
sound/soc/codecs/amlogic/tas5707.c
View File

@@ -185,6 +185,7 @@ static const struct snd_kcontrol_new tas5707_snd_controls[] = {
0xff, 1, chvol_tlv),
SOC_SINGLE("Ch1 Switch", DDX_SOFT_MUTE, 0, 1, 1),
SOC_SINGLE("Ch2 Switch", DDX_SOFT_MUTE, 1, 1, 1),
SOC_SINGLE("Shutdown Switch", DDX_SYS_CTL_2, 6, 1, 1),
SOC_SINGLE_RANGE("Fine Master Volume", DDX_CHANNEL3_VOL, 0,
0x80, 0x83, 0),
SOC_SINGLE_BOOL_EXT("Set EQ Enable", 0,