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arm64: dts: rockchip: rk3588: Add hdptxphy1 node

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Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ie8f483dd86e7279beed2b7e9aa7c00ec2be930e6
This commit is contained in:
Wyon Bi
2021-09-22 15:25:53 +08:00
committed by Tao Huang
parent b41b6ffed6
commit bd4cd9a4c9
1 changed files with 23 additions and 0 deletions
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23
arch/arm64/boot/dts/rockchip/rk3588.dtsi
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@@ -8,6 +8,8 @@
/ {
aliases {
ethernet0 = &gmac0;
hdptx0 = &hdptxphy0;
hdptx1 = &hdptxphy1;
};
usbdrd3_1: usbdrd3_1 {
@@ -75,6 +77,11 @@
};
};
hdptxphy1_grf: syscon@fd5e4000 {
compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
reg = <0x0 0xfd5e4000 0x0 0x80>;
};
spdif_tx5: spdif-tx@fddb8000 {
compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
reg = <0x0 0xfddb8000 0x0 0x1000>;
@@ -399,6 +406,22 @@
status = "disabled";
};
hdptxphy1: phy@fed70000 {
compatible = "rockchip,rk3588-hdptx-phy";
reg = <0x0 0xfed70000 0x0 0x2000>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
clock-names = "ref", "apb";
resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
<&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
<&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>,
<&cru SRST_HDPTX1_LCPLL>;
reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
"lcpll";
rockchip,grf = <&hdptxphy1_grf>;
#phy-cells = <0>;
status = "disabled";
};
usbdp_phy1: phy@fed90000 {
compatible = "rockchip,rk3588-usbdp-phy";
reg = <0x0 0xfed90000 0x0 0x10000>;