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hdmirx: change irq toggle mode [1/1]

Browse Source 
PD#SWPL-5224

Problem:
missing DRM irq.

Solution:
1. modify irq toggle mode.
2. add double check for IP irq bit.

Verify:
T962x2

Change-Id: I6c77e5da92d5f21bc3710d9a6a744c10b1895e71
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
This commit is contained in:
Lei Yang
2019-03-13 15:26:05 +08:00
committed by Luke Go
parent a00cc81039
commit bdedd622cb
5 changed files with 12 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/amlogic/tl1_pxp.dts
View File

@@ -401,7 +401,7 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
interrupts = <0 41 1>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,
<&clkc CLKID_HDMIRX_ACR_COMP>,

2
arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts
View File

@@ -627,7 +627,7 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
interrupts = <0 41 1>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,
<&clkc CLKID_HDMIRX_ACR_COMP>,

2
arch/arm/boot/dts/amlogic/tl1_t962x2_t309.dts
View File

@@ -809,7 +809,7 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
interrupts = <0 41 1>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,
<&clkc CLKID_HDMIRX_ACR_COMP>,

2
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
View File

@@ -34,7 +34,7 @@
#include "hdmi_rx_edid.h"
#define RX_VER0 "ver.2019-01-22"
#define RX_VER0 "ver.2019-03-13"
/*
*
*

8
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
View File

@@ -576,6 +576,14 @@ reisr:hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
if (rx.chip_id != CHIP_ID_TL1) {
if (error == 1)
goto reisr;
} else {
hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
hdmirx_top_intr_stat &= 0x1;
if (hdmirx_top_intr_stat) {
if (log_level & ERR_LOG)
rx_pr("\n irq_miss");
goto reisr;
}
}
/* check the ip interrupt again */
/*hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);