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drm/rockchip: drv: add support soft TE mode to sync with panel ram

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Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I3d0cc0f6f941da61336f47062a8682210234b803
This commit is contained in:
Sandy Huang
2021-12-02 20:09:35 +08:00
committed by Tao Huang
parent d64b8518d2
commit be1e4b616a
2 changed files with 12 additions and 0 deletions
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10
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
View File

@@ -222,6 +222,16 @@ int rockchip_drm_get_sub_dev_type(void)
}
EXPORT_SYMBOL(rockchip_drm_get_sub_dev_type);
void rockchip_drm_te_handle(struct drm_crtc *crtc)
{
struct rockchip_drm_private *priv = crtc->dev->dev_private;
int pipe = drm_crtc_index(crtc);
if (priv->crtc_funcs[pipe] && priv->crtc_funcs[pipe]->te_handler)
priv->crtc_funcs[pipe]->te_handler(crtc);
}
EXPORT_SYMBOL(rockchip_drm_te_handle);
static const struct drm_display_mode rockchip_drm_default_modes[] = {
/* 4 - 1280x720@60Hz 16:9 */
{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,

2
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
View File

@@ -322,6 +322,7 @@ struct rockchip_crtc_funcs {
int output_type);
void (*crtc_close)(struct drm_crtc *crtc);
void (*crtc_send_mcu_cmd)(struct drm_crtc *crtc, u32 type, u32 value);
void (*te_handler)(struct drm_crtc *crtc);
};
struct rockchip_dclk_pll {
@@ -400,6 +401,7 @@ void rockchip_drm_register_sub_dev(struct rockchip_drm_sub_dev *sub_dev);
void rockchip_drm_unregister_sub_dev(struct rockchip_drm_sub_dev *sub_dev);
struct rockchip_drm_sub_dev *rockchip_drm_get_sub_dev(struct device_node *node);
int rockchip_drm_add_modes_noedid(struct drm_connector *connector);
void rockchip_drm_te_handle(struct drm_crtc *crtc);
void drm_mode_convert_to_split_mode(struct drm_display_mode *mode);
void drm_mode_convert_to_origin_mode(struct drm_display_mode *mode);
#if IS_ENABLED(CONFIG_DRM_ROCKCHIP)