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di: merge latest di driver

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PD#154260: di: add latest driver

1) add nr4&cue
2) remove pq releated hard-code
3) add pq load support
4) remove timerc, add hrtimer
5) remove tffbff detection
6) remove extern & global variables
7) move pulldown detection to separate directory
8) update amvecm head file
9) up to commit of PD#154436

Change-Id: I9cde21bb1fd4b4ee08ea88e883ef1c5368ad5b5d
Signed-off-by: kele bai <kele.bai@amlogic.com>
This commit is contained in:
kele bai
2017-11-22 15:00:32 +08:00
committed by Bo Yang
parent 3dba191da3
commit bfebc35f9e
28 changed files with 5423 additions and 3968 deletions
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9
MAINTAINERS
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@@ -13650,9 +13650,12 @@ AMLOGIC VRTC DRIVER
M: Yun Cai <yun.cai@amlogic.com>
F: drivers/amlogic/vrtc/
AMLOGIC DEINTERLACE, DNR, Field Detection, VOF DRIVERS
M: Kele Bai <kele.bai@amlogic.com>
F: drivers/amlogic/deinterlace/*
AMLOGIC DEINTERLACE, NR, CUE, Field Detection, VOF DRIVERS
M: Kele Bai <kele.bai@amlogic.com>
F: drivers/amlogic/deinterlace/*
F: drivers/amlogic/media/deinterlace/film_mode_fmw/*
F: include/linux/amlogic/media/amvecm/amvecm.h
F: arch/arm64/boot/dts/amlogic/txlx_t962e_r321.dts
AMLOGIC TVIN
M: Dezhi Kong <dezhi.kong@amlogic.com>

14
drivers/amlogic/media/deinterlace/Makefile
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@@ -1,19 +1,17 @@
#
# Makefile for the Post Process Manager device
#
# # Makefile for the Post Process Manager device #
ifeq ($(TARGET_BUILD_VARIANT),userdebug)
ccflags-y := -D DEBUG_SUPPORT
endif
CFLAGS_deinterlace.o := -I$(src)
obj-$(CONFIG_AMLOGIC_MEDIA_DEINTERLACE) += film_mode_fmw/
obj-$(CONFIG_AMLOGIC_MEDIA_DEINTERLACE) += di.o
di-objs += deinterlace.o
di-objs += deinterlace_hw.o
di-objs += deinterlace_mtn.o
di-objs += deinterlace_dbg.o
di-objs += nr.o
di-objs += vof_soft_top.o
di-objs += film_fw1.o
di-objs += flm_mod_xx.o
di-objs += nr_drv.o
di-objs += pulldown_drv.o
di-objs += detect3d.o
di-objs += detect3d.o
di-objs += tffbff_check.o
ccflags-y += -Idrivers/amlogic/media/common/rdma/

3436
drivers/amlogic/media/deinterlace/deinterlace.c
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File diff suppressed because it is too large Load Diff

392
drivers/amlogic/media/deinterlace/deinterlace.h
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@@ -20,86 +20,61 @@
#include <linux/cdev.h>
#include <linux/amlogic/media/vfm/vframe.h>
#include <linux/amlogic/media/video_sink/video.h>
#include <linux/clk.h>
#include <linux/atomic.h>
#include "film_vof_soft.h"
/* di hardware version m8m2*/
#define NEW_DI_V1 0x00000002 /* from m6tvc */
#define NEW_DI_V2 0x00000004 /* from m6tvd */
#define NEW_DI_V3 0x00000008 /* from gx */
#define NEW_DI_V4 0x00000010 /* dnr added */
#include "deinterlace_hw.h"
#include "pulldown_drv.h"
#include "nr_drv.h"
/*trigger_pre_di_process param*/
#define TRIGGER_PRE_BY_PUT 'p'
#define TRIGGER_PRE_BY_PUT 'p'
#define TRIGGER_PRE_BY_DE_IRQ 'i'
#define TRIGGER_PRE_BY_UNREG 'u'
/*di_timer_handle*/
#define TRIGGER_PRE_BY_TIMER 't'
#define TRIGGER_PRE_BY_FORCE_UNREG 'f'
#define TRIGGER_PRE_BY_VFRAME_READY 'r'
#define TRIGGER_PRE_BY_TIMER 't'
#define TRIGGER_PRE_BY_FORCE_UNREG 'f'
#define TRIGGER_PRE_BY_VFRAME_READY 'r'
#define TRIGGER_PRE_BY_PROVERDER_UNREG 'n'
#define TRIGGER_PRE_BY_DEBUG_DISABLE 'd'
#define TRIGGER_PRE_BY_TIMERC 'T'
#define TRIGGER_PRE_BY_TIMERC 'T'
#define TRIGGER_PRE_BY_PROVERDER_REG 'R'
#define DI_RUN_FLAG_RUN 0
#define DI_RUN_FLAG_PAUSE 1
#define DI_RUN_FLAG_STEP 2
#define DI_RUN_FLAG_STEP_DONE 3
#define USED_LOCAL_BUF_MAX 3
#define BYPASS_GET_MAX_BUF_NUM 4
/* buffer management related */
#define MAX_IN_BUF_NUM 20
#define MAX_LOCAL_BUF_NUM 12
#define MAX_POST_BUF_NUM 16
#define VFRAME_TYPE_IN 1
#define VFRAME_TYPE_LOCAL 2
#define VFRAME_TYPE_POST 3
#define VFRAME_TYPE_NUM 3
/*vframe define*/
#define vframe_t struct vframe_s
/* canvas defination */
#define DI_USE_FIXED_CANVAS_IDX
#undef USE_LIST
/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
#define NEW_KEEP_LAST_FRAME
/* #endif */
#define DET3D
#undef SUPPORT_MPEG_TO_VDIN /* for all ic after m6c@20140731 */
#undef SUPPORT_MPEG_TO_VDIN
/************************************
* di hardware level interface
*************************************/
#define MAX_WIN_NUM 5
/* if post size < 80, filter of ei can't work */
#define MIN_POST_WIDTH 80
#define MIN_BLEND_WIDTH 27
struct pulldown_detect_info_s {
unsigned int field_diff;
/* total pixels difference between current field and previous field */
unsigned int field_diff_num;
/* the number of pixels with big difference between
* current field and previous field
*/
unsigned int frame_diff;
/*total pixels difference between current field and previouse-previouse field*/
unsigned int frame_diff_num;
/* the number of pixels with big difference between current
* field and previouse-previous field
*/
unsigned int frame_diff_skew;
/* the difference between current frame_diff and previous frame_diff */
unsigned int frame_diff_num_skew;
/* the difference between current frame_diff_num and previous frame_diff_num*/
/* parameters for detection */
unsigned int field_diff_by_pre;
unsigned int field_diff_by_next;
unsigned int field_diff_num_by_pre;
unsigned int field_diff_num_by_next;
unsigned int frame_diff_by_pre;
unsigned int frame_diff_num_by_pre;
unsigned int frame_diff_skew_ratio;
unsigned int frame_diff_num_skew_ratio;
/* matching pattern */
unsigned int field_diff_pattern;
unsigned int field_diff_num_pattern;
unsigned int frame_diff_pattern;
unsigned int frame_diff_num_pattern;
};
#define pulldown_detect_info_t struct pulldown_detect_info_s
#ifndef CONFIG_AMLOGIC_MEDIA_RDMA
#ifndef VSYNC_WR_MPEG_REG
#define VSYNC_WR_MPEG_REG(adr, val) aml_write_vcbus(adr, val)
#define VSYNC_WR_MPEG_REG_BITS(adr, val, start, len) \
aml_vcbus_update_bits(adr, ((1<<len)-1)<<start, val<<start)
#define VSYNC_RD_MPEG_REG(adr) aml_read_vcbus(adr)
#endif
#endif
struct pd_win_prop_s {
unsigned int pixels_num;
};
#define pd_win_prop_t struct pd_win_prop_s
enum process_fun_index_e {
PROCESS_FUN_NULL = 0,
PROCESS_FUN_DI,
@@ -108,14 +83,6 @@ enum process_fun_index_e {
PROCESS_FUN_BOB
};
#define process_fun_index_t enum process_fun_index_e
enum pulldown_mode_e {
PULL_DOWN_BLEND_0 = 0,/* buf1=dup[0] */
PULL_DOWN_BLEND_2 = 1,/* buf1=dup[2] */
PULL_DOWN_MTN = 2,/* mtn only */
PULL_DOWN_BUF1 = 3,/* do wave with dup[0] */
PULL_DOWN_EI = 4,/* ei only */
PULL_DOWN_NORMAL = 5,/* normal di */
};
enum canvas_idx_e {
NR_CANVAS,
@@ -124,9 +91,6 @@ enum canvas_idx_e {
};
#define pulldown_mode_t enum pulldown_mode_e
struct di_buf_s {
#ifdef USE_LIST
struct list_head list;
#endif
struct vframe_s *vframe;
int index; /* index in vframe_in_dup[] or vframe_in[],
* only for type of VFRAME_TYPE_IN
@@ -149,11 +113,8 @@ struct di_buf_s {
int nr_canvas_idx;
unsigned long mtn_adr;
int mtn_canvas_idx;
#ifdef NEW_DI_V1
unsigned long cnt_adr;
int cnt_canvas_idx;
#endif
#ifdef NEW_DI_V3
unsigned long mcinfo_adr;
int mcinfo_canvas_idx;
unsigned long mcvec_adr;
@@ -163,20 +124,9 @@ struct di_buf_s {
unsigned int motionparadoxflg;
unsigned int regs[26];/* reg 0x2fb0~0x2fc9 */
} curr_field_mcinfo;
#endif
/* blend window */
unsigned short reg0_s;
unsigned short reg0_e;
unsigned short reg0_bmode;
unsigned short reg1_s;
unsigned short reg1_e;
unsigned short reg1_bmode;
unsigned short reg2_s;
unsigned short reg2_e;
unsigned short reg2_bmode;
unsigned short reg3_s;
unsigned short reg3_e;
unsigned short reg3_bmode;
struct pulldown_detected_s
pd_config;
/* tff bff check result bit[1:0]*/
unsigned int privated;
unsigned int canvas_config_flag;
@@ -185,10 +135,6 @@ struct di_buf_s {
*/
unsigned int canvas_height;
unsigned int canvas_width[3];/* nr/mtn/mv */
/*bit [31~16] width; bit [15~0] height*/
pulldown_detect_info_t field_pd_info;
pulldown_detect_info_t win_pd_info[MAX_WIN_NUM];
pulldown_mode_t pulldown_mode;
process_fun_index_t process_fun_index;
int early_process_fun_index;
int left_right;/*1,left eye; 0,right eye in field alternative*/
@@ -202,169 +148,16 @@ struct di_buf_s {
* 0: after put
*/
atomic_t di_cnt;
struct page *pages;
};
#ifdef DET3D
extern bool det3d_en;
#endif
extern uint mtn_ctrl1;
extern pd_win_prop_t pd_win_prop[MAX_WIN_NUM];
extern int pd_enable;
extern void di_hw_init(void);
extern void di_hw_uninit(void);
extern void enable_di_pre_mif(int enable);
extern int di_vscale_skip_count;
extern unsigned int di_force_bit_mode;
/*
* di hardware internal
*/
#define RDMA_DET3D_IRQ 0x20
/* vdin0 rdma irq */
#define RDMA_DEINT_IRQ 0x2
#define RDMA_TABLE_SIZE ((PAGE_SIZE)<<1)
#define RDMA_TABLE_SIZE ((PAGE_SIZE)<<1)
#if defined(CONFIG_AM_DEINTERLACE_SD_ONLY)
#define MAX_CANVAS_WIDTH 720
#define MAX_CANVAS_HEIGHT 576
#else
#define MAX_CANVAS_WIDTH 1920
#define MAX_CANVAS_HEIGHT 1088
#endif
struct DI_MIF_s {
unsigned short luma_x_start0;
unsigned short luma_x_end0;
unsigned short luma_y_start0;
unsigned short luma_y_end0;
unsigned short chroma_x_start0;
unsigned short chroma_x_end0;
unsigned short chroma_y_start0;
unsigned short chroma_y_end0;
unsigned set_separate_en:2;
unsigned src_field_mode:1;
unsigned src_prog:1;
unsigned video_mode:1;
unsigned output_field_num:1;
unsigned bit_mode:2;
/*
* unsigned burst_size_y:2; set 3 as default
* unsigned burst_size_cb:2;set 1 as default
* unsigned burst_size_cr:2;set 1 as default
*/
unsigned canvas0_addr0:8;
unsigned canvas0_addr1:8;
unsigned canvas0_addr2:8;
};
struct DI_SIM_MIF_s {
unsigned short start_x;
unsigned short end_x;
unsigned short start_y;
unsigned short end_y;
unsigned short canvas_num;
unsigned short bit_mode;
};
struct DI_MC_MIF_s {
unsigned short start_x;
unsigned short start_y;
unsigned short size_x;
unsigned short size_y;
unsigned short canvas_num;
unsigned short blend_mode;
unsigned short vecrd_offset;
};
void disable_deinterlace(void);
void disable_pre_deinterlace(void);
void disable_post_deinterlace(void);
int get_di_pre_recycle_buf(void);
void disable_post_deinterlace_2(void);
void enable_film_mode_check(unsigned int width, unsigned int height,
enum vframe_source_type_e);
void enable_di_pre_aml(
struct DI_MIF_s *di_inp_mif,
struct DI_MIF_s *di_mem_mif,
struct DI_MIF_s *di_chan2_mif,
struct DI_SIM_MIF_s *di_nrwr_mif,
struct DI_SIM_MIF_s *di_mtnwr_mif,
#ifdef NEW_DI_V1
struct DI_SIM_MIF_s *di_contp2rd_mif,
struct DI_SIM_MIF_s *di_contprd_mif,
struct DI_SIM_MIF_s *di_contwr_mif,
#endif
int nr_en, int mtn_en, int pd32_check_en, int pd22_check_en,
int hist_check_en, int pre_field_num, int pre_vdin_link,
int hold_line, int urgent);
void enable_afbc_input(struct vframe_s *vf);
#ifdef NEW_DI_V3
void enable_mc_di_pre(struct DI_MC_MIF_s *di_mcinford_mif,
struct DI_MC_MIF_s *di_mcinfowr_mif,
struct DI_MC_MIF_s *di_mcvecwr_mif, int urgent);
void enable_mc_di_post(struct DI_MC_MIF_s *di_mcvecrd_mif,
int urgent, bool reverse);
#endif
void read_new_pulldown_info(struct FlmModReg_t *pFMRegp);
void initial_di_pre_aml(int hsize_pre, int vsize_pre, int hold_line);
void initial_di_post_2(int hsize_post, int vsize_post, int hold_line);
void enable_di_post_2(
struct DI_MIF_s *di_buf0_mif,
struct DI_MIF_s *di_buf1_mif,
struct DI_MIF_s *di_buf2_mif,
struct DI_SIM_MIF_s *di_diwr_mif,
#ifndef NEW_DI_V2
struct DI_SIM_MIF_s *di_mtncrd_mif,
#endif
struct DI_SIM_MIF_s *di_mtnprd_mif,
int ei_en, int blend_en, int blend_mtn_en, int blend_mode,
int di_vpp_en, int di_ddr_en,
int post_field_num, int hold_line, int urgent
#ifndef NEW_DI_V1
, unsigned long *reg_mtn_info
#endif
);
void di_post_switch_buffer(
struct DI_MIF_s *di_buf0_mif,
struct DI_MIF_s *di_buf1_mif,
struct DI_MIF_s *di_buf2_mif,
struct DI_SIM_MIF_s *di_diwr_mif,
#ifndef NEW_DI_V2
struct DI_SIM_MIF_s *di_mtncrd_mif,
#endif
struct DI_SIM_MIF_s *di_mtnprd_mif,
struct DI_MC_MIF_s *di_mcvecrd_mif,
int ei_en, int blend_en, int blend_mtn_en, int blend_mode,
int di_vpp_en, int di_ddr_en,
int post_field_num, int hold_line, int urgent
#ifndef NEW_DI_V1
, unsigned long *reg_mtn_info
#endif
);
bool read_pulldown_info(pulldown_detect_info_t *field_pd_info,
pulldown_detect_info_t *win_pd_info);
/* for video reverse */
void di_post_read_reverse(bool reverse);
void di_post_read_reverse_irq(bool reverse);
extern void recycle_keep_buffer(void);
/* #define DI_BUFFER_DEBUG */
@@ -376,42 +169,8 @@ extern void recycle_keep_buffer(void);
#define DI_LOG_QUEUE 0x40
#define DI_LOG_VFRAME 0x80
extern unsigned int di_log_flag;
extern unsigned int di_debug_flag;
extern bool mcpre_en;
extern bool dnr_reg_update;
extern bool dnr_dm_en;
extern int mpeg2vdin_flag;
extern int di_vscale_skip_count_real;
extern unsigned int pulldown_enable;
extern bool post_wr_en;
extern unsigned int post_wr_surpport;
extern int cmb_adpset_cnt;
extern unsigned int field_diff_rate;
int di_print(const char *fmt, ...);
int get_current_vscale_skip_count(struct vframe_s *vf);
void di_set_power_control(unsigned char type, unsigned char enable);
void diwr_set_power_control(unsigned char enable);
unsigned char di_get_power_control(unsigned char type);
void config_di_bit_mode(vframe_t *vframe, unsigned int bypass_flag);
void combing_pd22_window_config(unsigned int width, unsigned int height);
int tff_bff_check(int height, int width);
void tbff_init(void);
void DI_Wr(unsigned int addr, unsigned int val);
void DI_Wr_reg_bits(unsigned int adr, unsigned int val,
unsigned int start, unsigned int len);
void DI_VSYNC_WR_MPEG_REG(unsigned int addr, unsigned int val);
void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr, unsigned int val,
unsigned int start, unsigned int len);
#ifdef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
extern void enable_rdma(int enable_flag);
extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val);
@@ -430,30 +189,37 @@ extern bool is_vsync_rdma_enable(void);
#define DI_COUNT 1
#define DI_MAP_FLAG 0x1
#define DI_SUSPEND_FLAG 0x2
#define DI_LOAD_REG_FLAG 0x4
struct di_dev_s {
dev_t devt;
struct cdev cdev; /* The cdev structure */
struct device *dev;
struct platform_device *pdev;
struct task_struct *task;
struct clk *vpu_clkb;
unsigned long clkb_max_rate;
unsigned long clkb_min_rate;
struct list_head pq_table_list;
struct mutex pq_lock;
unsigned char di_event;
unsigned int di_irq;
unsigned int flags;
unsigned int timerc_irq;
unsigned long jiffy;
unsigned long mem_start;
unsigned int mem_size;
unsigned int buffer_size;
unsigned int post_buffer_size;
unsigned int buf_num_avail;
unsigned int hw_version;
int rdma_handle;
/* is surpport nr10bit */
unsigned int nr10bit_surpport;
/* is DI surpport post wr to mem for OMX */
unsigned int post_wr_surpport;
/* is support nr10bit */
unsigned int nr10bit_support;
/* is DI support post wr to mem for OMX */
unsigned int post_wr_support;
struct mutex cma_mutex;
unsigned int flag_cma;
unsigned int cma_alloc[10];
unsigned int buffer_addr[10];
struct page *pages[10];
struct page *total_pages;
atomic_t mem_flag;
};
struct di_pre_stru_s {
@@ -471,7 +237,6 @@ struct di_pre_stru_s {
struct DI_SIM_MIF_s di_mtnwr_mif;
struct di_buf_s *di_wr_buf;
struct di_buf_s *di_post_wr_buf;
#ifdef NEW_DI_V1
struct DI_SIM_MIF_s di_contp2rd_mif;
struct DI_SIM_MIF_s di_contprd_mif;
struct DI_SIM_MIF_s di_contwr_mif;
@@ -482,7 +247,6 @@ struct di_pre_stru_s {
* 2 (f2,nr1_cnt,nr0)->nr2_cnt
* 3 (f3,nr2_cnt,nr1_cnt)->nr3_cnt
*/
#endif
struct DI_MC_MIF_s di_mcinford_mif;
struct DI_MC_MIF_s di_mcvecwr_mif;
struct DI_MC_MIF_s di_mcinfowr_mif;
@@ -498,8 +262,10 @@ struct di_pre_stru_s {
/* flag is set when VFRAME_EVENT_PROVIDER_UNREG*/
int unreg_req_flag;
int unreg_req_flag_irq;
int unreg_req_flag_cnt;
int reg_req_flag;
int reg_req_flag_irq;
int reg_req_flag_cnt;
int force_unreg_req_flag;
int disable_req_flag;
/* current source info */
@@ -512,23 +278,23 @@ struct di_pre_stru_s {
int cur_prog_flag; /* 1 for progressive source */
/* valid only when prog_proc_type is 0, for
* progressive source: top field 1, bot field 0
*/
*/
int source_change_flag;
/* input size change flag, 1: need reconfig pre/nr/dnr size */
/* 0: not need config pre/nr/dnr size*/
bool input_size_change_flag;
/* true: bypass di all logic, false: not bypass */
bool bypass_flag;
unsigned char prog_proc_type;
/* set by prog_proc_config when source is vdin,0:use 2 i
* serial buffer,1:use 1 p buffer,3:use 2 i paralleling buffer
*/
*/
unsigned char buf_alloc_mode;
/* alloc di buf as p or i;0: alloc buf as i;
* 1: alloc buf as p;
*/
*/
unsigned char enable_mtnwr;
unsigned char enable_pulldown_check;
int same_field_source_flag;
int left_right;/*1,left eye; 0,right eye in field alternative*/
/*input2pre*/
int bypass_start_count;
@@ -540,16 +306,20 @@ struct di_pre_stru_s {
unsigned int det_tp;
unsigned int det_la;
unsigned int det_null;
unsigned int width_bk;
#ifdef DET3D
int vframe_interleave_flag;
#endif
/**/
int pre_de_irq_timeout_count;
int pre_throw_flag;
int bad_frame_throw_count;
/*for static pic*/
int static_frame_count;
bool force_interlace;
bool bypass_pre;
bool invert_flag;
bool vdin_source;
int nr_size;
int count_size;
int mcinfo_size;
@@ -558,6 +328,10 @@ struct di_pre_stru_s {
int cma_alloc_req;
int cma_alloc_done;
int cma_release_req;
/* for performance debug */
unsigned long irq_time;
/* combing adaptive */
struct combing_status_s *mtn_status;
};
struct di_post_stru_s {
@@ -568,8 +342,8 @@ struct di_post_stru_s {
struct DI_SIM_MIF_s di_mtnprd_mif;
struct DI_MC_MIF_s di_mcvecrd_mif;
struct di_buf_s *cur_post_buf;
struct di_buf_s *keep_buf;
int update_post_reg_flag;
int post_process_fun_index;
int run_early_proc_fun_flag;
int cur_disp_index;
int canvas_id;
@@ -581,17 +355,27 @@ struct di_post_stru_s {
int de_post_process_done;
int post_de_busy;
int di_post_num;
unsigned int di_post_process_cnt;
unsigned int check_recycle_buf_cnt;
/* performance debug */
unsigned int post_wr_cnt;
unsigned long irq_time;
};
#define MAX_QUEUE_POOL_SIZE 256
struct queue_s {
int num;
int in_idx;
int out_idx;
int type; /* 0, first in first out;
unsigned int num;
unsigned int in_idx;
unsigned int out_idx;
unsigned int type; /* 0, first in first out;
* 1, general;2, fix position for di buf
*/
unsigned int pool[MAX_QUEUE_POOL_SIZE];
unsigned int pool[MAX_QUEUE_POOL_SIZE];
};
struct di_buf_pool_s {
struct di_buf_s *di_buf_ptr;
unsigned int size;
};
#define di_dev_t struct di_dev_s

243
drivers/amlogic/media/deinterlace/deinterlace_dbg.c
View File

@@ -56,55 +56,119 @@ void parse_cmd_params(char *buf_orig, char **parm)
void dump_di_reg(void)
{
unsigned int i = 0;
unsigned int i = 0, base_addr = 0;
unsigned int size_reg_addr[57] = {
0x1702, 0x1703, 0x2d01,
0x2d01, 0x2d8f, 0x2d08,
0x2d09, 0x2f00, 0x2f01,
0x17d0, 0x17d1, 0x17d2,
0x17d3, 0x17dd, 0x17de,
0x17df, 0x17e0, 0x17f7,
0x17f8, 0x17f9, 0x17fa,
0x17c0, 0x17c1, 0x17a0,
0x17a1, 0x17c3, 0x17c4,
0x17cb, 0x17cc, 0x17a3,
0x17a4, 0x17a5, 0x17a6,
0x2f92, 0x2f93, 0x2f95,
0x2f96, 0x2f98, 0x2f99,
0x2f9b, 0x2f9c, 0x2f65,
0x2f66, 0x2f67, 0x2f68,
0x1a53, 0x1a54, 0x1a55,
0x1a56, 0x17ea, 0x17eb,
0x17ec, 0x17ed, 0x2012,
0x2013, 0x2014, 0x2015
};
if (is_meson_txlx_cpu() || is_meson_txhd_cpu())
base_addr = 0xff900000;
else
base_addr = 0xd0100000;
pr_info("----dump di reg----\n");
for (i = 0; i < 255; i++) {
if (i == 0x45)
pr_info("----nr reg----");
if (i == 0x80)
pr_info("----3d reg----");
if (i == 0x9e)
pr_info("---nr reg done---");
if (i == 0x9c)
pr_info("---3d reg done---");
pr_info("[0x%x][0x%x]=0x%x\n",
0xd0100000 + ((0x1700 + i) << 2),
0x1700 + i, RDMA_RD(0x1700 + i));
}
pr_info("----dump mcdi reg----\n");
for (i = 0; i < 201; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
0xd0100000 + ((0x2f00 + i) << 2),
0x2f00 + i, RDMA_RD(0x2f00 + i));
pr_info("----dump pulldown reg----\n");
for (i = 0; i < 26; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
0xd0100000 + ((0x2fd0 + i) << 2),
0x2fd0 + i, RDMA_RD(0x2fd0 + i));
pr_info("----dump bit mode reg----\n");
for (i = 0; i < 4; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
0xd0100000 + ((0x20a7 + i) << 2),
0x20a7 + i, RDMA_RD(0x20a7 + i));
pr_info("----dump di reg----\n");
pr_info("----dump size reg---");
for (i = 0; i < 57; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
0xd0100000 + (0x2022 << 2),
0x2022, RDMA_RD(0x2022));
base_addr + ((size_reg_addr[i]) << 2),
size_reg_addr[i], RDMA_RD(size_reg_addr[i]));
for (i = 0; i < 255; i++) {
if (i == 0x45)
pr_info("----nr reg----");
if (i == 0x80)
pr_info("----3d reg----");
if (i == 0x9e)
pr_info("---nr reg done---");
if (i == 0x9c)
pr_info("---3d reg done---");
pr_info("[0x%x][0x%x]=0x%x\n",
0xd0100000 + (0x17c1 << 2),
0x17c1, RDMA_RD(0x17c1));
base_addr + ((0x1700 + i) << 2),
0x1700 + i, RDMA_RD(0x1700 + i));
}
pr_info("----dump mcdi reg----\n");
for (i = 0; i < 201; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
0xd0100000 + (0x17c2 << 2),
0x17c2, RDMA_RD(0x17c2));
base_addr + ((0x2f00 + i) << 2),
0x2f00 + i, RDMA_RD(0x2f00 + i));
pr_info("----dump pulldown reg----\n");
for (i = 0; i < 26; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
0xd0100000 + (0x1aa7 << 2),
0x1aa7, RDMA_RD(0x1aa7));
pr_info("----dump dnr reg----\n");
for (i = 0; i < 29; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
0xd0100000 + ((0x2d00 + i) << 2),
0x2d00 + i, RDMA_RD(0x2d00 + i));
pr_info("----dump reg done----\n");
base_addr + ((0x2fd0 + i) << 2),
0x2fd0 + i, RDMA_RD(0x2fd0 + i));
pr_info("----dump bit mode reg----\n");
for (i = 0; i < 4; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x20a7 + i) << 2),
0x20a7 + i, RDMA_RD(0x20a7 + i));
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + (0x2022 << 2),
0x2022, RDMA_RD(0x2022));
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + (0x17c1 << 2),
0x17c1, RDMA_RD(0x17c1));
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + (0x17c2 << 2),
0x17c2, RDMA_RD(0x17c2));
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + (0x1aa7 << 2),
0x1aa7, RDMA_RD(0x1aa7));
pr_info("----dump dnr reg----\n");
for (i = 0; i < 29; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x2d00 + i) << 2),
0x2d00 + i, RDMA_RD(0x2d00 + i));
pr_info("----dump if0 reg----\n");
for (i = 0; i < 26; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x1a60 + i) << 2),
0x1a50 + i, RDMA_RD(0x1a50 + i));
pr_info("----dump gate reg----\n");
pr_info("[0x%x][0x1718]=0x%x\n",
base_addr + ((0x1718) << 2),
RDMA_RD(0x1718));
for (i = 0; i < 5; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x2006 + i) << 2),
0x2006 + i, RDMA_RD(0x2006 + i));
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x2dff) << 2),
0x2dff, RDMA_RD(0x2dff));
pr_info("----dump if2 reg----\n");
for (i = 0; i < 29; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x2010 + i) << 2),
0x2010 + i, RDMA_RD(0x2010 + i));
pr_info("----dump nr4 reg----\n");
for (i = 0x2da4; i < 0x2df6; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + (i << 2),
i, RDMA_RD(i));
for (i = 0x3700; i < 0x373f; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + (i << 2),
i, RDMA_RD(i));
for (i = 0; i < 57; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((size_reg_addr[i]) << 2),
size_reg_addr[i], RDMA_RD(size_reg_addr[i]));
pr_info("----dump reg done----\n");
}
void dump_di_pre_stru(struct di_pre_stru_s *di_pre_stru_p)
@@ -154,8 +218,6 @@ void dump_di_pre_stru(struct di_pre_stru_s *di_pre_stru_p)
di_pre_stru_p->enable_mtnwr);
pr_info("enable_pulldown_check = %d\n",
di_pre_stru_p->enable_pulldown_check);
pr_info("same_field_source_flag = %d\n",
di_pre_stru_p->same_field_source_flag);
#ifdef DET3D
pr_info("vframe_interleave_flag = %d\n",
di_pre_stru_p->vframe_interleave_flag);
@@ -197,7 +259,7 @@ void dump_di_buf(struct di_buf_s *di_buf)
di_buf->seq, di_buf->pre_ref_count, di_buf->post_ref_count,
di_buf->queue_index);
pr_info("pulldown_mode %d process_fun_index %d\n",
di_buf->pulldown_mode, di_buf->process_fun_index);
di_buf->pd_config.global_mode, di_buf->process_fun_index);
pr_info("di_buf: %p, %p, di_buf_dup_p: %p, %p, %p, %p, %p\n",
di_buf->di_buf[0], di_buf->di_buf[1], di_buf->di_buf_dup_p[0],
di_buf->di_buf_dup_p[1], di_buf->di_buf_dup_p[2],
@@ -292,4 +354,91 @@ void print_di_buf(struct di_buf_s *di_buf, int format)
}
}
}
void dump_pre_mif_state(void)
{
unsigned int i = 0;
Wr_reg_bits(DI_INP_GEN_REG3, 3, 10, 2);
Wr_reg_bits(DI_MEM_GEN_REG3, 3, 10, 2);
Wr_reg_bits(DI_CHAN2_GEN_REG3, 3, 10, 2);
pr_info("DI_INP_GEN_REG2=0x%x.\n", Rd(DI_INP_GEN_REG2));
pr_info("DI_INP_GEN_REG3=0x%x.\n", Rd(DI_INP_GEN_REG3));
pr_info("DI_INP_LUMA_FIFO_SIZE=0x%x.\n", Rd(DI_INP_LUMA_FIFO_SIZE));
pr_info("DI_INP_RANGE_MAP_Y=0x%x.\n", Rd(DI_INP_RANGE_MAP_Y));
pr_info("DI_INP_RANGE_MAP_CB=0x%x.\n", Rd(DI_INP_RANGE_MAP_CB));
pr_info("DI_INP_RANGE_MAP_CR=0x%x.\n", Rd(DI_INP_RANGE_MAP_CR));
pr_info("DI_INP_URGENT_CTRL=0x%x.\n", Rd(DI_INP_URGENT_CTRL));
for (i = 0; i < 10; i++)
pr_info("0x%x=0x%x.\n", 0x17ce + i, Rd(0x17ce + i));
pr_info("DI_MEM_GEN_REG2=0x%x.\n", Rd(DI_MEM_GEN_REG2));
pr_info("DI_MEM_GEN_REG3=0x%x.\n", Rd(DI_MEM_GEN_REG3));
pr_info("DI_MEM_LUMA_FIFO_SIZE=0x%x.\n", Rd(DI_MEM_LUMA_FIFO_SIZE));
pr_info("DI_MEM_RANGE_MAP_CB=0x%x.\n", Rd(DI_MEM_RANGE_MAP_CB));
pr_info("DI_MEM_RANGE_MAP_CR=0x%x.\n", Rd(DI_MEM_RANGE_MAP_CR));
pr_info("DI_MEM_URGENT_CTRL=0x%x.\n", Rd(DI_MEM_URGENT_CTRL));
for (i = 0; i < 10; i++)
pr_info("0x%x=0x%x.\n", 0x17db + i, Rd(0x17db + i));
pr_info("DI_CHAN2_GEN_REG2=0x%x.\n", Rd(DI_CHAN2_GEN_REG2));
pr_info("DI_CHAN2_GEN_REG3=0x%x.\n", Rd(DI_CHAN2_GEN_REG3));
pr_info("DI_CHAN2_LUMA_FIFO_SIZE=0x%x.\n", Rd(DI_CHAN2_LUMA_FIFO_SIZE));
pr_info("DI_CHAN2_RANGE_MAP_CB=0x%x.\n", Rd(DI_CHAN2_RANGE_MAP_CB));
pr_info("DI_CHAN2_RANGE_MAP_CR=0x%x.\n", Rd(DI_CHAN2_RANGE_MAP_CR));
pr_info("DI_CHAN2_URGENT_CTRL=0x%x.\n", Rd(DI_CHAN2_URGENT_CTRL));
for (i = 0; i < 10; i++)
pr_info("0x%x=0x%x.\n", 0x17f5 + i, Rd(0x17f5 + i));
}
void dump_post_mif_reg(void)
{
pr_info("VIU_MISC_CTRL0=0x%x\n", Rd(VIU_MISC_CTRL0));
pr_info("VD1_IF0_GEN_REG=0x%x\n", Rd(VD1_IF0_GEN_REG));
pr_info("VD1_IF0_GEN_REG2=0x%x\n", Rd(VD1_IF0_GEN_REG2));
pr_info("VD1_IF0_GEN_REG3=0x%x\n", Rd(VD1_IF0_GEN_REG3));
pr_info("VD1_IF0_LUMA_X0=0x%x\n", Rd(VD1_IF0_LUMA_X0));
pr_info("VD1_IF0_LUMA_Y0=0x%x\n", Rd(VD1_IF0_LUMA_Y0));
pr_info("VD1_IF0_CHROMA_X0=0x%x\n", Rd(VD1_IF0_CHROMA_X0));
pr_info("VD1_IF0_CHROMA_Y0=0x%x\n", Rd(VD1_IF0_CHROMA_Y0));
pr_info("VD1_IF0_LUMA_X1=0x%x\n", Rd(VD1_IF0_LUMA_X1));
pr_info("VD1_IF0_LUMA_Y1=0x%x\n", Rd(VD1_IF0_LUMA_Y1));
pr_info("VD1_IF0_CHROMA_X1=0x%x\n", Rd(VD1_IF0_CHROMA_X1));
pr_info("VD1_IF0_CHROMA_Y1=0x%x\n", Rd(VD1_IF0_CHROMA_Y1));
pr_info("VD1_IF0_REPEAT_LOOP=0x%x\n", Rd(VD1_IF0_RPT_LOOP));
pr_info("VD1_IF0_LUMA0_RPT_PAT=0x%x\n", Rd(VD1_IF0_LUMA0_RPT_PAT));
pr_info("VD1_IF0_CHROMA0_RPT_PAT=0x%x\n", Rd(VD1_IF0_CHROMA0_RPT_PAT));
pr_info("VD1_IF0_LUMA_PSEL=0x%x\n", Rd(VD1_IF0_LUMA_PSEL));
pr_info("VD1_IF0_CHROMA_PSEL=0x%x\n", Rd(VD1_IF0_CHROMA_PSEL));
pr_info("VIU_VD1_FMT_CTRL=0x%x\n", Rd(VIU_VD1_FMT_CTRL));
pr_info("VIU_VD1_FMT_W=0x%x\n", Rd(VIU_VD1_FMT_W));
pr_info("DI_IF1_GEN_REG=0x%x\n", Rd(DI_IF1_GEN_REG));
pr_info("DI_IF1_GEN_REG2=0x%x\n", Rd(DI_IF1_GEN_REG2));
pr_info("DI_IF1_GEN_REG3=0x%x\n", Rd(DI_IF1_GEN_REG3));
pr_info("DI_IF1_CANVAS0=0x%x\n", Rd(DI_IF1_CANVAS0));
pr_info("DI_IF1_LUMA_X0=0x%x\n", Rd(DI_IF1_LUMA_X0));
pr_info("DI_IF1_LUMA_Y0=0x%x\n", Rd(DI_IF1_LUMA_Y0));
pr_info("DI_IF1_CHROMA_X0=0x%x\n", Rd(DI_IF1_CHROMA_X0));
pr_info("DI_IF1_CHROMA_Y0=0x%x\n", Rd(DI_IF1_CHROMA_Y0));
pr_info("DI_IF1_LUMA0_RPT_PAT=0x%x\n", Rd(DI_IF1_LUMA0_RPT_PAT));
pr_info("DI_IF1_CHROMA0_RPT_PAT=0x%x\n", Rd(DI_IF1_LUMA0_RPT_PAT));
pr_info("DI_IF1_FMT_CTRL=0x%x\n", Rd(DI_IF1_FMT_CTRL));
pr_info("DI_IF1_FMT_W=0x%x\n", Rd(DI_IF1_FMT_W));
pr_info("DI_IF2_GEN_REG=0x%x\n", Rd(DI_IF2_GEN_REG));
pr_info("DI_IF2_GEN_REG2=0x%x\n", Rd(DI_IF2_GEN_REG2));
pr_info("DI_IF2_GEN_REG3=0x%x\n", Rd(DI_IF2_GEN_REG3));
pr_info("DI_IF2_CANVAS0=0x%x\n", Rd(DI_IF2_CANVAS0));
pr_info("DI_IF2_LUMA_X0=0x%x\n", Rd(DI_IF2_LUMA_X0));
pr_info("DI_IF2_LUMA_Y0=0x%x\n", Rd(DI_IF2_LUMA_Y0));
pr_info("DI_IF2_CHROMA_X0=0x%x\n", Rd(DI_IF2_CHROMA_X0));
pr_info("DI_IF2_CHROMA_Y0=0x%x\n", Rd(DI_IF2_CHROMA_Y0));
pr_info("DI_IF2_LUMA0_RPT_PAT=0x%x\n", Rd(DI_IF2_LUMA0_RPT_PAT));
pr_info("DI_IF2_CHROMA0_RPT_PAT=0x%x\n", Rd(DI_IF2_LUMA0_RPT_PAT));
pr_info("DI_IF2_FMT_CTRL=0x%x\n", Rd(DI_IF2_FMT_CTRL));
pr_info("DI_IF2_FMT_W=0x%x\n", Rd(DI_IF2_FMT_W));
pr_info("DI_DIWR_Y=0x%x\n", Rd(DI_DIWR_Y));
pr_info("DI_DIWR_CTRL=0x%x", Rd(DI_DIWR_CTRL));
pr_info("DI_DIWR_X=0x%x.\n", Rd(DI_DIWR_X));
}

10
drivers/amlogic/media/deinterlace/deinterlace_dbg.h
View File

@@ -14,8 +14,8 @@
* more details.
*
*/
#include <linux/amlogic/media/vfm/vframe.h>
#ifndef _DI_DBG_H
#define _DI_DBG_H
#include "deinterlace.h"
void parse_cmd_params(char *buf_orig, char **parm);
@@ -26,4 +26,8 @@ void dump_pool(struct queue_s *q);
void dump_vframe(vframe_t *vf);
void dump_di_reg(void);
void print_di_buf(struct di_buf_s *di_buf, int format);
void dump_pre_mif_state(void);
void dump_post_mif_reg(void);
void debug_device_files_add(struct device *dev);
void debug_device_files_del(struct device *dev);
#endif

1189
drivers/amlogic/media/deinterlace/deinterlace_hw.c
View File

File diff suppressed because it is too large Load Diff

165
drivers/amlogic/media/deinterlace/deinterlace_hw.h Normal file
View File

@@ -0,0 +1,165 @@
/*
* drivers/amlogic/media/deinterlace/deinterlace_hw.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef _DI_HW_H
#define _DI_HW_H
#include <linux/amlogic/media/amvecm/amvecm.h>
#include "pulldown_drv.h"
#include "nr_drv.h"
#include "deinterlace_hw.h"
/* if post size < 80, filter of ei can't work */
#define MIN_POST_WIDTH 80
#define MIN_BLEND_WIDTH 27
struct DI_MIF_s {
unsigned short luma_x_start0;
unsigned short luma_x_end0;
unsigned short luma_y_start0;
unsigned short luma_y_end0;
unsigned short chroma_x_start0;
unsigned short chroma_x_end0;
unsigned short chroma_y_start0;
unsigned short chroma_y_end0;
unsigned set_separate_en:2;
unsigned src_field_mode:1;
unsigned src_prog:1;
unsigned video_mode:1;
unsigned output_field_num:1;
unsigned bit_mode:2;
/*
* unsigned burst_size_y:2; set 3 as default
* unsigned burst_size_cb:2;set 1 as default
* unsigned burst_size_cr:2;set 1 as default
*/
unsigned canvas0_addr0:8;
unsigned canvas0_addr1:8;
unsigned canvas0_addr2:8;
};
struct DI_SIM_MIF_s {
unsigned short start_x;
unsigned short end_x;
unsigned short start_y;
unsigned short end_y;
unsigned short canvas_num;
unsigned short bit_mode;
};
struct DI_MC_MIF_s {
unsigned short start_x;
unsigned short start_y;
unsigned short end_y;
unsigned short size_x;
unsigned short size_y;
unsigned short canvas_num;
unsigned short blend_en;
unsigned short vecrd_offset;
};
enum gate_mode_e {
GATE_AUTO,
GATE_ON,
GATE_OFF,
};
struct mcinfo_lmv_s {
unsigned char lock_flag;
char lmv;
unsigned short lock_cnt;
};
struct di_pq_parm_s {
struct am_pq_parm_s pq_parm;
struct am_reg_s *regs;
struct list_head list;
};
void read_pulldown_info(unsigned int *glb_frm_mot_num,
unsigned int *glb_fid_mot_num);
void read_new_pulldown_info(struct FlmModReg_t *pFMRegp);
void combing_pd22_window_config(unsigned int width, unsigned int height);
void di_hw_init(bool pulldown_en, bool mc_enable);
void di_hw_uninit(void);
void enable_di_pre_aml(
struct DI_MIF_s *di_inp_mif,
struct DI_MIF_s *di_mem_mif,
struct DI_MIF_s *di_chan2_mif,
struct DI_SIM_MIF_s *di_nrwr_mif,
struct DI_SIM_MIF_s *di_mtnwr_mif,
struct DI_SIM_MIF_s *di_contp2rd_mif,
struct DI_SIM_MIF_s *di_contprd_mif,
struct DI_SIM_MIF_s *di_contwr_mif,
int nr_en, int mtn_en, int pd32_check_en, int pd22_check_en,
int hist_check_en, int pre_field_num, int pre_vdin_link,
int hold_line, int urgent);
void enable_afbc_input(struct vframe_s *vf);
void mc_pre_mv_irq(void);
void enable_mc_di_pre(struct DI_MC_MIF_s *di_mcinford_mif,
struct DI_MC_MIF_s *di_mcinfowr_mif,
struct DI_MC_MIF_s *di_mcvecwr_mif, int urgent);
void enable_mc_di_post(struct DI_MC_MIF_s *di_mcvecrd_mif,
int urgent, bool reverse, int invert_mv);
void disable_post_deinterlace_2(void);
void initial_di_post_2(int hsize_post, int vsize_post,
int hold_line, bool write_en);
void enable_di_post_2(
struct DI_MIF_s *di_buf0_mif,
struct DI_MIF_s *di_buf1_mif,
struct DI_MIF_s *di_buf2_mif,
struct DI_SIM_MIF_s *di_diwr_mif,
struct DI_SIM_MIF_s *di_mtnprd_mif,
int ei_en, int blend_en, int blend_mtn_en, int blend_mode,
int di_vpp_en, int di_ddr_en,
int post_field_num, int hold_line, int urgent,
int invert_mv, int vskip_cnt
);
void di_post_switch_buffer(
struct DI_MIF_s *di_buf0_mif,
struct DI_MIF_s *di_buf1_mif,
struct DI_MIF_s *di_buf2_mif,
struct DI_SIM_MIF_s *di_diwr_mif,
struct DI_SIM_MIF_s *di_mtnprd_mif,
struct DI_MC_MIF_s *di_mcvecrd_mif,
int ei_en, int blend_en, int blend_mtn_en, int blend_mode,
int di_vpp_en, int di_ddr_en,
int post_field_num, int hold_line, int urgent,
int invert_mv, bool pd_en, bool mc_enable,
int vskip_cnt
);
void di_post_read_reverse(bool reverse, bool mc_enable);
void di_post_read_reverse_irq(bool reverse,
unsigned char mc_pre_flag, bool mc_enable);
void di_top_gate_control(bool top_en, bool mc_en);
void di_pre_gate_control(bool enable, bool mc_enable);
void di_post_gate_control(bool gate);
void diwr_set_power_control(unsigned char enable);
void di_hw_disable(bool mc_enable);
void enable_di_pre_mif(bool enable, bool mc_enable);
void enable_di_post_mif(enum gate_mode_e mode);
void di_hw_uninit(void);
void di_load_regs(struct di_pq_parm_s *di_pq_ptr);
void combing_pd22_window_config(unsigned int width, unsigned int height);
void calc_lmv_init(void);
void calc_lmv_base_mcinfo(unsigned int vf_height, unsigned long mcinfo_adr);
void init_field_mode(unsigned short height);
void film_mode_win_config(unsigned int width, unsigned int height);
void pulldown_vof_win_config(struct pulldown_detected_s *wins);
void di_load_regs(struct di_pq_parm_s *di_pq_ptr);
#endif

339
drivers/amlogic/media/deinterlace/deinterlace_mtn.c
View File

@@ -39,7 +39,6 @@
#include <linux/amlogic/cpu_version.h>
#include <linux/amlogic/iomap.h>
#include "register.h"
#include "deinterlace.h"
#include "deinterlace_mtn.h"
#define MAX_NUM_DI_REG 32
@@ -88,7 +87,7 @@ module_param_array(combing_glb_mot_thr_LH, uint, &num_glb_mot_thr_LH, 0664);
static unsigned int num_glb_mot_thr_HL = 4;
module_param_array(combing_glb_mot_thr_HL, uint, &num_glb_mot_thr_HL, 0664);
int last_lev = -1;
static int last_lev = -1;
static int force_lev = 0xff;
module_param_named(combing_force_lev, force_lev, int, 0664);
static int dejaggy_flag = -1;
@@ -101,15 +100,6 @@ static uint num_dejaggy_setting = 5;
static int combing_dejaggy_setting[6] = {1, 1, 1, 2, 3, 3};
module_param_array(combing_dejaggy_setting, uint,
&num_dejaggy_setting, 0664);
#ifdef CONFIG_AM_ATVDEMOD
static int atv_snr_val = 30;
module_param_named(atv_snr_val, atv_snr_val, int, 0664);
static int atv_snr_cnt;
module_param_named(atv_snr_cnt, atv_snr_cnt, int, 0664);
static int atv_snr_cnt_limit = 30;
module_param_named(atv_snr_cnt_limit, atv_snr_cnt_limit, int, 0664);
#endif
static struct combing_param_s cmb_param;
static unsigned int combing_setting_masks[MAX_NUM_DI_REG] = {
@@ -123,7 +113,7 @@ static unsigned int combing_setting_masks[MAX_NUM_DI_REG] = {
0xffffffff,
0xffffffff,
0xffffffff,
0xffffffff,
0xffffff9f,
0xffffffff,
0x0003ff1f,
0x01ff3fff,
@@ -143,7 +133,7 @@ static unsigned int combing_pure_still_setting[MAX_NUM_DI_REG] = {
0x1A1A2662,
0x0D200302,
0x02020202,
0x06090708,
0x06090748,
0x40020A04,
0x0001FF0C,
0x00400204,
@@ -162,7 +152,7 @@ static unsigned int combing_bias_static_setting[MAX_NUM_DI_REG] = {
0x1A1A2662,
0x0D200302,
0x02020202,
0x06090708,
0x06090748,
0x40020A04,
0x0001FF0C,
0x00400204,
@@ -182,7 +172,7 @@ static unsigned int combing_normal_setting[MAX_NUM_DI_REG] = {
0x1A1A2662,
0x0D200302,
0x02020606,
0x05080304,
0x05080344,
0x40020a04,
0x0001FF0C,
0x00400204,
@@ -201,7 +191,7 @@ static unsigned int combing_bias_motion_setting[MAX_NUM_DI_REG] = {
0x1A1A2662,
0x0D200302,
0x02020606,
0x05080304,
0x05080344,
0x40020a04,
0x0001ff0c, /* 0x0001FF12 */
0x00400204, /* 0x00200204 */
@@ -220,7 +210,7 @@ static unsigned int combing_very_motion_setting[MAX_NUM_DI_REG] = {
0x1A1A2662,
0x0D200302,
0x02020606,
0x05080304,
0x05080344,
0x40020a04, /* 0x60000404,*/
0x0001ff0c, /* 0x0001FF12 */
0x00400204, /* 0x00200204 */
@@ -239,7 +229,7 @@ static unsigned int combing_resolution_setting[MAX_NUM_DI_REG] = {
0x1a1a2662,
0x0d200302,
0x01010101,
0x06090708,
0x06090748,
0x40020a04,
0x0001ff0c,
0x00400204,
@@ -278,10 +268,11 @@ static unsigned int (*combing_setting_values[6])[MAX_NUM_DI_REG] = {
&combing_very_motion_setting,
&combing_resolution_setting
};
void adpative_combing_config(unsigned int width, unsigned int height,
enum vframe_source_type_e src_type,
bool prog, enum tvin_sig_fmt_e fmt)
static struct combing_status_s cmb_status;
struct combing_status_s *adpative_combing_config(unsigned int width,
unsigned int height,
enum vframe_source_type_e src_type,
bool prog, enum tvin_sig_fmt_e fmt)
{
int i = 0;
@@ -294,10 +285,11 @@ void adpative_combing_config(unsigned int width, unsigned int height,
last_lev = -1;
cmb_param.width = width;
cmb_param.height = height;
cmb_param.field_idx = 0;
cmb_param.src_type = src_type;
cmb_param.fmt = fmt;
cmb_param.prog_flag = prog;
di_apply_reg_cfg(0);
return &cmb_status;
}
void adpative_combing_exit(void)
@@ -307,6 +299,7 @@ void adpative_combing_exit(void)
DI_Wr_reg_bits(SRSHARP0_SHARP_DEJ1_MISC, 0, 3, 1);
}
}
static int cmb_adpset_cnt;
unsigned int adp_set_level(unsigned int diff, unsigned int field_diff_num)
{
unsigned int rst = 0;
@@ -318,7 +311,7 @@ unsigned int adp_set_level(unsigned int diff, unsigned int field_diff_num)
rst = 1;
else
rst = 2;
pr_info("%s rst=%u.", __func__, rst);
if (cmb_adpset_cnt > 0) {
pr_info("\field-num=%04d frame-num=%04d lvl=%c\n",
field_diff_num, diff, tlog[rst]);
@@ -497,16 +490,19 @@ module_param(small_local_mtn, uint, 0644);
MODULE_PARM_DESC(small_local_mtn, "small_local_mtn");
unsigned int adp_set_mtn_ctrl10(unsigned int diff, unsigned int dlvel,
unsigned int *frame_diff_avg)
unsigned int frame_diff_avg)
{
int istp = 0, idats = 0, idatm = 0, idatr = 0;
unsigned int rst = 0;
if (*frame_diff_avg < small_local_mtn)
if (frame_diff_avg < small_local_mtn)
rst = combing_very_motion_setting[9];
else if (dlvel == 0)
rst = combing_pure_still_setting[9];
else if (dlvel == 1)
else if (dlvel == 0) {
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX))
rst = 0x01010101;
else
rst = combing_pure_still_setting[9];
} else if (dlvel == 1)
rst = combing_very_motion_setting[9];
else {
istp = 64 * (diff - combing_glb_mot_thr_LH[0]) /
@@ -540,7 +536,7 @@ unsigned int adp_set_mtn_ctrl10(unsigned int diff, unsigned int dlvel,
if (cmb_adpset_cnt > 0) {
pr_info("mtn_ctr10=0x%08x (frame_dif_avg=%03d)\n",
rst, *frame_diff_avg);
rst, frame_diff_avg);
}
return rst;
}
@@ -600,6 +596,10 @@ static void set_combing_regs(int lvl, int bit_mode)
if ((combing_setting_registers[i] == 0)
|| (combing_setting_masks[i] == 0))
break;
if (combing_setting_registers[i] == DI_MTN_1_CTRL1)
DI_Wr_reg_bits(DI_MTN_1_CTRL1,
((*combing_setting_values[lvl])[0] &
combing_setting_masks[i]), 0, 24);
if (bit_mode != 10 &&
combing_setting_registers[i] == NR2_MATNR_DEGHOST)
break;
@@ -622,15 +622,12 @@ static void set_combing_regs(int lvl, int bit_mode)
static int di_debug_readreg;
module_param(di_debug_readreg, int, 0644);
MODULE_PARM_DESC(di_debug_readreg, "di_debug_readreg");
static int dejaggy_4p = true;
module_param_named(dejaggy_4p, dejaggy_4p, int, 0664);
int adaptive_combing_fixing(
struct combing_status_s *cmb_status,
unsigned int field_diff,
unsigned int frame_diff,
int cur_lev, int bit_mode,
int cmb_cnt, int like_pulldown22_flag,
unsigned int *frame_diff_avg)
int bit_mode)
{
unsigned int glb_mot_avg2;
unsigned int glb_mot_avg3;
@@ -645,6 +642,7 @@ int adaptive_combing_fixing(
static unsigned int pre_num;
unsigned int crt_num = field_diff;
unsigned int drat = 0;
int tmp = 0;
static int still_field_count;
static int glb_mot[5] = {0, 0, 0, 0, 0};
@@ -654,13 +652,13 @@ int adaptive_combing_fixing(
diff = crt_num - pre_num;
if (diff >= cmb_param.width)
field_diff_rate = 0;
cmb_status->field_diff_rate = 0;
else {
drat = (diff << 8) / (cmb_param.width + 1);
if (drat > 255)
field_diff_rate = 0;
cmb_status->field_diff_rate = 0;
else
field_diff_rate = 256 - drat;
cmb_status->field_diff_rate = 256 - drat;
}
pre_num = crt_num;
@@ -690,26 +688,29 @@ int adaptive_combing_fixing(
else
if (still_field_count < 16)
still_field_count++;
if (glb_mot_avg3 > combing_glb_mot_thr_LH[min(cur_lev, 3)]) {
if (cur_lev < 4)
cur_lev++;
tmp = cmb_status->cur_level;
if (glb_mot_avg3 > combing_glb_mot_thr_LH[min(tmp, 3)]) {
if (cmb_status->cur_level < 4)
cmb_status->cur_level++;
} else {
tmp = cmb_status->cur_level;
if (glb_mot_avg5 <
combing_glb_mot_thr_HL[max(cur_lev - 1, 0)]) {
if (cur_lev <= 1 && still_field_count > 5)
cur_lev = 0;
combing_glb_mot_thr_HL[max((tmp - 1), 0)]) {
if (cmb_status->cur_level <= 1 && still_field_count > 5)
cmb_status->cur_level = 0;
else
cur_lev = max(cur_lev - 1, 1);
cmb_status->cur_level = max((tmp - 1), 1);
}
}
if ((force_lev >= 0) & (force_lev < 6))
cur_lev = force_lev;
if (cur_lev != last_lev) {
set_combing_regs(cur_lev, bit_mode);
if (pr_pd & 0x400)
pr_dbg("\t%5d: from %d to %d: di_mtn_1_ctrl1 = %08x\n",
field_count, last_lev, cur_lev, Rd(DI_MTN_1_CTRL1));
last_lev = cur_lev;
cmb_status->cur_level = force_lev;
if (cmb_status->cur_level != last_lev) {
set_combing_regs(cmb_status->cur_level, bit_mode);
if (prt_flg)
pr_info("\t%5d: from %d to %d: mtn_1_ctrl1 = %08x\n",
cmb_param.field_idx, last_lev,
cmb_status->cur_level, Rd(DI_MTN_1_CTRL1));
last_lev = cmb_status->cur_level;
}
if ((force_lev > 5) && (glb_mot[1] != glb_mot[0])) {
@@ -728,7 +729,7 @@ int adaptive_combing_fixing(
pre_dat[1] = Rd(DI_MTN_1_CTRL4);
wt_dat = adp_set_mtn_ctrl4(diff, dlvl, cmb_param.height,
cmb_cnt);
cmb_status->cmb_row_num);
if (pre_dat[1] != wt_dat) {
DI_Wr(DI_MTN_1_CTRL4, wt_dat);
if (prt_flg)
@@ -747,7 +748,8 @@ int adaptive_combing_fixing(
}
pre_dat[3] = Rd(DI_MTN_1_CTRL10);
wt_dat = adp_set_mtn_ctrl10(diff, dlvl, frame_diff_avg);
wt_dat = adp_set_mtn_ctrl10(diff, dlvl,
cmb_status->frame_diff_avg);
if (pre_dat[3] != wt_dat) {
DI_Wr(DI_MTN_1_CTRL10, wt_dat);
pre_dat[3] = wt_dat;
@@ -764,229 +766,10 @@ int adaptive_combing_fixing(
pr_info("set mtn11 0x%08x.\n\n", wt_dat);
}
}
if (is_meson_gxtvbb_cpu() && dejaggy_enable) {
/* only enable dejaggy for interlace */
if (cmb_param.prog_flag &&
!dejaggy_4p) {
if (dejaggy_flag != -1) {
dejaggy_flag = -1;
DI_Wr_reg_bits(SRSHARP0_SHARP_DEJ1_MISC,
0, 3, 1);
}
} else {
if ((dejaggy_flag == -1)
|| ((Rd(SRSHARP0_SHARP_SR2_CTRL) & (1 << 24)) == 0)) {
/* enable dejaggy module */
DI_Wr_reg_bits(SRSHARP0_SHARP_SR2_CTRL,
1, 24, 1);
/* first time set default */
DI_Wr_reg_bits(SRSHARP0_SHARP_DEJ2_PRC,
0xff, 24, 8);
DI_Wr(SRSHARP0_SHARP_DEJ1_PRC,
(0xff<<24)|(0xd1<<16)|(0xe<<8)|0x31);
DI_Wr(
SRSHARP0_SHARP_DEJ2_MISC, 0x30);
DI_Wr(
SRSHARP0_SHARP_DEJ1_MISC, 0x02f4);
dejaggy_flag = 0;
}
if (dejaggy_enable) {
/* dejaggy alpha according to motion level */
dejaggy_flag =
combing_dejaggy_setting[cur_lev];
/* TODO: check like_pulldown22_flag and ATV
* noise_level
*/
#ifdef CONFIG_AM_ATVDEMOD
if ((aml_atvdemod_get_snr_ex() < atv_snr_val)
&& cmb_param.src_type == VFRAME_SOURCE_TYPE_TUNER) {
if (atv_snr_cnt++ > atv_snr_cnt_limit)
dejaggy_flag += 3;
} else if (atv_snr_cnt)
atv_snr_cnt = 0;
#endif
if (like_pulldown22_flag && (cur_lev > 2))
dejaggy_flag += 1;
/* overwrite dejaggy alpha */
if (dejaggy_enable >= 2)
dejaggy_flag = dejaggy_enable;
if (dejaggy_flag > 4)
dejaggy_flag = 4;
if (dejaggy_flag)
DI_Wr_reg_bits(
SRSHARP0_SHARP_DEJ1_MISC,
(1<<3)|dejaggy_flag, 0, 4);
else
DI_Wr_reg_bits(
SRSHARP0_SHARP_DEJ1_MISC,
0, 3, 1);
} else
dejaggy_flag = 0;
}
} else if (is_meson_gxtvbb_cpu()) {
dejaggy_flag = -1;
DI_Wr_reg_bits(SRSHARP0_SHARP_DEJ1_MISC, 0, 3, 1);
}
return cur_lev;
cmb_param.field_idx++;
return 0;
}
static reg_cfg_t *reg_cfg_head;
/* new pre and post di setting */
reg_cfg_t di_default_pre = {
NULL,
((1 << VFRAME_SOURCE_TYPE_OTHERS) |
(1 << VFRAME_SOURCE_TYPE_TUNER) |
(1 << VFRAME_SOURCE_TYPE_CVBS) |
(1 << VFRAME_SOURCE_TYPE_COMP) |
(1 << VFRAME_SOURCE_TYPE_HDMI)
),
0,
0,
{
(
(TVIN_SIG_FMT_COMP_480P_60HZ_D000 << 16) |
TVIN_SIG_FMT_CVBS_SECAM),
0
},
{
{DI_EI_CTRL3, 0x0000013, 0, 27},
{DI_EI_CTRL4, 0x151b3084, 0, 31},
{DI_EI_CTRL5, 0x5273204f, 0, 31},
{DI_EI_CTRL6, 0x50232815, 0, 31},
{DI_EI_CTRL7, 0x2fb56650, 0, 31},
{DI_EI_CTRL8, 0x230019a4, 0, 31},
{DI_EI_CTRL9, 0x7cb9bb33, 0, 31},
/* #define DI_EI_CTRL10 */
{0x1793, 0x0842c6a9, 0, 31},
/* #define DI_EI_CTRL11 */
{0x179e, 0x486ab07a, 0, 31},
/* #define DI_EI_CTRL12 */
{0x179f, 0xdb0c2503, 0, 32},
/* #define DI_EI_CTRL13 */
{0x17a8, 0x0f021414, 0, 31},
{ 0 },
}
};
reg_cfg_t di_default_post = {
NULL,
((1 << VFRAME_SOURCE_TYPE_OTHERS) |
(1 << VFRAME_SOURCE_TYPE_TUNER) |
(1 << VFRAME_SOURCE_TYPE_CVBS) |
(1 << VFRAME_SOURCE_TYPE_COMP) |
(1 << VFRAME_SOURCE_TYPE_HDMI)
),
1,
2,
{
(
(TVIN_SIG_FMT_COMP_480P_60HZ_D000 << 16) |
TVIN_SIG_FMT_CVBS_SECAM),
0
},
{
{DI_MTN_1_CTRL1, 0, 30, 1},
{DI_MTN_1_CTRL1, 0x0202015, 0, 27},
{DI_MTN_1_CTRL2, 0x141a2062, 0, 31},
{DI_MTN_1_CTRL3, 0x1520050a, 0, 31},
{DI_MTN_1_CTRL4, 0x08800840, 0, 31},
{DI_MTN_1_CTRL5, 0x74200d0d, 0, 31},
/* #define DI_MTN_1_CTRL6 */
{DI_MTN_1_CTRL6, 0x0d5a1520, 0, 31},
/* #define DI_MTN_1_CTRL7 */
{DI_MTN_1_CTRL7, 0x0a0a0201, 0, 31},
/* #define DI_MTN_1_CTRL8 */
{DI_MTN_1_CTRL8, 0x1a1a2662, 0, 31},
/* #define DI_MTN_1_CTRL9 */
{DI_MTN_1_CTRL9, 0x0d200302, 0, 31},
/* #define DI_MTN_1_CTRL10 */
{DI_MTN_1_CTRL10, 0x02020606, 0, 31},
/* #define DI_MTN_1_CTRL11 */
{DI_MTN_1_CTRL11, 0x05080304, 0, 31},
/* #define DI_MTN_1_CTRL12 */
{DI_MTN_1_CTRL12, 0x40020a04, 0, 31},
{ 0 },
}
};
void di_add_reg_cfg(reg_cfg_t *reg_cfg)
{
reg_cfg->next = reg_cfg_head;
reg_cfg_head = reg_cfg;
}
void di_add_reg_cfg_init(void)
{
di_add_reg_cfg(&di_default_pre);
di_add_reg_cfg(&di_default_post);
}
static int use_reg_cfg = 1;
MODULE_PARM_DESC(use_reg_cfg, "\n use_reg_cfg\n");
module_param(use_reg_cfg, uint, 0664);
void di_apply_reg_cfg(unsigned char pre_post_type)
{
reg_cfg_t *reg_cfg = reg_cfg_head;
int ii;
unsigned char set_flag = 0;
if (!use_reg_cfg)
return;
while (reg_cfg) {
if ((pre_post_type == reg_cfg->pre_post_type) &&
((1 << cmb_param.src_type) &
reg_cfg->source_types_enable)) {
if (cmb_param.src_type ==
VFRAME_SOURCE_TYPE_OTHERS &&
(reg_cfg->dtv_definition_type != 2)) {
/* if:dtv stand definition
* else if:high definition
*/
if ((cmb_param.height<<1) < 720 &&
reg_cfg->dtv_definition_type)
set_flag = 1;
else if ((cmb_param.height<<1) >= 720
&& (!reg_cfg->dtv_definition_type))
set_flag = 1;
} else {
for (ii = 0; ii < FMT_MAX_NUM; ii++) {
if (reg_cfg->
sig_fmt_range[ii] == 0)
break;
else if (
(cmb_param.fmt >=
((reg_cfg->sig_fmt_range[ii]
>> 16) & 0xffff))
&& (cmb_param.fmt <=
(reg_cfg->sig_fmt_range[ii] &
0xffff))) {
set_flag = 1;
break;
}
}
}
}
if (set_flag) {
for (ii = 0; ii < REG_SET_MAX_NUM; ii++) {
if (reg_cfg->reg_set[ii].adr == 0)
break;
if (pre_post_type) {
DI_VSYNC_WR_MPEG_REG_BITS(
reg_cfg->reg_set[ii].adr,
reg_cfg->reg_set[ii].val,
reg_cfg->reg_set[ii].start,
reg_cfg->reg_set[ii].len);
} else {
RDMA_WR_BITS(
reg_cfg->reg_set[ii].adr,
reg_cfg->reg_set[ii].val,
reg_cfg->reg_set[ii].start,
reg_cfg->reg_set[ii].len);
}
}
break;
}
reg_cfg = reg_cfg->next;
}
}
#ifdef DEBUG_SUPPORT
module_param_named(cmb_adpset_cnt, cmb_adpset_cnt, int, 0644);
#endif

50
drivers/amlogic/media/deinterlace/deinterlace_mtn.h
View File

@@ -14,50 +14,34 @@
* more details.
*
*/
#ifndef _DI_MTN_H
#define _DI_MTN_H
#include <linux/amlogic/media/vfm/vframe.h>
#include <linux/amlogic/media/frame_provider/tvin/tvin.h>
struct combing_param_s {
unsigned int width;
unsigned int height;
unsigned int field_idx;
enum vframe_source_type_e src_type;
enum tvin_sig_fmt_e fmt;
bool prog_flag;
};
struct reg_set_s {
unsigned int adr;
unsigned int val;
unsigned short start;
unsigned short len;
struct combing_status_s {
unsigned int frame_diff_avg;
unsigned int cmb_row_num;
unsigned int field_diff_rate;
int like_pulldown22_flag;
unsigned int cur_level;
};
#define reg_set_t struct reg_set_s
#define REG_SET_MAX_NUM 128
#define FMT_MAX_NUM 32
struct reg_cfg_ {
struct reg_cfg_ *next;
unsigned int source_types_enable;
/* each bit corresponds to one source type */
unsigned int pre_post_type; /* pre, 0; post, 1 */
unsigned int dtv_definition_type;
/*high definition,0; stand definition ,1;common,2*/
unsigned int sig_fmt_range[FMT_MAX_NUM];
/* {bit[31:16]~bit[15:0]}, include bit[31:16] and bit[15:0] */
reg_set_t reg_set[REG_SET_MAX_NUM];
};
#define reg_cfg_t struct reg_cfg_
extern int last_lev;
extern int dejaggy_enable;
void adpative_combing_config(unsigned int width, unsigned int height,
enum vframe_source_type_e src_type, bool prog,
enum tvin_sig_fmt_e fmt);
struct combing_status_s *adpative_combing_config(unsigned int width,
unsigned int height,
enum vframe_source_type_e src_type, bool prog,
enum tvin_sig_fmt_e fmt);
int adaptive_combing_fixing(
struct combing_status_s *cmb_status,
unsigned int field_diff, unsigned int frame_diff,
int cur_lev, int bit_mode, int cmb_cnt,
int like_pulldown22_flag, unsigned int *frame_diff_avg);
int bit_mode);
void adpative_combing_exit(void);
#ifdef CONFIG_AM_ATVDEMOD
extern int aml_atvdemod_get_snr_ex(void);
#endif
void di_apply_reg_cfg(unsigned char pre_post_type);
void di_add_reg_cfg_init(void);

57
drivers/amlogic/media/deinterlace/deinterlace_trace.h Normal file
View File

@@ -0,0 +1,57 @@
/*
* drivers/amlogic/media/deinterlace/deinterlace_trace.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#undef TRACE_SYSTEM
#define TRACE_SYSTEM di
#if !defined(_DI_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
#define _DI_TRACE_H
#include <linux/tracepoint.h>
/* single lifecycle events */
DECLARE_EVENT_CLASS(di_event_class,
TP_PROTO(const char *name, int field_cnt, unsigned long time),
TP_ARGS(name, field_cnt, time),
TP_STRUCT__entry(
__string(name, name)
__field(int, field_cnt)
__field(unsigned long, time)
),
TP_fast_assign(
__assign_str(name, name);
__entry->field_cnt = field_cnt;
__entry->time = time;
),
TP_printk("[%s-%dth-%lums]", __get_str(name),
__entry->field_cnt, __entry->time)
);
#define DEFINE_DI_EVENT(name) \
DEFINE_EVENT(di_event_class, name, \
TP_PROTO(const char *name, int field_cnt, unsigned long time), \
TP_ARGS(name, field_cnt, time))
DEFINE_DI_EVENT(di_pre);
DEFINE_DI_EVENT(di_post);
#endif /* _VDEC_TRACE_H */
#undef TRACE_INCLUDE_PATH
#undef TRACE_INCLUDE_FILE
#define TRACE_INCLUDE_PATH .
#define TRACE_INCLUDE_FILE deinterlace_trace
#include <trace/define_trace.h>

11
drivers/amlogic/media/deinterlace/detect3d.c
View File

@@ -19,13 +19,10 @@
#include <linux/module.h>
/* Amlogic Headers */
#include <linux/amlogic/iomap.h>
#include <linux/amlogic/media/frame_provider/tvin/tvin.h>
#include <linux/amlogic/iomap.h>
#include "register.h"
#include "detect3d.h"
#include "deinterlace.h"
/*******************Local defines**********************/
#define DET3D_REG_NUM 9
@@ -98,7 +95,7 @@ static struct det3d_info_s det3d_info = {
* Enable and Disable det3d
* flag == true, enable det3d; flag == false, disable det3d;
*/
void det3d_enable(bool flag)
void det3d_config(bool flag)
{
int i;
@@ -225,7 +222,7 @@ det3d_info.tscore_3d_tb_accum + (tb_score <= 0) -
det3d_info.score_3d_chs = det3d_info.score_3d_chs + tmp1;
det3d_info.score_3d_int = det3d_info.score_3d_int + tmp2;
if (det3d_debug)
pr_dbg("%s input(%d,%d),output (%d,%d).\n",
pr_info("%s input(%d,%d),output (%d,%d).\n",
__func__, chessbd_score, int_score,
det3d_info.score_3d_chs, det3d_info.score_3d_int);
/* cliping to s7 */
@@ -422,9 +419,9 @@ chessbd_ver_thrd);
}
if (det3d_debug) {
pr_dbg("det3d:frame = %d, 3D_fmt = %d, score_3d_lr = %d,",
pr_info("det3d:frame = %d, 3D_fmt = %d, score_3d_lr = %d,",
det3d_info.nfrm, det3d_info.tfw_det3d_fmt, det3d_info.score_3d_lr);
pr_dbg("score_3d_tb = %d, score_3d_int = %d, score_3d_chs = %d",
pr_info("score_3d_tb = %d, score_3d_int = %d, score_3d_chs = %d",
det3d_info.score_3d_tb, det3d_info.score_3d_int, det3d_info.score_3d_chs);
}
return det3d_info.tfw_det3d_fmt;

2
drivers/amlogic/media/deinterlace/detect3d.h
View File

@@ -313,7 +313,7 @@ enum det3d_fmt_e {
/* *************************************** */
/* ******** GLOBAL FUNCTION CLAIM ******** */
/* *************************************** */
extern void det3d_enable(bool flag);
extern void det3d_config(bool flag);
extern enum tvin_trans_fmt det3d_fmt_detect(void);
#define WRITE_DET3D_REG(x, val) aml_write_vcbus(x, val)
#define WRITE_DET3D_REG_BITS(x, val, start, length) \

7
drivers/amlogic/media/deinterlace/film_mode_fmw/Makefile Normal file
View File

@@ -0,0 +1,7 @@
ifeq ($(TARGET_BUILD_VARIANT),userdebug)
ccflags-y := -D DEBUG_SUPPORT
endif
obj-y += film_mode.o
film_mode-objs += vof_soft_top.o
film_mode-objs += flm_mod_xx.o
film_mode-objs += film_fw1.o

240
drivers/amlogic/media/deinterlace/film_fw1.c → drivers/amlogic/media/deinterlace/film_mode_fmw/film_fw1.c
View File

@@ -1,5 +1,5 @@
/*
* drivers/amlogic/media/deinterlace/film_fw1.c
* drivers/amlogic/media/deinterlace/film_mode_fmw/film_fw1.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
@@ -19,6 +19,8 @@
#include <linux/module.h>
#include "film_vof_soft.h"
static int DIweavedetec(struct sFlmSftPar *pPar, int nDif01);
/* Software parameters (registers) */
UINT8 FlmVOFSftInt(struct sFlmSftPar *pPar)
{
@@ -38,7 +40,7 @@ UINT8 FlmVOFSftInt(struct sFlmSftPar *pPar)
pPar->sF32Dif01A1 = 65;
pPar->sF32Dif01T1 = 128;
pPar->sF32Dif01A2 = 65;
pPar->sF32Dif01A2 = 60;
pPar->sF32Dif01T2 = 128;
pPar->rCmbRwMinCt0 = 8; /* for film 3-2 */
@@ -52,11 +54,23 @@ UINT8 FlmVOFSftInt(struct sFlmSftPar *pPar)
*/
pPar->mNxtDlySft = 1;
pPar->sF32Dif02M0 = 4096; /* mpeg-4096, cvbs-8192 */
pPar->cmb22_nocmb_num = 30;
pPar->flm22_en = 1;
pPar->flm32_en = 1;
pPar->flm22_flag = 1;
pPar->flm2224_flag = 1;
pPar->flm22_comlev = 22;
pPar->flm22_comlev1 = 8;
pPar->flm22_comlev2 = 22;
pPar->flm22_comnum = 115;
pPar->flm22_comth = 15;
pPar->flm22_dif01_avgth = 55;
pPar->dif01rate = 20;
pPar->flag_di01th = 0;
pPar->numthd = 60;
pPar->sF32Dif02M0 = 4096;/* mpeg-4096, cvbs-8192 */
pPar->sF32Dif02M1 = 4096;
field_count = 0;
return 0;
}
@@ -103,6 +117,10 @@ int flm32_mim_frms = 6;
module_param(flm32_mim_frms, int, 0644);
MODULE_PARM_DESC(flm32_mim_frms, "flm32_mim_frms");
int flm22_dif01a_flag = 1;
module_param(flm22_dif01a_flag, int, 0644);
MODULE_PARM_DESC(flm22_dif01a_flag, "flm22_dif01a_flag");
int flm22_mim_frms = 60;
module_param(flm22_mim_frms, int, 0644);
MODULE_PARM_DESC(flm22_mim_frms, "flm22_mim_frms");
@@ -135,6 +153,10 @@ int flm32_chk3_rtn = 16;
module_param(flm32_chk3_rtn, int, 0644);
MODULE_PARM_DESC(flm32_chk3_rtn, "flm32_chk3_rtn");
int flm32_dif02_ratio = 8;
module_param(flm32_dif02_ratio, int, 0644);
MODULE_PARM_DESC(flm32_dif02_ratio, "flm32_dif02_ratio");
int flm22_chk20_sml = 6;
module_param(flm22_chk20_sml, int, 0644);
MODULE_PARM_DESC(flm22_chk20_sml, "flm22_chk20_sml");
@@ -200,15 +222,24 @@ int flm22_minus_cntmax = 2;
module_param(flm22_minus_cntmax, int, 0644);
MODULE_PARM_DESC(flm22_minus_cntmax, "flm22_minus_cntmax");
static int flagdif01chk = 1;
module_param(flagdif01chk, int, 0644);
MODULE_PARM_DESC(flagdif01chk, "flagdif01chk");
static int dif01_ratio = 10;
module_param(dif01_ratio, int, 0644);
MODULE_PARM_DESC(dif01_ratio, "dif01_ratio");
int comsum;
int FlmVOFSftTop(UINT8 *rCmb32Spcl, unsigned short *rPstCYWnd0,
unsigned short *rPstCYWnd1, unsigned short *rPstCYWnd2,
unsigned short *rPstCYWnd3, unsigned short *rPstCYWnd4,
UINT8 *rFlmPstGCm, UINT8 *rFlmSltPre, UINT8 *rFlmPstMod,
UINT32 *rROFldDif01, UINT32 *rROFrmDif02, UINT32 *rROCmbInf,
UINT32 glb_frame_mot_num, UINT32 glb_field_mot_num, int *tTCNm,
struct sFlmSftPar *pPar, int nROW, int nCOL,
unsigned int *frame_diff_avg)
unsigned short *rPstCYWnd1, unsigned short *rPstCYWnd2,
unsigned short *rPstCYWnd3, unsigned short *rPstCYWnd4,
UINT8 *rFlmPstGCm, UINT8 *rFlmSltPre, UINT8 *rFlmPstMod,
UINT8 *dif01flag, UINT32 *rROFldDif01, UINT32 *rROFrmDif02,
UINT32 *rROCmbInf, UINT32 glb_frame_mot_num,
UINT32 glb_field_mot_num, unsigned int *combing_row_num,
unsigned int *frame_diff_avg, struct sFlmSftPar *pPar, bool reverse)
{
static UINT32 DIF01[HISDIFNUM]; /* Last one is global */
static UINT32 DIF02[HISDIFNUM]; /* Last one is global */
@@ -218,34 +249,48 @@ int FlmVOFSftTop(UINT8 *rCmb32Spcl, unsigned short *rPstCYWnd0,
static struct sFlmDatSt pRDat;
static int pre22lvl;
static UINT32 pre_fld_motnum;
static int modpre;
static int num;
static int num32;
static int flag_pre;
static int comsumpre;
static int nS1pre;
int dif01th = 0;
int nDIF01[HISDIFNUM];
int nDIF02[HISDIFNUM];
/* UINT32 nCb32=0; */
unsigned int ntmp = 0;
unsigned int flm22_mim_numb = 0;
/* int nRCMB[ROWCMBNUM]; */
int mDly = pPar->mPstDlyPre;
int mNDly = pPar->mNxtDlySft;
int flm22 = pPar->flm22_en;
int flm32 = pPar->flm32_en;
int flm22_flag = pPar->flm22_flag;
int flm2224_flag = pPar->flm2224_flag;
int flm22_comth = pPar->flm22_comth;
int comdif = 0;
int dif01avg = 0;
int nT0 = 0;
int nT1 = 0;
int nS0 = 0;
int nS1 = 0;
int nMod = 0;
int difflag = 0;
/* difference */
pRDat.rROFrmDif02 = rROFrmDif02;
/* size of the image */
pRDat.iHeight = nROW; /* field height */
pRDat.iWidth = nCOL;
pRDat.iHeight = pPar->height; /* field height */
pRDat.iWidth = pPar->width;
prt_flg = 0;
debug_str[0] = '\0';
/* Initialization */
if (field_count < 3) {
if (pPar->field_count < 3) {
for (nT1 = 0; nT1 < HISDIFNUM; nT1++) {
DIF01[nT1] = 0xffffffff;
DIF02[nT1] = 0xffffffff;
@@ -296,7 +341,7 @@ int FlmVOFSftTop(UINT8 *rCmb32Spcl, unsigned short *rPstCYWnd0,
if (pr_pd) {
sprintf(debug_str, "\nField#%5d: [%4dx%4d]\n",
field_count, nROW, nCOL);
pPar->field_count, pPar->height, pPar->width);
sprintf(debug_str + strlen(debug_str),
"diff counter: %4d %4d\n",
glb_field_mot_num, glb_frame_mot_num);
@@ -389,7 +434,8 @@ int FlmVOFSftTop(UINT8 *rCmb32Spcl, unsigned short *rPstCYWnd0,
*/
*rFlmPstMod = 2;
/* param: at least 5 field+5 */
if (pRDat.mNum32[HISDETNUM - 1] < flm32_mim_frms) {
if (pRDat.mNum32[HISDETNUM - 1] < flm32_mim_frms ||
flm32 == 0) {
*rFlmSltPre = 0;
*rFlmPstMod = 0;
}
@@ -403,7 +449,7 @@ int FlmVOFSftTop(UINT8 *rCmb32Spcl, unsigned short *rPstCYWnd0,
*rFlmPstMod = 1;
ntmp = (glb_frame_mot_num + glb_field_mot_num) /
(nCOL + 1);
(pPar->width + 1);
if (flm22_mim_frms > ntmp + flm22_mim_smfrms)
flm22_mim_numb = flm22_mim_frms - ntmp;
else
@@ -426,6 +472,7 @@ int FlmVOFSftTop(UINT8 *rCmb32Spcl, unsigned short *rPstCYWnd0,
/*ntmp = DIF01[HISDIFNUM-1] / (glb_field_mot_num + 1);*/
/* min / max */
ntmp = DIF01[HISDIFNUM-1] / (pre_fld_motnum + 1);
dif01avg = ntmp;
if (pr_pd)
pr_info("diff01-avg=%4d\n", ntmp);
@@ -441,10 +488,38 @@ int FlmVOFSftTop(UINT8 *rCmb32Spcl, unsigned short *rPstCYWnd0,
else
pRDat.mNum22[HISDETNUM - 1] = 0;
}
comdif = (comsumpre < comsum) ? (comsum - comsumpre)
: (comsumpre - comsum);
if (pr_pd)
pr_info("comsum=%d, comsumpre=%d, flev=%d\n",
comsum, comsumpre, nS1);
if ((comsum < 200) && (comsum > pPar->flm22_comnum)
&& (comdif < flm22_comth) &&
flm22_dif01a_flag) {
if (nS1 < pPar->flm22_comlev)
nS1 = 0;
else
nS1 = nS1 - pPar->flm22_comlev;
} else if (dif01avg > pPar->flm22_dif01_avgth) {
if (nS1 < pPar->flm22_comlev)
nS1 = 0;
else
nS1 = nS1 - pPar->flm22_comlev;
}
if (pr_pd)
pr_info("flev=%d\n", nS1);
comsumpre = comsum;
} else if (nS1pre < 100) {
if (nS1 < pPar->flm22_comlev2)
nS1 = 0;
else
nS1 = nS1 - pPar->flm22_comlev2;
}
nS1pre = nS1;
/* param: at least 60 field+4 */
if (pRDat.mNum22[HISDETNUM - 1] < flm22_mim_numb) {
if (pRDat.mNum22[HISDETNUM - 1] < flm22_mim_numb ||
flm22 == 0) {
*rFlmSltPre = 0;
*rFlmPstMod = 0;
if (pr_pd)
@@ -461,19 +536,63 @@ int FlmVOFSftTop(UINT8 *rCmb32Spcl, unsigned short *rPstCYWnd0,
}
pre_fld_motnum = glb_field_mot_num;
VOFSftTop(rFlmPstGCm, rFlmSltPre, rFlmPstMod,
comsum = VOFSftTop(rFlmPstGCm, rFlmSltPre, rFlmPstMod,
rPstCYWnd0, rPstCYWnd1, rPstCYWnd2, rPstCYWnd3,
nMod, rROCmbInf, &pRDat, pPar, nROW, nCOL);
nMod, rROCmbInf, &pRDat, pPar, pPar->height,
pPar->width, reverse);
if (*rFlmPstMod == 1 && *rFlmPstGCm && flm22_flag)
*rFlmPstMod = 0;
nT1 = pRDat.pLvlXx[HISDETNUM - 1 - mDly];
if ((*rFlmPstMod == 0) && (nT1 > flmxx_maybe_num)
&& (nS0 != 6) && (pRDat.pMod22[HISDETNUM - 1 - mDly] != 2)) {
&& (nS0 != 6) &&
(pRDat.pMod22[HISDETNUM - 1 - mDly] != 2 || flm2224_flag)) {
*rFlmSltPre = pRDat.pFlgXx[HISDETNUM - 1 - mDly];
*rFlmPstMod = 4 + pRDat.pModXx[HISDETNUM - 1 - mDly];
nS1 = pRDat.pLvlXx[HISDETNUM - 1 - mDly];
}
*dif01flag = 2;
if (*rFlmPstMod == 0)
*dif01flag = DIweavedetec(pPar, rROFldDif01[0]);
if (num32 > 0 && *rFlmPstMod != 2)
num32 = num32-1;
if (pRDat.pFlg32[HISDETNUM - 1 - mDly] == 3) {
if (DIF01[HISDIFNUM - 2] > DIF01[HISDIFNUM - 1])
num32 = num32 + 1;
else if (num32 > 0)
num32 = num32 - 1;
}
if (modpre != *rFlmPstMod && modpre != 0 && *rFlmPstMod != 0 &&
num32 == 0) {
flag_pre = 1;
num = 0;
} else {
if (modpre == 0 || *rFlmPstMod == 0)
num = 0;
else if (num <= 255)
num = num + 1;
}
if (num > 5 || num32 > 0)
flag_pre = 0;
if (DIF01[HISDIFNUM - 2] < DIF01[HISDIFNUM - 1])
difflag = 1;
else
difflag = 0;
dif01th = (DIF01[HISDIFNUM - 2] + DIF01[HISDIFNUM - 1]) / dif01_ratio;
if (abs(DIF01[HISDIFNUM - 2] - DIF01[HISDIFNUM - 1]) > dif01th &&
flag_pre && flagdif01chk)
*rFlmSltPre = difflag;
modpre = *rFlmPstMod;
*combing_row_num = pRDat.TCNm[HISCMBNUM - 1];
pPar->field_count++;
if (pPar->field_count == 0x7fffffff)
pPar->field_count = 3;
*tTCNm = pRDat.TCNm[HISCMBNUM - 1];
return nS1;
}
@@ -647,9 +766,8 @@ int Flm32DetSft(struct sFlmDatSt *pRDat, int *nDif02,
if (nMn <= (1 << flm32_f2fdif_min0)) {
nSTP = nT2;
} else {
nSTP =
16 * (nDif02[HISDIFNUM - 1] - nMn) + (nAV1 - nMn +
sFrmDifLgTDif) / 2;
nSTP = flm32_dif02_ratio * (nDif02[HISDIFNUM - 1] - nMn) +
(nAV1 - nMn + sFrmDifLgTDif) / 2;
nSTP = nSTP / (nAV1 - nMn + sFrmDifLgTDif);
/* ======================== */
@@ -1036,6 +1154,10 @@ int Flm22DetSft(struct sFlmDatSt *pRDat, int *nDif02,
int sFlm20ftAlpha = pPar->sFlm20ftAlpha; /* 16; // [0~63] */
int sFlm2LgDifThd = pPar->sFlm2LgDifThd; /* 4096; */
int sFlm2LgFlgThd = pPar->sFlm2LgFlgThd; /* 8; */
int flm22_flag = pPar->flm22_flag;
int flm22_comlev = pPar->flm22_comlev;
int flm22_comlev1 = pPar->flm22_comlev1;
int flm22_comnum = pPar->flm22_comnum;
int cFlg = pFlg[HISDETNUM - 1];
int rFlg[4] = { 2, 3, 4, 1 };
@@ -1062,6 +1184,7 @@ int Flm22DetSft(struct sFlmDatSt *pRDat, int *nDif02,
int nOfst = 0;
int tMgn = 0;
int BtMn = 0;
static int num22;
int FdTg[6];
@@ -1435,6 +1558,33 @@ int Flm22DetSft(struct sFlmDatSt *pRDat, int *nDif02,
nFlm22Lvl -= nT1;
}
if (flm22_flag) {
if (pFlg[HISDETNUM-1] == 3
|| pFlg[HISDETNUM-1] == 1) {
if (comsum > flm22_comnum) {
if (num22 < 30)
num22 = num22 + 1;
else
nFlm22Lvl = nFlm22Lvl + flm22_comlev;
} else {
num22 = 0;
nFlm22Lvl = nFlm22Lvl - flm22_comlev;
}
/* if(prt_flg)
* pr_info("nFlm22Lvl = %d, comsum=%d,num22=%d,"
* "flm22_comnum=%d,flm22_flag=%d\n",
* nFlm22Lvl,comsum,num22,flm22_comnum,flm22_flag);
*/
}
if (nFlgCk20 < flm22_chk20_sml)
nFlm22Lvl = nFlm22Lvl + flm22_comlev1 - nFlgCk20;
if (nFlgCk21 < flm22_chk21_sml)
nFlm22Lvl = nFlm22Lvl + flm22_comlev1 - nFlgCk20;
if (prt_flg) {
pr_info("nFlm22Lvl=%d, nFlgCk20=%d, nFlgCk21=%d\n",
nFlm22Lvl, nFlgCk20, nFlgCk21);
}
}
/* for sony-mp3 */
nFlm22Lvl -= nFlgChk5;
@@ -1454,3 +1604,39 @@ int Flm22DetSft(struct sFlmDatSt *pRDat, int *nDif02,
return nFlm22Lvl;
}
static int DIweavedetec(struct sFlmSftPar *pPar, int nDif01)
{
int dif01th = 0;
int dif01rate = pPar->dif01rate;
int flag_di01th = pPar->flag_di01th;
int numthd = pPar->numthd;
static int numdif;
static int predifflag;
static int predif01;
static int difflag;
dif01th = (predif01+nDif01)/dif01rate;
if (abs(predif01 - nDif01) < dif01th && flag_di01th)
difflag = 2;
else {
if (predif01 < nDif01)
difflag = 1;
else
difflag = 0;
if (difflag^predifflag) {
if (numdif > 255)
numdif = numdif;
else
numdif = numdif + 1;
predifflag = difflag;
} else if (numdif > numthd) {
numdif = 0;
difflag = difflag^1;
predifflag = difflag;
} else
difflag = 2;
}
predif01 = nDif01;
return difflag;
}

208
drivers/amlogic/media/deinterlace/film_mode_fmw/film_vof_soft.h Normal file
View File

@@ -0,0 +1,208 @@
/*
* drivers/amlogic/media/deinterlace/film_mode_fmw/film_vof_soft.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef _FLMVOFSFT_H_
#define _FLMVOFSFT_H_
#include <linux/kernel.h>
/* Film Detection and VOF detection Software implementation */
/* Designer: Xin.Hu@amlogic.com */
/* Date: 12/06/13 */
/* Difference Windows Number (Last one is the global/total dif) */
/* 5wind+global */
/* #define DIFWNDNUM 6 */
#define HISDIFNUM 10
#define HISCMBNUM 10
/* detection history information */
#define HISDETNUM 6
/* The number of VOF window */
#define VOFWNDNUM 4
#define PDXX_PT_NUM 7
/* 288Row, 1bit/row -> (288/32)=9 */
#define ROWCMBNUM 288
#define ROWCMBLEN 9
#ifndef UINT32
#define UINT32 unsigned int
#endif
#ifndef UINT8
#define UINT8 unsigned char
#endif
#ifndef UShort
#define UShort unsigned short
#endif
extern uint pr_pd;
extern bool prt_flg;
extern char debug_str[];
/* Software: Film Detection and VOF parameters */
struct sFlmDatSt {
UINT8 pFlg32[HISDETNUM]; /* history information */
UINT8 pMod32[HISDETNUM];
UINT8 mNum32[HISDETNUM];
UINT8 pFld32[HISDETNUM];
UINT8 pFrm32[HISDETNUM];
UINT8 pFrm32t[HISDETNUM]; /* history information: spacial processing */
UINT8 pFlg22[HISDETNUM];
UINT8 pMod22[HISDETNUM];
UINT8 mNum22[HISDETNUM];
UINT8 pStp22[HISDETNUM];
UINT8 pSmp22[HISDETNUM];
UINT8 pModXx[HISDETNUM]; /* mode */
UINT8 pFlgXx[HISDETNUM]; /* pre-1, nxt-0 */
UINT8 pLvlXx[HISDETNUM]; /* mode level */
int TCNm[HISCMBNUM];/* history: the number of combing-rows */
UINT32 *rROFrmDif02;
/* size of the image */
int iHeight;
int iWidth;
};
/* Software parameters */
struct sFlmSftPar {
/* software */
int sFrmDifAvgRat; /* 16; //0~32 */
/* 4096; //The Large Decision should be: (large>average+LgDifThrd) */
int sFrmDifLgTDif;
int sF32StpWgt01; /* 15; */
int sF32StpWgt02; /* 15; */
int sF32DifLgRat; /* 16; //Dif>Rat*Min --> Larger */
int sFlm2MinAlpha; /* = 32; // [0~63] */
int sFlm2MinBelta; /* = 32; // [0~63] */
int sFlm20ftAlpha; /* = 16; // [0~63] */
int sFlm2LgDifThd; /* = 4096; // [0~63] %LgDifThrd */
int sFlm2LgFlgThd; /* = 8; */
int sF32Dif01A1; /* 65; */
int sF32Dif01T1; /* 128; */
int sF32Dif01A2; /* 65; */
int sF32Dif01T2; /* 128; */
int rCmbRwMinCt0; /* 8; //for film 3-2 */
int rCmbRwMinCt1; /* =7; //for film 2-2 */
UINT8 sFlm32NCmb; /* absolute no combing for film 32 */
/* pre-processing (t-0), post-processing f(t-mPstDlyPre); // No RTL */
int mPstDlyPre;
/* pre-processing (t-0), pre-processing f(t+mNxtDlySft); default=1 */
int mNxtDlySft;
int cmb22_nocmb_num;
int flm22_en;
int flm32_en;
int flm22_flag;
int flm2224_flag;
int flm22_comlev;
int flm22_comlev1;
int flm22_comlev2;
int flm22_comnum;
int flm22_comth;
int flm22_dif01_avgth;
int dif01rate;
int flag_di01th;
int numthd;
UINT32 sF32Dif02M0; /* mpeg-4096, cvbs-8192 */
UINT32 sF32Dif02M1; /* mpeg-4096, cvbs-8192 */
unsigned int field_count;
unsigned short width;
unsigned short height;
};
struct FlmModReg_t {
UINT32 rROFrmDif02[6]; /* Read only */
UINT32 rROFldDif01[6]; /* Read only */
UINT32 rROCmbInf[9];/* Inf[0]-[31:0], First-[31], Lst-[0] (Only 0/1) */
};
struct FlmDectRes {
UINT8 rCmb32Spcl;
UINT8 rFlmPstGCm;
UINT8 rFlmSltPre;
UINT8 rFlmPstMod;
UINT8 dif01flag;
UShort rPstCYWnds[5][3];
UShort rF22Flag;
};
UINT8 FlmVOFSftInt(struct sFlmSftPar *pPar);
/* Get 1-Row combing information, 1bit */
/* iHSCMB[9]; 9x32=288 */
UINT8 Get1RCmb(UINT32 *iHSCMB, UINT32 iRow);
int FlmModsDet(struct sFlmDatSt *pRDat, int nDif01, int nDif02);
/* */
int FlmVOFSftTop(UINT8 *rCmb32Spcl, unsigned short *rPstCYWnd0,
unsigned short *rPstCYWnd1, unsigned short *rPstCYWnd2,
unsigned short *rPstCYWnd3, unsigned short *rPstCYWnd4,
UINT8 *rFlmPstGCm, UINT8 *rFlmSltPre, UINT8 *rFlmPstMod,
UINT8 *dif01flag, UINT32 *rROFldDif01, UINT32 *rROFrmDif02,
UINT32 *rROCmbInf, UINT32 glb_frame_mot_num,
UINT32 glb_field_mot_num, unsigned int *cmb_row_num,
unsigned int *frame_diff_avg, struct sFlmSftPar *pPar, bool reverse);
/* length of pFlm01/nDif01: [0:5]; */
/* iDx: index of minimum dif02 ([0:5] */
int Cal32Flm01(UINT8 *pFlm01, int *nDif01, int iDx, struct sFlmSftPar *pPar);
/* Film Detection Software implementation */
/* nDif01: Fild Difference */
/* nDif02: Frame Difference */
/* WND: The index of Window */
int FlmDetSft(struct sFlmDatSt *pRDat, int *nDif01, int *nDif02, int WND,
struct sFlmSftPar *pPar);
int VOFDetSub1(int *PREWV, int *nCNum, int nMod, UINT32 *nRCmb, int nROW,
struct sFlmSftPar *pPar);
/* Video on Film Detection Software implementaion */
int VOFDetSft(int *VOFWnd, int *nCNum, int *nGCmb,
UINT32 HSCMB[HISCMBNUM][ROWCMBLEN], int nMod, UINT8 *PREWV,
int nROW, struct sFlmSftPar *pPar);
/* */
int Flm32DetSft(struct sFlmDatSt *pRDat, int *nDif02, int *nDif01,
struct sFlmSftPar *pPar);
/* Film2-2 Detection */
int Flm22DetSft(struct sFlmDatSt *pRDat, int *nDif02,
int *nDif01, struct sFlmSftPar *pPar);
/* length: [0:5] */
/* MIX: [1~5] */
int Flm32DetSub1(struct sFlmDatSt *pRDat, UINT8 *nFlg12, UINT8 *pFlm02t,
UINT8 *nFlg01, UINT8 *nFlg02, UINT8 MIX);
int VOFSftTop(UINT8 *rFlmPstGCm, UINT8 *rFlmSltPre, UINT8 *rFlmPstMod,
UShort *rPstCYWnd0, UShort *rPstCYWnd1, UShort *rPstCYWnd2,
UShort *rPstCYWnd3, int nMod, UINT32 *rROCmbInf,
struct sFlmDatSt *pRDat, struct sFlmSftPar *pPar,
int nROW, int nCOL, bool reverse);
#endif

2
drivers/amlogic/media/deinterlace/flm_mod_xx.c → drivers/amlogic/media/deinterlace/film_mode_fmw/flm_mod_xx.c
View File

@@ -1,5 +1,5 @@
/*
* drivers/amlogic/media/deinterlace/flm_mod_xx.c
* drivers/amlogic/media/deinterlace/film_mode_fmw/flm_mod_xx.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*

73
drivers/amlogic/media/deinterlace/vof_soft_top.c → drivers/amlogic/media/deinterlace/film_mode_fmw/vof_soft_top.c
View File

@@ -1,5 +1,5 @@
/*
* drivers/amlogic/media/deinterlace/vof_soft_top.c
* drivers/amlogic/media/deinterlace/film_mode_fmw/vof_soft_top.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
@@ -80,7 +80,7 @@ int VOFSftTop(UINT8 *rFlmPstGCm, UINT8 *rFlmSltPre, UINT8 *rFlmPstMod,
UShort *rPstCYWnd0, UShort *rPstCYWnd1,
UShort *rPstCYWnd2, UShort *rPstCYWnd3, int nMod,
UINT32 *rROCmbInf, struct sFlmDatSt *pRDat,
struct sFlmSftPar *pPar, int nROW, int nCOL)
struct sFlmSftPar *pPar, int nROW, int nCOL, bool reverse)
{
/* HSCMB[hist10][9(32bit)] */
static UINT32 HSCMB[HISCMBNUM][ROWCMBLEN];
@@ -92,7 +92,9 @@ int VOFSftTop(UINT8 *rFlmPstGCm, UINT8 *rFlmSltPre, UINT8 *rFlmPstMod,
static UINT8 NumSmFd; /* counter for same field */
int mDly = pPar->mPstDlyPre;
int flm22_flag = pPar->flm22_flag;
int cmb22_nocmb_num = pPar->cmb22_nocmb_num;
int cmb32_blw_wnd_rel = cmb32_blw_wnd;
/* UINT8 *PREWV = pRDat.pFlg32; or pRDat.pFlg22 */
/* static int TCNm[HISCMBNUM]; history: the number of combing-rows */
int *TCNm = pRDat->TCNm;
@@ -125,7 +127,9 @@ int VOFSftTop(UINT8 *rFlmPstGCm, UINT8 *rFlmSltPre, UINT8 *rFlmPstMod,
pFlgXx = (((pFlgXx >> 1) << 2) |
(pRDat->pFlgXx[HISDETNUM - 2] << 1) |
(pRDat->pFlgXx[HISDETNUM - 1]));
/* for 1080i */
if (nROW > 288)
cmb32_blw_wnd_rel = 70;
/* Initialization */
if (BGN == 0) {
for (nT0 = 0; nT0 < HISCMBNUM; nT0++) {
@@ -225,11 +229,21 @@ int VOFSftTop(UINT8 *rFlmPstGCm, UINT8 *rFlmSltPre, UINT8 *rFlmPstMod,
nWCmb = 0;
nBCmb = 0;
for (nT0 = 0; nT0 < nT1; nT0++) {
if (VOFWnd[2 * nT0] > (cmb32_blw_wnd * nROW >> 8)) {
CWND[HISDETNUM - 1][2 * nT0] =
VOFWnd[2 * nT0] - cmb32_wnd_ext;
CWND[HISDETNUM - 1][2 * nT0 + 1] =
VOFWnd[2 * nT0 + 1] + cmb32_wnd_ext;
if (VOFWnd[2*nT0] > (cmb32_blw_wnd_rel * nROW >> 8)) {
CWND[HISDETNUM-1][2*nT0] =
VOFWnd[2*nT0] - cmb32_wnd_ext;
CWND[HISDETNUM-1][2*nT0+1] =
VOFWnd[2*nT0+1] + cmb32_wnd_ext;
if (reverse) {
if (CWND[HISDETNUM-1][2*nT0+1] >=
nROW - 1)
CWND[HISDETNUM-1][2*nT0+1]
= nROW - 1;
CWND[HISDETNUM-1][2*nT0] = nROW - 1
- CWND[HISDETNUM-1][2*nT0+1];
CWND[HISDETNUM-1][2*nT0+1] = nROW
- 1 - (VOFWnd[2*nT0] - cmb32_wnd_ext);
}
nBCmb = VOFWnd[2*nT0+1]-VOFWnd[2*nT0]+1;
@@ -350,13 +364,17 @@ int VOFSftTop(UINT8 *rFlmPstGCm, UINT8 *rFlmSltPre, UINT8 *rFlmPstMod,
} /* here for vertical moving VOF */
} else if ((pMod22[HISDETNUM-1] == 2) &&
(pFlg22[HISDETNUM-1] & 0x1)) {
nT2 = ((nROW * cmb22_gcmb_rnum + 8) >> 4);
if (flm22_flag)
nT2 = 288 - cmb22_nocmb_num;
else
nT2 = ((nROW * cmb22_gcmb_rnum + 8) >> 4);
if (nCSum > nT2)
WGlb[HISDETNUM-1] = 1; /*global combing*/
else
WGlb[HISDETNUM-1] = 0; /*global combing*/
if (prt_flg)
sprintf(debug_str + strlen(debug_str),
"WGlb22=%d\n", WGlb[HISDETNUM-1]);
"WGlb22=%d\n", WGlb[HISDETNUM-1]);
for (nT0 = 0; nT0 < ROWCMBLEN; nT0++)
nRCmbAd[nT0] = HSCMB[HISCMBNUM-1][nT0];
@@ -377,7 +395,12 @@ int VOFSftTop(UINT8 *rFlmPstGCm, UINT8 *rFlmSltPre, UINT8 *rFlmPstMod,
for (nT0 = 0; nT0 < nT1; nT0++) {
CWND[HISDETNUM-1][2*nT0] = VOFWnd[2*nT0];
CWND[HISDETNUM-1][2*nT0+1] = VOFWnd[2*nT0+1];
if (reverse) {
CWND[HISDETNUM-1][2*nT0] =
nROW - 1 - VOFWnd[2*nT0+1];
CWND[HISDETNUM-1][2*nT0+1] =
nROW - 1 - VOFWnd[2*nT0];
}
if (prt_flg)
sprintf(debug_str + strlen(debug_str),
"Wnd22[%d]=[%3d~%3d]\n",
@@ -428,7 +451,12 @@ int VOFSftTop(UINT8 *rFlmPstGCm, UINT8 *rFlmSltPre, UINT8 *rFlmPstMod,
for (nT0 = 0; nT0 < nT1; nT0++) {
CWND[HISDETNUM-1][2*nT0] = VOFWnd[2*nT0];
CWND[HISDETNUM-1][2*nT0+1] = VOFWnd[2*nT0+1];
if (reverse) {
CWND[HISDETNUM-1][2*nT0] =
nROW - 1 - VOFWnd[2*nT0+1];
CWND[HISDETNUM-1][2*nT0+1] =
nROW - 1 - VOFWnd[2*nT0];
}
if (prt_flg)
sprintf(debug_str + strlen(debug_str),
"WndXx[%d]=[%3d~%3d]\n",
@@ -553,7 +581,7 @@ int VOFSftTop(UINT8 *rFlmPstGCm, UINT8 *rFlmSltPre, UINT8 *rFlmPstMod,
pr_info("%s", debug_str);
}
return nWCmb;
return nCSum;
}
/* int *PREWV:5*2 */
@@ -561,10 +589,10 @@ int VOFSftTop(UINT8 *rFlmPstGCm, UINT8 *rFlmSltPre, UINT8 *rFlmPstMod,
int VOFDetSub1(int *VOFWnd, int *nCNum, int nMod, UINT32 *nRCmb, int nROW,
struct sFlmSftPar *pPar)
{
int rCmbRwMinCt0 = pPar->rCmbRwMinCt0; /* 8; //for film 3-2 */
int rCmbRwMinCt1 = pPar->rCmbRwMinCt1; /* =7; //for film 2-2 */
int rCmbRwMinCt0 = 0; /* 8; //for film 3-2 */
int rCmbRwMinCt1 = 0; /* =7; //for film 2-2 */
/* int rCmbRwMaxStp=1; //fill in the hole */
int rCmbRwMinCt = rCmbRwMinCt1;
int rCmbRwMinCt = 0;
int nCSUM = 0; /* Combing sum (nCSUM>rCmbRwMinCt0) */
int nMIN = 0;
int nT0 = 0;
@@ -577,8 +605,16 @@ int VOFDetSub1(int *VOFWnd, int *nCNum, int nMod, UINT32 *nRCmb, int nROW,
int pIDx[VOFWNDNUM + 1][2]; /* Maximum-5windows */
int nIDx = 0;
rCmbRwMinCt = rCmbRwMinCt1;
if (nMod == 3)
rCmbRwMinCt = rCmbRwMinCt0;
if (IS_ERR(pPar)) {
pr_err("%s:%d pPar = 0x%p.\n",
__func__, __LINE__, pPar);
return -1;
}
rCmbRwMinCt0 = pPar->rCmbRwMinCt0; /* 8; //for film 3-2 */
rCmbRwMinCt1 = pPar->rCmbRwMinCt1; /* =7; //for film 2-2 */
for (nT0 = 0; (nT0 < nROW) && (nIDx <= VOFWNDNUM); nT0++) {
fEND = 0;
@@ -650,6 +686,7 @@ UINT8 Get1RCmb(UINT32 *iHSCMB, UINT32 iRow)
UINT8 nBt = 0;
nR1 = ((iRow >> 5) & 0xf);/* iRow/32; 0--8 */
iHSCMB[nR1] = nR1 > 8 ? 0 : iHSCMB[nR1];
nBt = (iRow & 0x1f);/* iRow%32 */
return (iHSCMB[nR1] >> nBt) & 0x1;
}

29
drivers/amlogic/media/deinterlace/film_vof_soft.h
View File

@@ -114,6 +114,20 @@ struct sFlmSftPar {
int mPstDlyPre;
/* pre-processing (t-0), pre-processing f(t+mNxtDlySft); default=1 */
int mNxtDlySft;
int cmb22_nocmb_num;
int flm22_en;
int flm32_en;
int flm22_flag;
int flm2224_flag;
int flm22_comlev;
int flm22_comlev1;
int flm22_comlev2;
int flm22_comnum;
int flm22_comth;
int flm22_dif01_avgth;
int dif01rate;
int flag_di01th;
int numthd;
UINT32 sF32Dif02M0; /* mpeg-4096, cvbs-8192 */
UINT32 sF32Dif02M1; /* mpeg-4096, cvbs-8192 */
@@ -130,6 +144,7 @@ struct FlmDectRes {
UINT8 rFlmPstGCm;
UINT8 rFlmSltPre;
UINT8 rFlmPstMod;
UINT8 dif01flag;
UShort rPstCYWnd0[3];
UShort rPstCYWnd1[3];
UShort rPstCYWnd2[3];
@@ -147,13 +162,15 @@ int FlmModsDet(struct sFlmDatSt *pRDat, int nDif01, int nDif02);
/* */
int FlmVOFSftTop(UINT8 *rCmb32Spcl, UShort *rPstCYWnd0, UShort *rPstCYWnd1,
UShort *rPstCYWnd2, UShort *rPstCYWnd3, UShort *rPstCYWnd4,
int FlmVOFSftTop(UINT8 *rCmb32Spcl, unsigned short *rPstCYWnd0,
unsigned short *rPstCYWnd1, unsigned short *rPstCYWnd2,
unsigned short *rPstCYWnd3, unsigned short *rPstCYWnd4,
UINT8 *rFlmPstGCm, UINT8 *rFlmSltPre, UINT8 *rFlmPstMod,
UINT32 *rROFldDif01, UINT32 *rROFrmDif02, UINT32 *rROCmbInf,
UINT32 glb_frame_mot_num, UINT32 glb_field_mot_num, int *tTCNm,
UINT8 *dif01flag, UINT32 *rROFldDif01, UINT32 *rROFrmDif02,
UINT32 *rROCmbInf, UINT32 glb_frame_mot_num,
UINT32 glb_field_mot_num, int *tTCNm,
struct sFlmSftPar *pPar, int nROW, int nCOL,
unsigned int *frame_diff_avg);
unsigned int *frame_diff_avg, bool reverse);
/* length of pFlm01/nDif01: [0:5]; */
/* iDx: index of minimum dif02 ([0:5] */
@@ -191,7 +208,7 @@ int VOFSftTop(UINT8 *rFlmPstGCm, UINT8 *rFlmSltPre, UINT8 *rFlmPstMod,
UShort *rPstCYWnd0, UShort *rPstCYWnd1, UShort *rPstCYWnd2,
UShort *rPstCYWnd3, int nMod, UINT32 *rROCmbInf,
struct sFlmDatSt *pRDat, struct sFlmSftPar *pPar,
int nROW, int nCOL);
int nROW, int nCOL, bool reverse);
extern UINT32 field_count;

602
drivers/amlogic/media/deinterlace/nr.c
View File

@@ -1,602 +0,0 @@
/*
* drivers/amlogic/media/deinterlace/nr.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/amlogic/iomap.h>
#include "register.h"
#include "nr.h"
#include "deinterlace.h"
static DNR_PRM_t dnr_param;
static DNR_PRM_t *pDnrPrm = &dnr_param;
static bool dnr_pr;
module_param(dnr_pr, bool, 0644);
MODULE_PARM_DESC(dnr_pr, "/n print dnr debug information /n");
bool dnr_dm_en;/*gxtvbb can't work normal,must set to 0*/
module_param(dnr_dm_en, bool, 0644);
MODULE_PARM_DESC(dnr_dm_en, "/n dnr dm enable debug /n");
bool dnr_reg_update = 1;/*gxtvbb can't work normal,must set to 0*/
module_param(dnr_reg_update, bool, 0644);
MODULE_PARM_DESC(dnr_reg_update, "/n dnr dm enable debug /n");
static unsigned int dnr_stat_coef = 3;/*gxtvbb default is 3*/
module_param(dnr_stat_coef, uint, 0644);
MODULE_PARM_DESC(dnr_stat_coef, "/n dnr stat coef /n");
static int dnr_prm_init(DNR_PRM_t *pPrm)
{
pPrm->prm_sw_gbs_ctrl = 0;
/* 0: update gbs, 1: update hoffst & gbs,
* 2: update voffst & gbs, 3: update all (hoffst & voffst & gbs).
*/
pPrm->prm_gbs_vldcntthd = 4;
pPrm->prm_gbs_cnt_min = 32;
pPrm->prm_gbs_ratcalcmod = 1;/* 0: use LR, 1: use Dif */
pPrm->prm_gbs_ratthd[0] = 40;
pPrm->prm_gbs_ratthd[1] = 80;
pPrm->prm_gbs_ratthd[2] = 120;
pPrm->prm_gbs_difthd[0] = 25;
pPrm->prm_gbs_difthd[1] = 75;
pPrm->prm_gbs_difthd[2] = 125;
pPrm->prm_gbs_bsdifthd = 1;
pPrm->prm_gbs_calcmod = 1; /* 0:dif0, 1:dif1, 2: dif2 */
pPrm->sw_gbs = 0;
pPrm->sw_gbs_vld_flg = 0;
pPrm->sw_gbs_vld_cnt = 0;
pPrm->prm_hbof_minthd = 32;
pPrm->prm_hbof_ratthd0 = 150;
pPrm->prm_hbof_ratthd1 = 150;
pPrm->prm_hbof_vldcntthd = 4;
pPrm->sw_hbof = 0;
pPrm->sw_hbof_vld_flg = 0;
pPrm->sw_hbof_vld_cnt = 0;
pPrm->prm_vbof_minthd = 32;
pPrm->prm_vbof_ratthd0 = 150;
pPrm->prm_vbof_ratthd1 = 120;
pPrm->prm_vbof_vldcntthd = 4;
pPrm->sw_vbof = 0;
pPrm->sw_vbof_vld_flg = 0;
pPrm->sw_vbof_vld_cnt = 0;
return 0;
}
int global_bs_calc_sw(int *pGbsVldCnt,
int *pGbsVldFlg,
int *pGbs,
int nGbsStatLR,
int nGbsStatLL,
int nGbsStatRR,
int nGbsStatDif,
int nGbsStatCnt,
int prm_gbs_vldcntthd, /* prm below */
int prm_gbs_cnt_min,
int prm_gbs_ratcalcmod,
int prm_gbs_ratthd[3],
int prm_gbs_difthd[3],
int prm_gbs_bsdifthd,
int prm_gbs_calcmod)
{
int nMax, nMin;
int nDif0, nDif1, nDif2;
int nDif, nRat;
int nCurGbs;
nMax = max(max(nGbsStatLR, nGbsStatLL), nGbsStatRR);
nMin = min(min(nGbsStatLR, nGbsStatLL), nGbsStatRR);
nDif0 = nMax == 0 ? 0 : ((nMax - nMin) << 9)/nMax;
nDif0 = min(511, nDif0);
nDif1 = nGbsStatLR == 0 ? 0 :
(abs(nGbsStatLR - (nGbsStatLL + nGbsStatRR)/2) << 9)/nGbsStatLR;
nDif1 = min(511, nDif1);
nDif2 = nGbsStatLR == 0 ? 0 :
(abs(nGbsStatLR - max(nGbsStatLL, nGbsStatRR)) << 9)/nGbsStatLR;
nDif2 = min(511, nDif2);
if (prm_gbs_ratcalcmod == 0)
nRat = (nGbsStatLR << 4) / max(prm_gbs_cnt_min, nGbsStatCnt);
else
nRat = (nGbsStatDif << 4) / max(prm_gbs_cnt_min, nGbsStatCnt);
nDif = (prm_gbs_calcmod == 0) ? nDif0 :
(prm_gbs_calcmod == 1 ? nDif1 : nDif2);
if (nGbsStatLR < max(nGbsStatLL, nGbsStatRR)) {
if (nGbsStatCnt <= prm_gbs_cnt_min || nRat <= prm_gbs_ratthd[0])
nCurGbs = 0;
else if (nRat <= prm_gbs_ratthd[1])
nCurGbs = 1;
else if (nRat <= prm_gbs_ratthd[2])
nCurGbs = 2;
else
nCurGbs = 3;
} else {
if (nGbsStatCnt <= prm_gbs_cnt_min || nDif <= prm_gbs_difthd[0])
nCurGbs = 0;
else if (nDif <= prm_gbs_difthd[1])
nCurGbs = 1;
else if (nDif <= prm_gbs_difthd[2])
nCurGbs = 2;
else
nCurGbs = 3;
}
/* */
if ((nCurGbs != 0 && 0 == *pGbs) ||
(nCurGbs != 0 && abs(nCurGbs - *pGbs) <= prm_gbs_bsdifthd))
(*pGbsVldCnt)++;
else
*pGbsVldCnt = 0;
if (*pGbsVldCnt >= prm_gbs_vldcntthd)
*pGbsVldFlg = 1;
else
*pGbsVldFlg = 0;
*pGbs = nCurGbs;
/* print debug info. */
/* printk("GBS info at Field: LR = %6d, LL = %6d, RR = %6d.\n",
* nGbsStatLR, nGbsStatLL, nGbsStatRR;
*/
return 0;
}
#ifdef DNR_HV_SHIFT
int hor_blk_ofst_calc_sw(int *pHbOfVldCnt,
int *pHbOfVldFlg,
int *pHbOfst,
int nHbOfStatCnt[32],
int nXst,
int nXed,
int prm_hbof_minthd,
int prm_hbof_ratthd0,
int prm_hbof_ratthd1,
int prm_hbof_vldcntthd,
int nRow,
int nCol)
{
int i = 0;
int nCurHbOfst = 0;
int nRat0 = 0, nRat1 = 0;
int nMax1 = 0;
int nMax2 = 0;
int nMaxIdx = 0;
/* get 2 maximum, move to RTL part */
nMax1 = nMax2 = 0;
for (i = 0; i < 8; i++) {
if (nHbOfStatCnt[i] > nMax1) {
nMax2 = nMax1;
nMax1 = nHbOfStatCnt[i];
nMaxIdx = i;
} else if (nHbOfStatCnt[i] > nMax2) {
nMax2 = nHbOfStatCnt[i];
}
} /* i */
/* decide if offset valid */
nCurHbOfst = -1;
nRat0 = 256*nMax1/((nXed - nXst)/8)/nRow;
nRat1 = 128*nMax1/max(nMax2, prm_hbof_minthd);
if (nRat0 >= prm_hbof_ratthd0 && nRat1 >= prm_hbof_ratthd1)
nCurHbOfst = (nMaxIdx+1)%8;
if (nCurHbOfst == *pHbOfst)
(*pHbOfVldCnt)++;
else
*pHbOfVldCnt = 0;
if (*pHbOfVldCnt >= prm_hbof_vldcntthd)
*pHbOfVldFlg = 1;
else
*pHbOfVldFlg = 0;
*pHbOfst = (nCurHbOfst == -1) ? 0 : nCurHbOfst;
/* print for debug
* printk("Hoff info at Field: ");
* for ( i = 0; i < 32; i++ ) {
* printk("%5d, ", nHbOfStatCnt[i]);
* }
*/
if (dnr_pr) {
pr_dbg("Max1 = %5d, Max2 = %5d, MaxIdx = %5d, Rat0 = %5d,Rat1 = %5d.\n",
nMax1, nMax2, nMaxIdx, nRat0, nRat1);
pr_dbg("CurHbOfst = %5d, HbOfVldFlg = %d, HbOfVldCnt = %d.\n",
nCurHbOfst, *pHbOfVldFlg, *pHbOfVldCnt);
}
return 0;
}
int ver_blk_ofst_calc_sw(int *pVbOfVldCnt,
int *pVbOfVldFlg,
int *pVbOfst,
int nVbOfStatCnt[32],
int nYst,
int nYed,
int prm_vbof_minthd,
int prm_vbof_ratthd0,
int prm_vbof_ratthd1,
int prm_vbof_vldcntthd,
int nRow,
int nCol)
{
int i = 0;
int nCurVbOfst = 0;
int nRat0 = 0, nRat1 = 0;
int nMax1 = 0;
int nMax2 = 0;
int nMaxIdx = 0;
/* get 2 maximum, move to RTL part */
nMax1 = nMax2 = 0;
for (i = 0; i < 8; i++) {
if (nVbOfStatCnt[i] > nMax1) {
nMax2 = nMax1;
nMax1 = nVbOfStatCnt[i];
nMaxIdx = i;
}
else if (nVbOfStatCnt[i] > nMax2) {
nMax2 = nVbOfStatCnt[i];
}
}
/* decide if offset valid */
nCurVbOfst = -1;
nRat0 = 256*nMax1/((nYed - nYst)/8)/nCol;
nRat1 = 128*nMax1/max(nMax2, prm_vbof_minthd);
if (nRat0 >= prm_vbof_ratthd0 && nRat1 >= prm_vbof_ratthd1)
nCurVbOfst = (nMaxIdx+1)%8;
if (nCurVbOfst == *pVbOfst)
(*pVbOfVldCnt)++;
else
*pVbOfVldCnt = 0;
if (*pVbOfVldCnt >= prm_vbof_vldcntthd)
*pVbOfVldFlg = 1;
else
*pVbOfVldFlg = 0;
*pVbOfst = (nCurVbOfst == -1) ? 0 : nCurVbOfst;
/* print for debug
* printk("Voff info at Field: ");
* for ( i = 0; i < 32; i++ ) {
* printk("%5d, ", nVbOfStatCnt[i]);
* }//i
* //printk("Max1 = %5d, Max2 = %5d, MaxIdx = %5d, Rat0 = %5d,
* Rat1 = %5d, CurVbOfst = %5d, VbOfVldFlg = %d, VbOfVldCnt = %d.\n"
* nMax1, nMax2, nMaxIdx, nRat0, nRat1, nCurVbOfst, *pVbOfVldFlg,
* *pVbOfVldCnt);
*/
return 0;
}
#endif
void run_dnr_in_irq(unsigned short nCol, unsigned short nRow)
{
static int ro_gbs_stat_lr = 0, ro_gbs_stat_ll = 0, ro_gbs_stat_rr = 0,
ro_gbs_stat_dif = 0, ro_gbs_stat_cnt = 0;
/* int reg_dnr_stat_xst=0,reg_dnr_stat_xed=0,
* reg_dnr_stat_yst=0,reg_dnr_stat_yed=0;
*/
#ifdef DNR_HV_SHIFT
int ro_hbof_stat_cnt[32], ro_vbof_stat_cnt[32], i = 0;
#endif
if (dnr_reg_update == 0)
return;
DI_Wr(DNR_CTRL, 0x1df00);
DI_Wr(DNR_DM_CTRL, Rd(DNR_DM_CTRL)|(1 << 11));
/* dm for sd, hd will slower */
if (nCol >= 1920)
DI_Wr_reg_bits(DNR_DM_CTRL, 0, 9, 1);
else
DI_Wr_reg_bits(DNR_DM_CTRL, dnr_dm_en, 9, 1);
DI_Wr(DNR_HVSIZE, nCol<<16|nRow);
DI_Wr(DNR_STAT_X_START_END, (((dnr_stat_coef<<3)&0x3fff) << 16)
|((nCol-((dnr_stat_coef<<3)+1))&0x3fff));
DI_Wr(DNR_STAT_Y_START_END, (((dnr_stat_coef<<3)&0x3fff) << 16)
|((nRow-((dnr_stat_coef<<3)+1))&0x3fff));
if (ro_gbs_stat_lr != Rd(DNR_RO_GBS_STAT_LR) ||
ro_gbs_stat_ll != Rd(DNR_RO_GBS_STAT_LL) ||
ro_gbs_stat_rr != Rd(DNR_RO_GBS_STAT_RR) ||
ro_gbs_stat_dif != Rd(DNR_RO_GBS_STAT_DIF) ||
ro_gbs_stat_cnt != Rd(DNR_RO_GBS_STAT_CNT)) {
ro_gbs_stat_lr = Rd(DNR_RO_GBS_STAT_LR);
ro_gbs_stat_ll = Rd(DNR_RO_GBS_STAT_LL);
ro_gbs_stat_rr = Rd(DNR_RO_GBS_STAT_RR);
ro_gbs_stat_dif = Rd(DNR_RO_GBS_STAT_DIF);
ro_gbs_stat_cnt = Rd(DNR_RO_GBS_STAT_CNT);
} else {
return;
}
global_bs_calc_sw(&pDnrPrm->sw_gbs_vld_cnt,
&pDnrPrm->sw_gbs_vld_flg,
&pDnrPrm->sw_gbs,
ro_gbs_stat_lr,
ro_gbs_stat_ll,
ro_gbs_stat_rr,
ro_gbs_stat_dif,
ro_gbs_stat_cnt,
pDnrPrm->prm_gbs_vldcntthd, /* prm below */
pDnrPrm->prm_gbs_cnt_min,
pDnrPrm->prm_gbs_ratcalcmod,
pDnrPrm->prm_gbs_ratthd,
pDnrPrm->prm_gbs_difthd,
pDnrPrm->prm_gbs_bsdifthd,
pDnrPrm->prm_gbs_calcmod);
#ifdef DNR_HV_SHIFT
for (i = 0; i < 32; i++)
ro_hbof_stat_cnt[i] = Rd(DNR_RO_HBOF_STAT_CNT_0+i);
for (i = 0; i < 32; i++)
ro_vbof_stat_cnt[i] = Rd(DNR_RO_VBOF_STAT_CNT_0+i);
hor_blk_ofst_calc_sw(&pDnrPrm->sw_hbof_vld_cnt,
&pDnrPrm->sw_hbof_vld_flg,
&pDnrPrm->sw_hbof,
ro_hbof_stat_cnt,
0,
nCol-1,
pDnrPrm->prm_hbof_minthd,
pDnrPrm->prm_hbof_ratthd0,
pDnrPrm->prm_hbof_ratthd1,
pDnrPrm->prm_hbof_vldcntthd,
nRow,
nCol);
ver_blk_ofst_calc_sw(&pDnrPrm->sw_vbof_vld_cnt,
&pDnrPrm->sw_vbof_vld_flg,
&pDnrPrm->sw_vbof,
ro_vbof_stat_cnt,
0,
nRow-1,
pDnrPrm->prm_vbof_minthd,
pDnrPrm->prm_vbof_ratthd0,
pDnrPrm->prm_vbof_ratthd1,
pDnrPrm->prm_vbof_vldcntthd,
nRow,
nCol);
#endif
/* update hardware registers */
if (pDnrPrm->prm_sw_gbs_ctrl == 0) {
DI_Wr(DNR_GBS,
(pDnrPrm->sw_gbs_vld_flg == 1)?pDnrPrm->sw_gbs : 0);
} else if (pDnrPrm->prm_sw_gbs_ctrl == 1) {
DI_Wr_reg_bits(DNR_BLK_OFFST,
(pDnrPrm->sw_hbof_vld_flg == 1)?pDnrPrm->sw_hbof:0, 4, 3);
DI_Wr(DNR_GBS, (pDnrPrm->sw_hbof_vld_flg == 1 &&
pDnrPrm->sw_gbs_vld_flg == 1)?pDnrPrm->sw_gbs:0);
} else if (pDnrPrm->prm_sw_gbs_ctrl == 2) {
DI_Wr_reg_bits(DNR_BLK_OFFST,
(pDnrPrm->sw_vbof_vld_flg == 1)?pDnrPrm->sw_vbof:0, 0, 3);
DI_Wr(DNR_GBS, (pDnrPrm->sw_vbof_vld_flg == 1 &&
pDnrPrm->sw_gbs_vld_flg == 1)?pDnrPrm->sw_gbs:0);
} else if (pDnrPrm->prm_sw_gbs_ctrl == 1) {
DI_Wr_reg_bits(DNR_BLK_OFFST,
pDnrPrm->sw_hbof_vld_flg == 1 ? pDnrPrm->sw_hbof : 0, 4, 3);
DI_Wr_reg_bits(DNR_BLK_OFFST,
pDnrPrm->sw_vbof_vld_flg == 1 ? pDnrPrm->sw_vbof : 0, 0, 3);
DI_Wr(DNR_GBS, (pDnrPrm->sw_hbof_vld_flg == 1 &&
pDnrPrm->sw_vbof_vld_flg == 1 &&
pDnrPrm->sw_gbs_vld_flg == 1)?pDnrPrm->sw_gbs:0);
}
}
static void parse_cmd_params(char *buf_orig, char **parm)
{
char *ps, *token;
char delim1[2] = " ";
char delim2[2] = "\n";
unsigned int n = 0;
ps = buf_orig;
strcat(delim1, delim2);
while (1) {
token = strsep(&ps, delim1);
if (token == NULL)
break;
if (*token == '\0')
continue;
parm[n++] = token;
}
}
static dnr_param_t dnr_params[] = {
{"prm_sw_gbs_ctrl", &(dnr_param.prm_sw_gbs_ctrl)},
{"prm_gbs_vldcntthd", &(dnr_param.prm_gbs_vldcntthd)},
{"prm_gbs_cnt_min", &(dnr_param.prm_gbs_cnt_min)},
{"prm_gbs_ratcalcmod", &(dnr_param.prm_gbs_ratcalcmod)},
{"prm_gbs_ratthd[0]", &(dnr_param.prm_gbs_ratthd[0])},
{"prm_gbs_ratthd[1]", &(dnr_param.prm_gbs_ratthd[1])},
{"prm_gbs_ratthd[2]", &(dnr_param.prm_gbs_ratthd[2])},
{"prm_gbs_difthd[0]", &(dnr_param.prm_gbs_difthd[0])},
{"prm_gbs_difthd[1]", &(dnr_param.prm_gbs_difthd[1])},
{"prm_gbs_difthd[2]", &(dnr_param.prm_gbs_difthd[2])},
{"prm_gbs_bsdifthd", &(dnr_param.prm_gbs_bsdifthd)},
{"prm_gbs_calcmod", &(dnr_param.prm_gbs_calcmod)},
{"sw_gbs", &(dnr_param.sw_gbs)},
{"sw_gbs_vld_flg", &(dnr_param.sw_gbs_vld_flg)},
{"sw_gbs_vld_cnt", &(dnr_param.sw_gbs_vld_cnt)},
{"prm_hbof_minthd", &(dnr_param.prm_hbof_minthd)},
{"prm_hbof_ratthd0", &(dnr_param.prm_hbof_ratthd0)},
{"prm_hbof_ratthd1", &(dnr_param.prm_hbof_ratthd1)},
{"prm_hbof_vldcntthd", &(dnr_param.prm_hbof_vldcntthd)},
{"sw_hbof", &(dnr_param.sw_hbof)},
{"sw_hbof_vld_flg", &(dnr_param.sw_hbof_vld_flg)},
{"sw_hbof_vld_cnt", &(dnr_param.sw_hbof_vld_cnt)},
{"prm_vbof_minthd", &(dnr_param.prm_vbof_minthd)},
{"prm_vbof_ratthd0", &(dnr_param.prm_vbof_ratthd0)},
{"prm_vbof_ratthd1", &(dnr_param.prm_vbof_ratthd1)},
{"prm_vbof_vldcntthd", &(dnr_param.prm_vbof_vldcntthd)},
{"sw_vbof", &(dnr_param.sw_vbof)},
{"sw_vbof_vld_flg", &(dnr_param.sw_vbof_vld_flg)},
{"sw_vbof_vld_cnt", &(dnr_param.sw_vbof_vld_cnt)},
{"", NULL}
};
static ssize_t dnr_param_store(struct device *dev,
struct device_attribute *attr,
const char *buff, size_t count)
{
int i = 0, value = 0;
char *parm[2] = {NULL}, *buf_orig;
buf_orig = kstrdup(buff, GFP_KERNEL);
parse_cmd_params(buf_orig, (char **)(&parm));
for (i = 0; dnr_params[i].addr; i++) {
if (!strcmp(parm[0], dnr_params[i].name)) {
value = kstrtol(parm[1], 10, NULL);
*(dnr_params[i].addr) = value;
pr_dbg("%s=%d.\n", dnr_params[i].name,
*(dnr_params[i].addr));
}
}
return count;
}
static ssize_t dnr_param_show(struct device *dev,
struct device_attribute *attr,
char *buff)
{
ssize_t len = 0;
int i = 0;
for (i = 0; dnr_params[i].addr; i++)
len += sprintf(buff+len, "%s=%d.\n",
dnr_params[i].name,
*(dnr_params[i].addr));
return len;
}
static DEVICE_ATTR(dnr_param, 0664, dnr_param_show, dnr_param_store);
void di_nr_init(void)
{
#if 0
DI_Wr(DI_NR_CTRL0, 0xc60c0804);
DI_Wr(DI_NR_CTRL1, 0x403e3c3a);
DI_Wr(DI_NR_CTRL2, 0x08010a01);
DI_Wr(NR2_MET_NM_CCTRL, 0x45056410);
DI_Wr(NR2_MATNR_SNR_NRM_GAIN, 0x4);
DI_Wr(NR2_MATNR_SNR_LPF_CFG, 0xc2b64);
DI_Wr(NR2_MATNR_SNR_EDGE2B, 0xcff08);
DI_Wr(NR2_MATNR_YBETA_SCL, 0x00ff2000);
DI_Wr(NR2_MATNR_MTN_CRTL2, 0x32020);
DI_Wr(NR2_MATNR_MTN_COR, 0x3333);
DI_Wr(NR2_MATNR_DEGHOST, 0x133);
DI_Wr(NR2_MATNR_ALPHALP_LUT0, 0x99999a9a);
DI_Wr(NR2_MATNR_ALPHALP_LUT1, 0x9aa0a6e3);
DI_Wr(NR2_MATNR_ALPHALP_LUT2, 0x90808080);
DI_Wr(NR2_MATNR_ALPHALP_LUT3, 0xffe0c0a4);
DI_Wr(NR2_MATNR_ALPHAHP_LUT1, 0x80805040);
DI_Wr(NR2_MATNR_ALPHAHP_LUT2, 0x90808080);
DI_Wr(NR2_MATNR_ALPHAHP_LUT3, 0xffe0c0a4);
#endif
DI_Wr(NR3_MODE, 0x3);
DI_Wr(NR3_COOP_PARA, 0x28ff00);
DI_Wr(NR3_CNOOP_GAIN, 0x881900);
DI_Wr(NR3_YMOT_PARA, 0x0c0a1e);
DI_Wr(NR3_CMOT_PARA, 0x08140f);
DI_Wr(NR3_SUREMOT_YGAIN, 0x100c4014);
DI_Wr(NR3_SUREMOT_CGAIN, 0x22264014);
DI_Wr(0x1745, 0x5056410);
DI_Wr(0x1746, 0x45056410);
DI_Wr(0x1747, 0x45056410);
DI_Wr(0x1748, 0x1);
DI_Wr(0x1749, 0x7c3a);
DI_Wr(0x174a, 0x29e77);
DI_Wr(0x174b, 0x9f1a);
DI_Wr(0x174c, 0x2822c);
DI_Wr(0x174d, 0x77);
DI_Wr(0x174e, 0x3030);
DI_Wr(0x174f, 0x20030);
DI_Wr(0x1750, 0xf002d0);
DI_Wr(0x1751, 0x132f);
DI_Wr(0x1752, 0x8d);
DI_Wr(0x1753, 0x40ff00);
DI_Wr(0x1754, 0x4);
DI_Wr(0x1755, 0xc2b64);
DI_Wr(0x1756, 0x0);
DI_Wr(0x1757, 0x3608);
DI_Wr(0x1758, 0x420);
DI_Wr(0x1759, 0xa06664);
DI_Wr(0x175a, 0xe0000);
DI_Wr(0x175b, 0x991c00);
DI_Wr(0x175c, 0x991000);
DI_Wr(0x175d, 0xf9f3e);
DI_Wr(0x175e, 0x7292abcd);
DI_Wr(0x175f, 0x1c23314f);
DI_Wr(0x1760, 0xf111317);
DI_Wr(0x1761, 0x8090a0c);
DI_Wr(0x1762, 0x80a0e0ff);
DI_Wr(0x1763, 0x4102050);
DI_Wr(0x1764, 0x2);
DI_Wr(0x1765, 0x0);
DI_Wr(0x1766, 0x20100400);
DI_Wr(0x1767, 0xc4804030);
DI_Wr(0x1768, 0xfffff0e0);
DI_Wr(0x1769, 0xffffffff);
DI_Wr(0x176a, 0x1132);
DI_Wr(0x176b, 0x32020);
DI_Wr(0x176c, 0x3333);
DI_Wr(0x176d, 0x4b4e4b4d);
DI_Wr(0x176e, 0x111);
DI_Wr(0x176f, 0x32181818);
DI_Wr(0x1770, 0x80644032);
DI_Wr(0x1771, 0x9e808080);
DI_Wr(0x1772, 0xffffffff);
DI_Wr(0x1773, 0x32181818);
DI_Wr(0x1774, 0x80644032);
DI_Wr(0x1775, 0xa5808080);
DI_Wr(0x1776, 0xffffffff);
DI_Wr(0x1777, 0xa06663);
DI_Wr(0x1778, 0x372);
DI_Wr(0x1779, 0x14141414);
DI_Wr(0x177a, 0x1400);
DI_Wr(0x177b, 0x80064);
DI_Wr(0x177c, 0x80064);
DI_Wr(0x177d, 0x80a0a);
DI_Wr(0x177e, 0x4281e);
DI_Wr(0x177f, 0x0);
DI_Wr(0x179c, 0x11b);
DI_Wr(0x179d, 0x202220);
}
void nr_init(struct device *dev)
{
dnr_prm_init(&dnr_param);
device_create_file(dev, &dev_attr_dnr_param);
}

1157
drivers/amlogic/media/deinterlace/nr_drv.c Normal file
View File

File diff suppressed because it is too large Load Diff

60
drivers/amlogic/media/deinterlace/nr.h → drivers/amlogic/media/deinterlace/nr_drv.h
View File

@@ -1,5 +1,5 @@
/*
* drivers/amlogic/media/deinterlace/nr.h
* drivers/amlogic/media/deinterlace/nr_drv.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
@@ -18,14 +18,15 @@
#ifndef _DNR_H
#define _DNR_H
struct dnr_param_s {
struct nr_param_s {
char *name;
int *addr;
};
#define dnr_param_t struct dnr_param_s
#define dnr_param_t struct nr_param_s
#define nr4_param_t struct nr_param_s
struct DNR_PRM_s {
struct DNR_PARM_s {
int prm_sw_gbs_ctrl;
int prm_gbs_vldcntthd;
int prm_gbs_cnt_min;
@@ -51,11 +52,44 @@ struct DNR_PRM_s {
int sw_vbof;
int sw_vbof_vld_flg;
int sw_vbof_vld_cnt;
int dnr_stat_coef;
};/* used for software */
#define DNR_PRM_t struct DNR_PRM_s
/* software parameters initialization£¬ initializing before used */
void nr_init(struct device *dev);
void di_nr_init(void);
#define DNR_PRM_t struct DNR_PARM_s
struct NR4_PARM_s {
int prm_nr4_srch_stp;
int sw_nr4_field_sad[2];
int sw_nr4_scene_change_thd;
int sw_nr4_scene_change_flg[3];
int sw_nr4_sad2gain_en;
int sw_nr4_sad2gain_lut[16];
int nr4_debug;
unsigned short width;
unsigned short height;
unsigned short border_offset;
};
struct CUE_PARM_s {
int glb_mot_framethr;
int glb_mot_fieldnum;
int glb_mot_fieldthr;
int field_count;
int frame_count;
};
struct NR_PARM_s {
unsigned short width;
unsigned short height;
unsigned short frame_count;
bool prog_flag;
struct DNR_PARM_s *pdnr_parm;
struct NR4_PARM_s *pnr4_parm;
struct CUE_PARM_s *pcue_parm;
};
#ifndef SGN2
#define SGN2(x) ((x) > 0 ? 1 : ((x) < 0 ? -1 : 0))
#endif
int global_bs_calc_sw(int *pGbsVldCnt,
int *pGbsVldFlg,
int *pGbs,
@@ -110,6 +144,14 @@ int ver_blk_ofst_calc_sw(int *pVbOfVldCnt,
int prm_vbof_vldcntthd,
int nRow,
int nCol);
void run_dnr_in_irq(unsigned short nCol, unsigned short nRow);
/* software parameters initialization before used */
void adaptive_cue_adjust(unsigned int frame_diff, unsigned int field_diff);
void nr_hw_init(void);
void nr_gate_control(bool gate);
void nr_drv_init(struct device *dev);
void nr_drv_uninit(struct device *dev);
void nr_process_in_irq(void);
void nr_all_config(unsigned short nCol, unsigned short nRow,
unsigned short type);
#endif

519
drivers/amlogic/media/deinterlace/pulldown_drv.c Normal file
View File

@@ -0,0 +1,519 @@
/*
* drivers/amlogic/media/deinterlace/pulldown_drv.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/device.h>
#include "deinterlace_hw.h"
#include "deinterlace_dbg.h"
static unsigned int field_diff_rate;
static unsigned int flm22_sure_num = 100;
static unsigned int flm22_sure_smnum = 70;
static unsigned int flm22_ratio = 200;
/* 79 for iptv test pd22 ts */
module_param_named(flm22_ratio, flm22_ratio, uint, 0644);
static struct sFlmSftPar pd_param;
static struct FlmDectRes dectres;
static struct FlmModReg_t flmreg;
static void pulldown_mode_init(struct pulldown_detected_s *pd_config)
{
unsigned int i = 0;
pd_config->global_mode =
PULL_DOWN_NORMAL;
for (i = 0; i < MAX_VOF_WIN_NUM; i++) {
pd_config->regs[i].win_vs = 0;
pd_config->regs[i].win_ve = 0;
pd_config->regs[i].blend_mode =
PULL_DOWN_NORMAL;
}
}
static void pulldown_wnd_config(struct pulldown_detected_s *pd_config,
unsigned short **wins)
{
unsigned int i = 0;
for (i = 0; i < MAX_VOF_WIN_NUM; i++) {
pd_config->regs[i].win_vs = wins[i][0];
pd_config->regs[i].win_ve = wins[i][1];
pd_config->regs[i].blend_mode = wins[i][2];
}
}
void pulldown_vof_win_vshift(struct pulldown_detected_s *wins,
unsigned short v_offset)
{
unsigned int i = 0;
for (i = 0; i < MAX_VOF_WIN_NUM; i++) {
if (wins->regs[0].win_vs > v_offset)
wins->regs[0].win_vs -= v_offset;
else
wins->regs[0].win_vs = 0;
if (wins->regs[0].win_ve > v_offset)
wins->regs[0].win_ve -= v_offset;
else
wins->regs[0].win_ve = 0;
}
}
static int flag_di_weave = 1;
static unsigned int pldn_mod;
static unsigned int pldn_cmb0 = 1;
module_param_named(pldn_cmb0, pldn_cmb0, uint, 0644);
static unsigned int pldn_cmb1;
module_param_named(pldn_cmb1, pldn_cmb1, uint, 0644);
/* static unsigned int flmxx_sure_num[7]
* = {50, 50, 50, 50, 50, 50, 50};
*/
static unsigned int flmxx_sure_num[7] = {20, 20, 20, 20, 20, 20, 20};
static unsigned int flmxx_snum_adr = 7;
module_param_array(flmxx_sure_num, uint, &flmxx_snum_adr, 0664);
static unsigned int flm22_glbpxlnum_rat = 4; /* 4/256 = 64 */
static unsigned int flm22_glbpxl_maxrow = 16; /* 16/256 = 16 */
module_param(flm22_glbpxl_maxrow, uint, 0644);
MODULE_PARM_DESC(flm22_glbpxl_maxrow, "flm22_glbpxl_maxrow/n");
static unsigned int flm22_glbpxl_minrow = 3; /* 4/256 = 64 */
module_param(flm22_glbpxl_minrow, uint, 0644);
MODULE_PARM_DESC(flm22_glbpxl_minrow, "flm22_glbpxl_minrow/n");
static unsigned int cmb_3point_rnum;
module_param(cmb_3point_rnum, uint, 0644);
MODULE_PARM_DESC(cmb_3point_rnum, "cmb_3point_rnum/n");
static unsigned int cmb_3point_rrat = 32;
module_param(cmb_3point_rrat, uint, 0644);
MODULE_PARM_DESC(cmb_3point_rrat, "cmb_3point_rrat/n");
unsigned int pulldown_detection(struct pulldown_detected_s *res,
struct combing_status_s *cmb_sts, bool reverse)
{
unsigned int glb_frame_mot_num, glb_field_mot_num, i;
unsigned int mot_row = 0, mot_max = 0, ntmp = 0;
unsigned int flm22_surenum = flm22_sure_num;
int difflag = 2;
bool flm32 = false, flm22 = false, flmxx = false;
read_pulldown_info(&glb_frame_mot_num,
&glb_field_mot_num);
read_new_pulldown_info(&flmreg);
dectres.rF22Flag = FlmVOFSftTop(&(dectres.rCmb32Spcl),
dectres.rPstCYWnds[0],
dectres.rPstCYWnds[1],
dectres.rPstCYWnds[2],
dectres.rPstCYWnds[3],
dectres.rPstCYWnds[4],
&(dectres.rFlmPstGCm),
&(dectres.rFlmSltPre),
&(dectres.rFlmPstMod),
&(dectres.dif01flag),
flmreg.rROFldDif01,
flmreg.rROFrmDif02,
flmreg.rROCmbInf,
glb_frame_mot_num,
glb_field_mot_num,
&cmb_sts->cmb_row_num,
&cmb_sts->frame_diff_avg,
&pd_param,
reverse);
difflag = dectres.dif01flag;
if (dectres.rFlmPstMod == 1)
difflag = dectres.rFlmSltPre;
if (pd_param.height >= 289) /*full hd */
cmb_sts->cmb_row_num = cmb_sts->cmb_row_num << 1;
if (cmb_sts->cmb_row_num > pd_param.height)
cmb_sts->cmb_row_num = pd_param.height;
prt_flg = ((pr_pd >> 1) & 0x1);
if (prt_flg) {
sprintf(debug_str, "#Pst-Dbg:\n");
sprintf(debug_str + strlen(debug_str),
"Mod=%d, Pre=%d, GCmb=%d, Lvl2=%d\n",
dectres.rFlmPstMod,
dectres.rFlmSltPre,
dectres.rFlmPstGCm,
dectres.rF22Flag);
sprintf(debug_str + strlen(debug_str),
"N%03d: nd[%d~%d], [%d~%d], [%d~%d], [%d~%d]\n",
cmb_sts->cmb_row_num,
dectres.rPstCYWnds[0][0],
dectres.rPstCYWnds[0][1],
dectres.rPstCYWnds[1][0],
dectres.rPstCYWnds[1][1],
dectres.rPstCYWnds[2][0],
dectres.rPstCYWnds[2][1],
dectres.rPstCYWnds[3][0],
dectres.rPstCYWnds[3][1]);
pr_info("%s", debug_str);
}
pulldown_mode_init(res);
if (difflag == 1 && flag_di_weave)
res->global_mode = PULL_DOWN_NORMAL;
else if (difflag == 0 && flag_di_weave == 1)
res->global_mode = PULL_DOWN_NORMAL_2;
if (dectres.rFlmPstMod == 1)
cmb_sts->like_pulldown22_flag = dectres.rF22Flag;
else
cmb_sts->like_pulldown22_flag = 0;
if ((pr_pd >> 1) & 0x1)
pr_info("fld_dif_rat=%d\n",
field_diff_rate);
if ((dectres.rF22Flag >=
(cmb_3point_rnum + field_diff_rate)) &&
(cmb_sts->cmb_row_num >
(pd_param.height * cmb_3point_rrat >> 8))) {
if ((pr_pd >> 1) & 0x1)
pr_info("coeff-3-point enabled\n");
}
if (dectres.rFlmPstMod != 0) {
flm32 = (dectres.rFlmPstMod == 2 &&
dectres.rFlmPstGCm == 0);
ntmp = (glb_frame_mot_num + glb_field_mot_num) /
(pd_param.width + 1);
if (flm22_sure_num > ntmp + flm22_sure_smnum)
flm22_surenum = flm22_sure_num - ntmp;
else
flm22_surenum = flm22_sure_smnum;
if (dectres.rFlmPstMod == 1) {
mot_row = glb_frame_mot_num *
flm22_glbpxlnum_rat / (pd_param.width + 1);
mot_max = (flm22_glbpxl_maxrow *
pd_param.height + 128) >> 8;
if ((pr_pd >> 1) & 0x1)
pr_info("dejaggies level=%3d - (%02d - %02d)\n",
dectres.rF22Flag,
mot_max, mot_row);
if (mot_row < mot_max) {
if (dectres.rF22Flag >
(mot_max - mot_row))
dectres.rF22Flag -=
(mot_max - mot_row);
else
dectres.rF22Flag = 0;
if (mot_row <= flm22_glbpxl_minrow)
dectres.rFlmPstMod = 0;
}
}
flm22 = (dectres.rFlmPstMod == 1 &&
dectres.rF22Flag >= flm22_surenum);
if (dectres.rFlmPstMod >= 4)
flmxx = (dectres.rF22Flag >=
flmxx_sure_num[dectres.rFlmPstMod - 4]);
else
flmxx = 0;
/* 2-2 force */
if ((pldn_mod == 0) &&
(flm32 || flm22 || flmxx)) {
if (dectres.rFlmSltPre == 1)
res->global_mode =
PULL_DOWN_BLEND_0;
else {
res->global_mode =
PULL_DOWN_BLEND_2;
}
} else if (pldn_mod == 1) {
if (dectres.rFlmSltPre == 1)
res->global_mode =
PULL_DOWN_BLEND_0;
else
res->global_mode =
PULL_DOWN_BLEND_2;
} else {
if (difflag == 1 && flag_di_weave) {
res->global_mode
= PULL_DOWN_NORMAL;
} else if (difflag == 0 &&
flag_di_weave) {
res->global_mode
= PULL_DOWN_NORMAL_2;
} else {
res->global_mode
= PULL_DOWN_NORMAL;
}
}
if (flm32 && (pldn_cmb0 == 1)) {
pulldown_wnd_config(res,
(unsigned short **)dectres.rPstCYWnds);
} else if (dectres.rF22Flag > 1 &&
dectres.rFlmPstMod == 1 &&
pldn_cmb0 == 1) {
if ((pr_pd >> 1) & 0x1)
pr_info("dejaggies level= %3d\n",
dectres.rF22Flag);
} else if (dectres.rFlmPstGCm == 0 &&
pldn_cmb0 > 1 && pldn_cmb0 <= 5) {
pulldown_wnd_config(res,
(unsigned short **)dectres.rPstCYWnds);
/* 1-->only film-mode
* 2-->windows-->mtn
* 3-->windows-->detected
* 4-->windows-->di
*/
/* pldn_cmb0 == 2
* setting in pulldown wnd config
*/
if (pldn_cmb0 == 3) {
for (i = 0; i < MAX_VOF_WIN_NUM; i++)
res->regs[i].blend_mode = 3;
} else if (pldn_cmb0 == 4) {
for (i = 0; i < MAX_VOF_WIN_NUM; i++)
res->regs[i].blend_mode = 2;
} else if (pldn_cmb0 == 5) {
res->regs[3].win_vs = 0;
res->regs[3].win_ve = 60;
res->regs[3].blend_mode = 0;
}
}
/* else pldn_cmb0==0 (Nothing) */
if ((dectres.rFlmPstGCm == 1) && (pldn_cmb1 > 0)
&& (pldn_cmb1 <= 5)) {
pulldown_wnd_config(res,
(unsigned short **)dectres.rPstCYWnds);
/*
* 1-->normal set in pulldown
* wnd config func
*/
if (pldn_cmb1 == 2) {
for (i = 0; i < MAX_VOF_WIN_NUM; i++)
res->regs[i].blend_mode = 3;
} else if (pldn_cmb1 == 3) {
for (i = 0; i < MAX_VOF_WIN_NUM; i++)
res->regs[i].blend_mode = 2;
} else if (pldn_cmb1 == 4) {
res->regs[2].win_vs = 202;
res->regs[2].win_ve = 222;
res->regs[2].blend_mode = 0;
}
} else if ((pldn_cmb0 == 6) && (pldn_cmb1 == 6)) {
res->regs[1].win_vs = 60;
res->regs[1].win_ve = 180;
res->regs[1].blend_mode = 0;
}
}
return 0;
}
unsigned char pulldown_init(unsigned short width, unsigned short height)
{
flm22_sure_num = (height * 100)/480;
flm22_sure_smnum = (flm22_sure_num * flm22_ratio)/100;
pd_param.width = width;
pd_param.height = height;
pd_param.field_count = 0;
return FlmVOFSftInt(&pd_param);
}
struct pd_param_s {
char *name;
int *addr;
};
static struct pd_param_s pd_params[] = {
{ "sFrmDifAvgRat",
&(pd_param.sFrmDifAvgRat)},
{ "sFrmDifLgTDif",
&(pd_param.sFrmDifLgTDif) },
{ "sF32StpWgt01",
&(pd_param.sF32StpWgt01) },
{ "sF32StpWgt02",
&(pd_param.sF32StpWgt02) },
{ "sF32DifLgRat",
&(pd_param.sF32DifLgRat) },
{ "sFlm2MinAlpha",
&(pd_param.sFlm2MinAlpha) },
{ "sFlm2MinBelta",
&(pd_param.sFlm2MinBelta) },
{ "sFlm20ftAlpha",
&(pd_param.sFlm20ftAlpha) },
{ "sFlm2LgDifThd",
&(pd_param.sFlm2LgDifThd) },
{ "sFlm2LgFlgThd",
&(pd_param.sFlm2LgFlgThd) },
{ "sF32Dif01A1",
&(pd_param.sF32Dif01A1) },
{ "sF32Dif01T1",
&(pd_param.sF32Dif01T1) },
{ "sF32Dif01A2",
&(pd_param.sF32Dif01A2) },
{ "sF32Dif01T2",
&(pd_param.sF32Dif01T2) },
{ "rCmbRwMinCt0",
&(pd_param.rCmbRwMinCt0) },
{ "rCmbRwMinCt1",
&(pd_param.rCmbRwMinCt1) },
{ "mPstDlyPre",
&(pd_param.mPstDlyPre) },
{ "mNxtDlySft",
&(pd_param.mNxtDlySft) },
{ "cmb22_nocmb_num",
&(pd_param.cmb22_nocmb_num)},
{ "flm22_en",
&(pd_param.flm22_en) },
{ "flm32_en",
&(pd_param.flm32_en) },
{ "flm22_flag",
&(pd_param.flm22_flag) },
{ "flm2224_flag",
&(pd_param.flm2224_flag) },
{ "flm22_comlev",
&(pd_param.flm22_comlev) },
{ "flm22_comlev1",
&(pd_param.flm22_comlev1) },
{ "flm22_comnum",
&(pd_param.flm22_comnum) },
{ "flm22_comth",
&(pd_param.flm22_comth) },
{ "flm22_dif01_avgth",
&(pd_param.flm22_dif01_avgth) },
{ "dif01rate",
&(pd_param.dif01rate) },
{ "flag_di01th",
&(pd_param.flag_di01th) },
{ "numthd",
&(pd_param.numthd) },
{ "sF32Dif02M0",
&(pd_param.sF32Dif02M0) }, /* mpeg-4096, cvbs-8192 */
{ "sF32Dif02M1",
&(pd_param.sF32Dif02M1) }, /* mpeg-4096, cvbs-8192 */
{ "", NULL }
};
static ssize_t pd_parm_store(struct device *dev,
struct device_attribute *attr, const char *buff,
size_t count)
{
int i = 0;
int value = 0;
int rc = 0;
char *parm[2] = { NULL }, *buf_orig;
buf_orig = kstrdup(buff, GFP_KERNEL);
parse_cmd_params(buf_orig, (char **)(&parm));
for (i = 0; pd_params[i].addr; i++) {
if (!strcmp(parm[0], pd_params[i].name)) {
rc = kstrtoint(parm[1], 10, &value);
*(pd_params[i].addr) = value;
pr_dbg("%s=%d.\n", pd_params[i].name, value);
}
}
return count;
}
static ssize_t pd_parm_show(struct device *dev,
struct device_attribute *attr, char *buff)
{
ssize_t len = 0;
int i = 0;
for (i = 0; pd_params[i].addr; i++) {
len += sprintf(buff + len, "%s=%d.\n",
pd_params[i].name, *pd_params[i].addr);
}
len += sprintf(buff + len, "\npulldown detection result:\n");
len += sprintf(buff + len, "rPstCYWnd0 s=%u.\n",
dectres.rPstCYWnds[0][0]);
len += sprintf(buff + len, "rPstCYWnd0 e=%u.\n",
dectres.rPstCYWnds[0][1]);
len += sprintf(buff + len, "rPstCYWnd0 b=%u.\n",
dectres.rPstCYWnds[0][2]);
len += sprintf(buff + len, "rPstCYWnd1 s=%u.\n",
dectres.rPstCYWnds[1][0]);
len += sprintf(buff + len, "rPstCYWnd1 e=%u.\n",
dectres.rPstCYWnds[1][1]);
len += sprintf(buff + len, "rPstCYWnd1 b=%u.\n",
dectres.rPstCYWnds[1][2]);
len += sprintf(buff + len, "rPstCYWnd2 s=%u.\n",
dectres.rPstCYWnds[2][0]);
len += sprintf(buff + len, "rPstCYWnd2 e=%u.\n",
dectres.rPstCYWnds[2][1]);
len += sprintf(buff + len, "rPstCYWnd2 b=%u.\n",
dectres.rPstCYWnds[2][2]);
len += sprintf(buff + len, "rPstCYWnd3 s=%u.\n",
dectres.rPstCYWnds[3][0]);
len += sprintf(buff + len, "rPstCYWnd3 e=%u.\n",
dectres.rPstCYWnds[3][1]);
len += sprintf(buff + len, "rPstCYWnd3 b=%u.\n",
dectres.rPstCYWnds[3][2]);
len += sprintf(buff + len, "rPstCYWnd4 s=%u.\n",
dectres.rPstCYWnds[4][0]);
len += sprintf(buff + len, "rPstCYWnd4 e=%u.\n",
dectres.rPstCYWnds[4][1]);
len += sprintf(buff + len, "rPstCYWnd4 b=%u.\n",
dectres.rPstCYWnds[4][2]);
len += sprintf(buff + len, "rFlmPstGCm=%u.\n",
dectres.rFlmPstGCm);
len += sprintf(buff + len, "rFlmSltPre=%u.\n",
dectres.rFlmSltPre);
len += sprintf(buff + len, "rFlmPstMod=%d.\n",
dectres.rFlmPstMod);
len += sprintf(buff + len, "rFlmPstMod=%d.\n",
dectres.dif01flag);
len += sprintf(buff + len, "rF22Flag=%d.\n",
dectres.rF22Flag);
return len;
}
static DEVICE_ATTR(pd_param, 0664, pd_parm_show, pd_parm_store);
void pd_device_files_add(struct device *dev)
{
device_create_file(dev, &dev_attr_pd_param);
}
void pd_device_files_del(struct device *dev)
{
device_create_file(dev, &dev_attr_pd_param);
}
#ifdef DEBUG_SUPPORT
module_param_named(flm22_sure_num, flm22_sure_num, uint, 0644);
module_param_named(flm22_glbpxlnum_rat, flm22_glbpxlnum_rat, uint, 0644);
module_param_named(flag_di_weave, flag_di_weave, int, 0644);
#endif

57
drivers/amlogic/media/deinterlace/pulldown_drv.h Normal file
View File

@@ -0,0 +1,57 @@
/*
* drivers/amlogic/media/deinterlace/pulldown_drv.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef _DI_PULLDOWN_H
#define _DI_PULLDOWN_H
#include "film_mode_fmw/film_vof_soft.h"
#include "deinterlace_mtn.h"
#define MAX_VOF_WIN_NUM 4
enum pulldown_mode_e {
PULL_DOWN_BLEND_0 = 0,/* buf1=dup[0] */
PULL_DOWN_BLEND_2 = 1,/* buf1=dup[2] */
PULL_DOWN_MTN = 2,/* mtn only */
PULL_DOWN_BUF1 = 3,/* do wave with dup[0] */
PULL_DOWN_EI = 4,/* ei only */
PULL_DOWN_NORMAL = 5,/* normal di */
PULL_DOWN_NORMAL_2 = 6,/* di */
};
struct pulldown_vof_win_s {
unsigned short win_vs;
unsigned short win_ve;
enum pulldown_mode_e blend_mode;
};
struct pulldown_detected_s {
enum pulldown_mode_e global_mode;
struct pulldown_vof_win_s regs[4];
};
unsigned char pulldown_init(unsigned short width, unsigned short height);
unsigned int pulldown_detection(struct pulldown_detected_s *res,
struct combing_status_s *cmb_sts, bool reverse);
void pulldown_vof_win_vshift(struct pulldown_detected_s *wins,
unsigned short v_offset);
void pd_device_files_add(struct device *dev);
void pd_device_files_del(struct device *dev);
#endif

102
drivers/amlogic/media/deinterlace/register.h
View File

@@ -17,6 +17,7 @@
#ifndef __MACH_DEINTERLACE_REG_ADDR_H_
#define __MACH_DEINTERLACE_REG_ADDR_H_
#include <linux/amlogic/iomap.h>
#define Wr(adr, val) aml_write_vcbus(adr, val)
#define Rd(adr) aml_read_vcbus(adr)
@@ -31,6 +32,13 @@ unsigned int RDMA_WR_BITS(unsigned int adr, unsigned int val,
unsigned int start, unsigned int len);
unsigned int RDMA_RD_BITS(unsigned int adr, unsigned int start,
unsigned int len);
void DI_Wr(unsigned int addr, unsigned int val);
void DI_Wr_reg_bits(unsigned int adr, unsigned int val,
unsigned int start, unsigned int len);
void DI_VSYNC_WR_MPEG_REG(unsigned int addr, unsigned int val);
void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr,
unsigned int val, unsigned int start, unsigned int len);
#define VPU_WRARB_REQEN_SLV_L1C1 ((0x2795)) /* << 2) + 0xd0100000) */
#define VPU_ARB_DBG_STAT_L1C1 ((0x27b4)) /* << 2) + 0xd0100000) */
#define SRSHARP0_SHARP_SR2_CTRL ((0x3257)) /* << 2) + 0xd0100000) */
@@ -152,17 +160,9 @@ unsigned int RDMA_RD_BITS(unsigned int adr, unsigned int start,
* Bit 7:0 Write luma canvas address
*/
/* timerc */
#define ISA_TIMER_MUX 0x2650
/* 0xc1109940 */
#define ISA_TIMERC 0x2653
/* 0xc110994c */
#define ISA_TIMERE 0x2655
/* 0xc1109954 */
/* vd1 */
#define VD1_IF0_LUMA_FIFO_SIZE 0x1a63
/* 0xd010698c */
#define VD2_IF0_LUMA_FIFO_SIZE 0x1a83
/* 0xd0106a0c */
#define VD1_IF0_GEN_REG 0x1a50
#define VD1_IF0_CANVAS0 0x1a51
/* 0xd0106944 */
#define VD1_IF0_CANVAS1 0x1a52
@@ -175,11 +175,50 @@ unsigned int RDMA_RD_BITS(unsigned int adr, unsigned int start,
/* 0xd0106954 */
#define VD1_IF0_CHROMA_Y0 0x1a56
/* 0xd0106958 */
#define VD1_IF0_LUMA_X1 0x1a57
#define VD1_IF0_LUMA_Y1 0x1a58
#define VD1_IF0_CHROMA_X1 0x1a59
#define VD1_IF0_CHROMA_Y1 0x1a5a
#define VD1_IF0_RPT_LOOP 0x1a5b
/* 0xd010696c */
#define VD1_IF0_LUMA0_RPT_PAT 0x1a5c
/* 0xd0106970 */
#define VD1_IF0_CHROMA0_RPT_PAT 0x1a5d
#define VD1_IF0_LUMA0_RPT_PAT 0x1a5c
#define VD1_IF0_CHROMA0_RPT_PAT 0x1a5d
#define VD1_IF0_LUMA1_RPT_PAT 0x1a5e
#define VD1_IF0_CHROMA1_RPT_PAT 0x1a5f
#define VD1_IF0_LUMA_PSEL 0x1a60
#define VD1_IF0_CHROMA_PSEL 0x1a61
#define VD1_IF0_DUMMY_PIXEL 0x1a62
#define VD1_IF0_LUMA_FIFO_SIZE 0x1a63
#define VD1_IF0_RANGE_MAP_Y 0x1a6a
#define VD1_IF0_RANGE_MAP_CB 0x1a6b
#define VD1_IF0_RANGE_MAP_CR 0x1a6c
#define VD1_IF0_GEN_REG2 0x1a6d
#define VD1_IF0_PROT_CNTL 0x1a6e
#define VIU_VD1_FMT_CTRL 0x1a68
#define VIU_VD1_FMT_W 0x1a69
#define VD1_IF0_LUMA_FIFO_SIZE 0x1a63
/* 0xd010698c */
#define VD2_IF0_LUMA_FIFO_SIZE 0x1a83
/* 0xd0106a0c */
/* 0xd0106974 */
#define VIU_OSD1_CTRL_STAT 0x1a10
/* 0xd0106840 */
@@ -322,7 +361,10 @@ unsigned int RDMA_RD_BITS(unsigned int adr, unsigned int start,
/* 0xd0106818 */
#define VIUB_MISC_CTRL0 0x2006
/* 0xd0108018 */
/* txl new add begin */
#define VIUB_GCLK_CTRL0 0x2007
#define VIUB_GCLK_CTRL1 0x2008
#define VIUB_GCLK_CTRL2 0x2009
#define VIUB_GCLK_CTRL3 0x200a
#define DI_IF2_GEN_REG 0x2010
#define DI_IF2_CANVAS0 0x2011
#define DI_IF2_LUMA_X0 0x2012
@@ -1384,6 +1426,19 @@ unsigned int RDMA_RD_BITS(unsigned int adr, unsigned int start,
/* Bit 7: 0, reg_CUE_CON_difP1_thrd2 U8, P1 field Intra-Field top/below line
* chroma difference threshold (tighter),
*/
/* change from txlx */
#define DI_EI_DRT_CTRL ((0x1778))
#define DI_EI_DRT_PIXTH ((0x1779))
#define DI_EI_DRT_CORRPIXTH ((0x177a))
#define DI_EI_DRT_RECTG_WAVE ((0x177b))
#define DI_EI_DRT_PIX_DIFFTH ((0x177c))
#define DI_EI_DRT_UNBITREND_TH ((0x177d))
#define NR2_CUE_PRG_DIF ((0x177e)) /* << 2) + 0xd0100000) */
/* Bit 20, reg_CUE_PRG_Enable Enable bit for progressive video CUE
* detection.If interlace input video,
@@ -1408,6 +1463,17 @@ unsigned int RDMA_RD_BITS(unsigned int adr, unsigned int start,
/* // NR2 REG DEFINE END //// */
/* // DET 3D REG DEFINE BEGIN //// */
/* // 8'h80~8'h8f */
#define DI_EI_DRT_CTRL_GXLX ((0x2028))
#define DI_EI_DRT_PIXTH_GXLX ((0x2029))
#define DI_EI_DRT_CORRPIXTH_GXLX ((0x202a))
#define DI_EI_DRT_RECTG_WAVE_GXLX ((0x202b))
#define DI_EI_DRT_PIX_DIFFTH_GXLX ((0x202c))
#define DI_EI_DRT_UNBITREND_TH_GXLX ((0x202d))
#define DET3D_RO_SPLT_HB ((0x1780)) /* << 2) + 0xd0100000) */
/* Bit 24, RO_Det3D_Split_HB_valid
* U1 horizontal LR split border detected valid signal for top half picture
@@ -2667,6 +2733,7 @@ unsigned int RDMA_RD_BITS(unsigned int adr, unsigned int start,
#define MCDI_PD_22_CHK_WND0_Y (0x2f5a)
#define MCDI_PD_22_CHK_WND1_X (0x2f5b)
#define MCDI_PD_22_CHK_WND1_Y (0x2f5c)
#define MCDI_PD_22_CHK_FLG_CNT (0x2f5e)
/* mc di */
/* //=================================================================//// */
/* // memc di core 0 */
@@ -4013,6 +4080,10 @@ unsigned int RDMA_RD_BITS(unsigned int adr, unsigned int start,
#define MCDI_MCVECRD_CANVAS_SIZE ((0x2f66))
#define MCDI_MCINFOWR_CANVAS_SIZE ((0x2f67))
#define MCDI_MCINFORD_CANVAS_SIZE ((0x2f68))
#define MCDI_LMVLCKSTEXT_0 ((0x2f69))
#define MCDI_LMVLCKSTEXT_1 ((0x2f6a))
#define MCDI_LMVLCKEDEXT_0 ((0x2f6b))
#define MCDI_LMVLCKEDEXT_1 ((0x2f6c))
#define MCDI_MCVECWR_X ((0x2f92))
#define MCDI_MCVECWR_Y ((0x2f93))
#define MCDI_MCVECWR_CTRL ((0x2f94))
@@ -4491,6 +4562,7 @@ unsigned int RDMA_RD_BITS(unsigned int adr, unsigned int start,
#define DIPD_RO_COMB_18 0x2fe8
#define DIPD_RO_COMB_19 0x2fe9
#define DIPD_RO_COMB_20 0x2fea
#define DIPD_COMB_CTRL6 0x2feb
/* nr3 */
#define NR3_MODE 0x2ff0
/* d010bfc0 */

149
drivers/amlogic/media/deinterlace/register_nr4.h Normal file
View File

@@ -0,0 +1,149 @@
/*
* drivers/amlogic/media/deinterlace/register_nr4.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#define NR4_DRT_CTRL ((0x2da4))
#define NR4_DRT_YSAD_GAIN ((0x2da5))
#define NR4_DRT_CSAD_GAIN ((0x2da6))
#define NR4_DRT_SAD_ALP_CORE ((0x2da7))
#define NR4_DRT_ALP_MINMAX ((0x2da8))
#define NR4_SNR_CTRL_REG ((0x2da9))
#define NR4_SNR_ALPHA0_MAX_MIN ((0x2daa))
#define NR4_ALP0C_ERR2CURV_LIMIT0 ((0x2dab))
#define NR4_ALP0C_ERR2CURV_LIMIT1 ((0x2dac))
#define NR4_ALP0Y_ERR2CURV_LIMIT0 ((0x2dad))
#define NR4_ALP0Y_ERR2CURV_LIMIT1 ((0x2dae))
#define NR4_SNR_ALPA1_RATE_AND_OFST ((0x2daf))
#define NR4_SNR_ALPHA1_MAX_MIN ((0x2db0))
#define NR4_ALP1C_ERR2CURV_LIMIT0 ((0x2db1))
#define NR4_ALP1C_ERR2CURV_LIMIT1 ((0x2db2))
#define NR4_ALP1Y_ERR2CURV_LIMIT0 ((0x2db3))
#define NR4_ALP1Y_ERR2CURV_LIMIT1 ((0x2db4))
#define NR4_MTN_CTRL ((0x2db5))
#define NR4_MTN_REF_PAR0 ((0x2db6))
#define NR4_MTN_REF_PAR1 ((0x2db7))
#define NR4_MCNR_LUMA_ENH_CTRL ((0x2db8))
#define NR4_MCNR_LUMA_STAT_LIMTX ((0x2db9))
#define NR4_MCNR_LUMA_STAT_LIMTY ((0x2dba))
#define NR4_MCNR_LUMA_DIF_CALC ((0x2dbb))
#define NR4_MCNR_LUMAPRE_CAL_PRAM ((0x2dbc))
#define NR4_MCNR_LUMACUR_CAL_PRAM ((0x2dbd))
#define NR4_MCNR_MV_CTRL_REG ((0x2dbe))
#define NR4_MCNR_MV_GAIN0 ((0x2dbf))
#define NR4_MCNR_LMV_PARM ((0x2dc0))
#define NR4_MCNR_ALP0_REG (0x2dc1)
#define NR4_MCNR_ALP1_AND_BET0_REG (0x2dc2)
#define NR4_MCNR_BET1_AND_BET2_REG (0x2dc3)
#define NR4_MCNR_AC_DC_CRTL (0x2dc4)
#define NR4_MCNR_CM_CTRL0 (0x2dc5)
#define NR4_MCNR_CM_PRAM (0x2dc6)
#define NR4_MCNR_CM_RSHFT_ALP0 (0x2dc7)
#define NR4_MCNR_BLUE_CENT (0x2dc8)
#define NR4_MCNR_BLUE_GAIN_PAR0 (0x2dc9)
#define NR4_MCNR_BLUE_GAIN_PAR1 (0x2dca)
#define NR4_MCNR_CM_BLUE_CLIP0 (0x2dcb)
#define NR4_MCNR_CM_BLUE_CLIP1 (0x2dcc)
#define NR4_MCNR_GREEN_CENT (0x2dcd)
#define NR4_MCNR_GREEN_GAIN_PAR0 (0x2dce)
#define NR4_MCNR_GREEN_GAIN_PAR1 (0x2dcf)
#define NR4_MCNR_GREEN_CLIP0 (0x2dd0)
#define NR4_MCNR_GREEN_CLIP2 (0x2dd1)
#define NR4_MCNR_SKIN_CENT (0x2dd2)
#define NR4_MCNR_SKIN_GAIN_PAR0 (0x2dd3)
#define NR4_MCNR_SKIN_GAIN_PAR1 (0x2dd4)
#define NR4_MCNR_SKIN_CLIP0 (0x2dd5)
#define NR4_MCNR_SKIN_CLIP1 (0x2dd6)
#define NR4_MCNR_ALP1_GLB_CTRL (0x2dd7)
#define NR4_MCNR_DC2NORM_LUT0 (0x2dd8)
#define NR4_MCNR_DC2NORM_LUT1 (0x2dd9)
#define NR4_MCNR_DC2NORM_LUT2 (0x2dda)
#define NR4_MCNR_AC2NORM_LUT0 (0x2ddb)
#define NR4_MCNR_AC2NORM_LUT1 (0x2ddc)
#define NR4_MCNR_AC2NORM_LUT2 (0x2ddd)
#define NR4_MCNR_SAD2ALP0_LUT0 (0x2dde)
#define NR4_MCNR_SAD2ALP0_LUT1 (0x2ddf)
#define NR4_MCNR_SAD2ALP0_LUT2 (0x2de0)
#define NR4_MCNR_SAD2ALP0_LUT3 (0x2de1)
#define NR4_MCNR_SAD2ALP1_LUT0 (0x2de2)
#define NR4_MCNR_SAD2ALP1_LUT1 (0x2de3)
#define NR4_MCNR_SAD2ALP1_LUT2 (0x2de4)
#define NR4_MCNR_SAD2ALP1_LUT3 (0x2de5)
#define NR4_MCNR_SAD2BET0_LUT0 (0x2de6)
#define NR4_MCNR_SAD2BET0_LUT1 (0x2de7)
#define NR4_MCNR_SAD2BET0_LUT2 (0x2de8)
#define NR4_MCNR_SAD2BET0_LUT3 (0x2de9)
#define NR4_MCNR_SAD2BET1_LUT0 (0x2dea)
#define NR4_MCNR_SAD2BET1_LUT1 (0x2deb)
#define NR4_MCNR_SAD2BET1_LUT2 (0x2dec)
#define NR4_MCNR_SAD2BET1_LUT3 (0x2ded)
#define NR4_MCNR_SAD2BET2_LUT0 (0x2dee)
#define NR4_MCNR_SAD2BET2_LUT1 (0x2def)
#define NR4_MCNR_SAD2BET2_LUT2 (0x2df0)
#define NR4_MCNR_SAD2BET2_LUT3 (0x2df1)
#define NR4_MCNR_RO_U_SUM (0x2df2)
#define NR4_MCNR_RO_V_SUM (0x2df3)
#define NR4_MCNR_RO_GRDU_SUM (0x2df4)
#define NR4_MCNR_RO_GRDV_SUM (0x2df5)
#define NR4_TOP_CTRL (0x2dff)
#define NR4_MCNR_SAD_GAIN (0x3700)
#define NR4_MCNR_LPF_CTRL (0x3701)
#define NR4_MCNR_BLD_VS3LUT0 (0x3702)
#define NR4_MCNR_BLD_VS3LUT1 (0x3703)
#define NR4_MCNR_BLD_VS3LUT2 (0x3704)
#define NR4_MCNR_BLD_VS2LUT0 (0x3705)
#define NR4_MCNR_BLD_VS2LUT1 (0x3706)
#define NR4_COEFBLT_LUT10 (0x3707)
#define NR4_COEFBLT_LUT11 (0x3708)
#define NR4_COEFBLT_LUT12 (0x3709)
#define NR4_COEFBLT_LUT20 (0x370a)
#define NR4_COEFBLT_LUT21 (0x370b)
#define NR4_COEFBLT_LUT22 (0x370c)
#define NR4_COEFBLT_LUT30 (0x370d)
#define NR4_COEFBLT_LUT31 (0x370e)
#define NR4_COEFBLT_LUT32 (0x370f)
#define NR4_COEFBLT_CONV (0x3710)
#define NR4_DBGWIN_YX0 (0x3711)
#define NR4_DBGWIN_YX1 (0x3712)
#define NR4_NM_X_CFG (0x3713)
#define NR4_NM_Y_CFG (0x3714)
#define NR4_NM_SAD_THD (0x3715)
#define NR4_MCNR_BANDSPLIT_PRAM (0x3716)
#define NR4_MCNR_ALP1_SGN_COR (0x3717)
#define NR4_MCNR_ALP1_SGN_PRAM (0x3718)
#define NR4_MCNR_ALP1_MVX_LUT1 (0x3719)
#define NR4_MCNR_ALP1_MVX_LUT2 (0x371a)
#define NR4_MCNR_ALP1_MVX_LUT3 (0x371b)
#define NR4_MCNR_ALP1_LP_PRAM (0x371c)
#define NR4_MCNR_ALP1_SGN_LUT1 (0x371d)
#define NR4_MCNR_ALP1_SGN_LUT2 (0x371e)
#define NR4_RO_NM_SAD_SUM (0x371f)
#define NR4_RO_NM_SAD_CNT (0x3720)
#define NR4_RO_NM_VAR_SUM (0x3721)
#define NR4_RO_NM_VAR_SCNT (0x3722)
#define NR4_RO_NM_VAR_MIN_MAX (0x3723)
#define NR4_RO_NR4_DBGPIX_NUM (0x3724)
#define NR4_RO_NR4_BLDVS2_SUM (0x3725)
#define NR4_BLDVS3_SUM (0x3726)
#define NR4_COEF12_SUM (0x3727)
#define NR4_COEF123_SUM (0x3728)
#define NR_DB_FLT_CTRL (0x3738)
#define NR_DB_FLT_YC_THRD (0x3739)
#define NR_DB_FLT_RANDLUT (0x373a)
#define NR_DB_FLT_PXI_THRD (0x373b)
#define NR_DB_FLT_SEED_Y (0x373c)
#define NR_DB_FLT_SEED_V (0x373e)
#define NR_DB_FLT_SEED3 (0x373f)
#define LBUF_TOP_CTRL (0x2fff)

229
drivers/amlogic/media/deinterlace/tffbff_check.c
View File

@@ -1,229 +0,0 @@
/*
* drivers/amlogic/media/deinterlace/tffbff_check.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/module.h>
#include <linux/types.h>
#include "deinterlace.h"
#include "register.h"
/* define the length of history */
#define TBFF_DLEN 20
/* parameters */
/* valid data: only pixel_num > size*rat >> 8 */
/* u8: [0,255] */
static int tbff_pixel_minnum = 16;
/* x3 / row > rat */
/* => x3 > (row * rat >> 5) */
/* u10: [0 ~ 1023] => [0, 16] */
static int tbff_x3_minrow = 64;
/* m1/p1/m2/p2 changing 0/1/0/1... as 2-2 mode */
/* (max)/ min > (rat): define it max, else min */
/* u8: [0,31] */
static int tbff_mp_lgrat[4] = {16, 16, 16, 16};
/* tbff check length */
/* [0, 31] */
static int tbff_chk_len[4] = {4, 4, 4, 4};
static int calc_tbff_pixel_minnum = 16;
static int calc_tbff_x3_minrow = 64;
static int calc_tbff_mp_lgrat[4] = {16, 16, 16, 16};
static int nTmp0;
static bool tbff_pr, tffbff_en = true;
static int mode_count;
void tbff_init(void)
{
int i = 0;
mode_count = 0;
calc_tbff_pixel_minnum = tbff_pixel_minnum;
calc_tbff_x3_minrow = tbff_x3_minrow;
for (i = 0; i < 4; i++)
calc_tbff_mp_lgrat[i] = tbff_mp_lgrat[i];
}
static int tbff_get_rate(int t0, int t1)
{
int nmax = t1;
int nmin = t0;
int nrst = 0;
if (t0 > t1) {
nmax = t0;
nmin = t1;
}
nrst = (8 * nmax) + (nmin >> 1);
nrst /= (nmin+1);
if (nrst > 31)
nrst = 31;
if (nmax == t1) /* current is small */
nrst = 0;
return nrst;
}
static int tbff_get_minrate(int *pLen)
{
int iT0 = 0;
int aTLn[4] = {0, 0, 0, 0};
int nrst = 255;
int nP0 = pLen[TBFF_DLEN - 1];
int nP1 = pLen[TBFF_DLEN - 2];
if (nP0 < nP1) {
for (iT0 = 0; iT0 < 4; (iT0 += 2)) {
aTLn[iT0] = 31 - pLen[TBFF_DLEN - iT0 - 1];
aTLn[iT0 + 1] = pLen[TBFF_DLEN - iT0 - 2];
}
} else {
for (iT0 = 0; iT0 < 4; (iT0 += 2)) {
aTLn[iT0] = pLen[TBFF_DLEN - iT0 - 1];
aTLn[iT0 + 1] = 31 - pLen[TBFF_DLEN - iT0 - 2];
}
}
for (iT0 = 0; iT0 < 4; iT0++) {
if (aTLn[iT0] < nrst)
nrst = aTLn[iT0];
}
return nrst;
}
/* update param according to detection count */
static void calc_tbff_param(int mode_cnt, int step_max)
{
int delt_num, delt_row, delt_lgrat, i;
delt_num = tbff_pixel_minnum - 4;
delt_row = tbff_x3_minrow;
delt_lgrat = tbff_mp_lgrat[0] - 6;
calc_tbff_pixel_minnum =
tbff_pixel_minnum - (delt_num * mode_cnt)/step_max;
calc_tbff_x3_minrow = tbff_x3_minrow - (delt_row * mode_cnt)/step_max;
calc_tbff_mp_lgrat[0] =
tbff_mp_lgrat[0] - (delt_lgrat * mode_cnt)/step_max;
for (i = 1; i < 4; i++)
calc_tbff_mp_lgrat[i] = calc_tbff_mp_lgrat[0];
}
/* TFF / BFF error check */
/* polar3[0]: num of pixels */
/* polar3[1]: smooth motion vector */
/* polar3[2]: m1 */
/* polar3[3]: p1 */
/* polar3[4]: m2 */
/* polar3[5]: p2 */
/* polar3[6]: x3 */
int tff_bff_check(int nROW, int nCOL)
{
int iT0 = 0, iT1 = 0, nTmp1 = 0;
int nTmp2 = 0, tbfalse = 0, nSIZE = nROW * nCOL;
/* int nMin0 = 0; */
unsigned int uTp0 = 0;
int polar3[7];
/* top/bot field first error */
static int pPolar3[7]; /* previous polar3 */
static int sDat[4][TBFF_DLEN]; /* history infor */
static unsigned int stc_pp3[4];
for (iT0 = 0; iT0 < 7; iT0++)
polar3[iT0] = Rd_reg_bits(NR2_RO_POLAR3_NUMOFPIX+iT0, 0, 24);
if (tbff_pr)
pr_info("polar3=%8d %8d %8d %8d %8d %8d %8d.\n",
polar3[0], polar3[1], polar3[2], polar3[3],
polar3[4], polar3[5], polar3[6]);
/* history */
for (iT0 = 0; iT0 < 4; iT0++) {
for (iT1 = 0; iT1 < (TBFF_DLEN - 1); iT1++)
sDat[iT0][iT1] = sDat[iT0][iT1 + 1];
stc_pp3[iT0] = (stc_pp3[iT0] << 1);
sDat[iT0][TBFF_DLEN - 1] = 0;
}
/* only valid pixel is enough */
nTmp0 = ((nSIZE * calc_tbff_pixel_minnum + 128) >> 8);
if (polar3[0] > nTmp0) {
/* only x3 pixel is enough */
nTmp1 = ((nROW * calc_tbff_x3_minrow + 16) >> 5);
if (polar3[6] > nTmp1) {
/* nMin0 = 255; */
for (iT1 = 0; iT1 < 4; iT1++) {
nTmp2 =
tbff_get_rate(polar3[iT1 + 2], pPolar3[iT1 + 2]);
sDat[iT1][TBFF_DLEN - 1] = nTmp2;
}
}
}
for (iT1 = 0; iT1 < 4; iT1++) {
nTmp2 = tbff_get_minrate(sDat[iT1]);
if (nTmp2 >= calc_tbff_mp_lgrat[iT1])
stc_pp3[iT1] |= 0x1;
}
for (iT1 = 0; iT1 < 4; iT1++) {
uTp0 = stc_pp3[iT1];
nTmp0 = 0;
for (iT0 = 0; iT0 < 31; iT0++) {
if (uTp0 & 0x1)
nTmp0++;
else
break;
uTp0 = (uTp0 >> 1);
}
if (nTmp0 >= tbff_chk_len[iT1])
tbfalse += 1;
}
/* m1/p1/m2/p2 all 2-2 mode */
/* return (tbfalse==4); */
nTmp0 = (tbfalse == 4);
if (nTmp0 == 1)
nTmp0 += (polar3[2] < pPolar3[2]);
if (nTmp0 != 0)
mode_count = mode_count > 32 ? 32 : (mode_count+1);
else
mode_count = mode_count > 0 ? (mode_count-1) : 0;
calc_tbff_param(mode_count, 32);
for (iT0 = 0; iT0 < 7; iT0++)
pPolar3[iT0] = polar3[iT0];
if (tbff_pr)
pr_info("num %d, x3 %d, lgrat %d, result is %d.\n",
calc_tbff_pixel_minnum, calc_tbff_x3_minrow,
calc_tbff_mp_lgrat[0], nTmp0);
return tffbff_en?nTmp0:0;
}
module_param_named(tffbff_en, tffbff_en, bool, 0664);
module_param_named(tbff_pixel_minnum, tbff_pixel_minnum, int, 0664);
module_param_named(tbff_x3_minrow, tbff_x3_minrow, int, 0664);
module_param_named(tbff_pr, tbff_pr, bool, 0664);

40
include/linux/amlogic/media/amvecm/amvecm.h
View File

@@ -20,6 +20,7 @@
#include "linux/amlogic/media/amvecm/ve.h"
#include "linux/amlogic/media/amvecm/cm.h"
#include <linux/amlogic/media/vfm/vframe.h>
#include <linux/amlogic/media/utils/amstream.h>
#include <linux/amlogic/cpu_version.h>
@@ -94,6 +95,34 @@
#define MTX_BYPASS_RGB_OGO (1 << 0)
#define MTX_RGB2YUVL_RGB_OGO (1 << 1)
enum pq_table_name_e {
TABLE_NAME_SHARPNESS0 = 0x1,/*in vpp*/
TABLE_NAME_SHARPNESS1 = 0x2,/*in vpp*/
TABLE_NAME_DNLP = 0x4, /*in vpp*/
TABLE_NAME_CM = 0x8, /*in vpp*/
TABLE_NAME_BLK_BLUE_EXT = 0x10,/*in vpp*/
TABLE_NAME_BRIGHTNESS = 0x20,/*in vpp*/
TABLE_NAME_CONTRAST = 0x40, /*in vpp*/
TABLE_NAME_SATURATION_HUE = 0x80,/*in vpp*/
TABLE_NAME_CVD2 = 0x100, /*in tvafe*/
TABLE_NAME_DI = 0x200, /*in di*/
TABLE_NAME_NR = 0x400, /*in di*/
TABLE_NAME_MCDI = 0x800, /*in di*/
TABLE_NAME_DEBLOCK = 0x1000, /*in di*/
TABLE_NAME_DEMOSQUITO = 0x2000,/*in di*/
TABLE_NAME_WB = 0X4000, /*in vpp*/
TABLE_NAME_GAMMA = 0X8000, /*in vpp*/
TABLE_NAME_XVYCC = 0x10000, /*in vpp*/
TABLE_NAME_HDR = 0x20000, /*in vpp*/
TABLE_NAME_DOLBY_VISION = 0x40000,/*in vpp*/
TABLE_NAME_RESERVED1 = 0x80000,
TABLE_NAME_RESERVED2 = 0x100000,
TABLE_NAME_RESERVED3 = 0x200000,
TABLE_NAME_RESERVED4 = 0x400000,
TABLE_NAME_RESERVED5 = 0x800000,
TABLE_NAME_MAX,
};
#define _VE_CM 'C'
#define AMVECM_IOC_VE_DNLP _IOW(_VE_CM, 0x21, struct ve_dnlp_s)
@@ -126,6 +155,17 @@
#define AMVECM_IOC_3D_SYNC_EN _IO(_VE_CM, 0x49)
#define AMVECM_IOC_3D_SYNC_DIS _IO(_VE_CM, 0x50)
#define _DI_ 'D'
struct am_pq_parm_s {
unsigned int table_name;
unsigned int table_len;
void *table_ptr;
void *reserved;
};
#define AMDI_IOC_SET_PQ_PARM _IOW(_DI_, 0x51, struct am_pq_parm_s)
/* #if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8) */
/* #define WRITE_VPP_REG(x,val)*/
/* WRITE_VCBUS_REG(x,val) */