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arm64: dts: renesas: rzg2l: Drop WDT2 nodes

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On members of the RZ/G2L family, WDT CH2 is specifically meant to check
the operation of the Cortex-M33 CPU.  Using it from a Cortex-A55 CPU
would result in unexpected behaviour.  Hence drop all WDT2 nodes and
their references from the affected SoC and SoM DTSI files.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221009230044.10961-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar
2022-10-10 00:00:40 +01:00
committed by Geert Uytterhoeven
parent 4a76d4ab84
commit c02734d6e4
5 changed files with 0 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
View File

@@ -820,21 +820,6 @@
status = "disabled";
};
wdt2: watchdog@12800400 {
compatible = "renesas,r9a07g043-wdt",
"renesas,rzg2l-wdt";
reg = <0 0x12800400 0 0x400>;
clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>,
<&cpg CPG_MOD R9A07G043_WDT2_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G043_WDT2_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
ostm0: timer@12801000 {
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";

15
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View File

@@ -994,21 +994,6 @@
status = "disabled";
};
wdt2: watchdog@12800400 {
compatible = "renesas,r9a07g044-wdt",
"renesas,rzg2l-wdt";
reg = <0 0x12800400 0 0x400>;
clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>,
<&cpg CPG_MOD R9A07G044_WDT2_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G044_WDT2_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
ostm0: timer@12801000 {
compatible = "renesas,r9a07g044-ostm",
"renesas,ostm";

15
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
View File

@@ -1000,21 +1000,6 @@
status = "disabled";
};
wdt2: watchdog@12800400 {
compatible = "renesas,r9a07g054-wdt",
"renesas,rzg2l-wdt";
reg = <0 0x12800400 0 0x400>;
clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>,
<&cpg CPG_MOD R9A07G054_WDT2_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G054_WDT2_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
ostm0: timer@12801000 {
compatible = "renesas,r9a07g054-ostm",
"renesas,ostm";

5
arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
View File

@@ -351,8 +351,3 @@
status = "okay";
timeout-sec = <60>;
};
&wdt2 {
status = "okay";
timeout-sec = <60>;
};

5
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
View File

@@ -276,8 +276,3 @@
status = "okay";
timeout-sec = <60>;
};
&wdt2 {
status = "okay";
timeout-sec = <60>;
};