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synced 2026-06-07 19:30:30 +09:00
clk: rockchip: add rkclk_init_enable and open rk3288 gating
This commit is contained in:
dkl
@@ -2012,14 +2012,14 @@
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<&dummy>, <&dummy>;
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clock-output-names =
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"reserved", "core_apll",
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"reserved", "reserved", /* do not use bit1 = "core_apll" */
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"clk_arm_gpll", "g_aclk_bus",
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"hclk_bus", "pclk_bus",
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"reserved", "aclk_bus_2pmu",
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"reserved", "reserved", /*"clk_ddr_dpll", "clk_ddr_gpll",*/
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"clk_bus_gpll", "clk_bus_cpll",
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"reserved", "reserved", /*"clk_bus_gpll", "clk_bus_cpll",*/
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"clk_acc_efuse", "reserved",
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"reserved", "reserved";
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@@ -2078,7 +2078,7 @@
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<&dummy>, <&dummy>;
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clock-output-names =
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"aclk_peri", "g_aclk_periph",
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"aclk_peri", "reserved", /*"g_aclk_periph",*/
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"hclk_peri", "pclk_peri",
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"reserved", "clk_mac_pll",
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@@ -2354,7 +2354,7 @@
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"g_hclk_spdif", "g_h_spdif_8ch",
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"g_aclk_dmac1", "g_aclk_strc_sys",
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"g_p_ddrupctl0", "g_pclk_publ0";
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"reserved", "reserved"; /*"g_p_ddrupctl0", "g_pclk_publ0";*/
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rockchip,suspend-clkgating-setting=<0xe2f0 0xe2f0>;
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#clock-cells = <1>;
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@@ -2377,11 +2377,11 @@
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<&dummy>, <&dummy>;
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clock-output-names =
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"g_p_ddrupctl1", "g_pclk_publ1",
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"g_p_efuse_1024", "g_pclk_tzpc",
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"reserved", "reserved", /*"g_p_ddrupctl1", "g_pclk_publ1",*/
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"g_p_efuse_1024", "g_pclk_tzpc",
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"reserved", "reserved", /*"g_nclk_ddrupctl0", "g_nclk_ddrupctl1"*/
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"g_aclk_crypto", "g_hclk_crypto",
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"g_aclk_crypto", "g_hclk_crypto",
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"g_aclk_ccp", "g_pclk_uart2",
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"g_p_efuse_256", "g_pclk_rkpwm",
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@@ -2416,8 +2416,8 @@
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"clk_l2ram", "aclk_core_m0",
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"aclk_core_mp", "atclk_core",
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"pclk_dbg_src", "g_dbg_core_clk",
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"g_cs_dbg_clk", "g_pclk_core_niu",
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"pclk_dbg_src", "reserved", /*"g_dbg_core_clk",*/
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"reserved", "reserved", /*"g_cs_dbg_clk", "g_pclk_core_niu",*/
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"reserved", "reserved",
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"reserved", "reserved";
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@@ -2509,7 +2509,7 @@
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<&aclk_vio0>, <&hclk_vio>;
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clock-output-names =
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"g_aclk_rga", "g_hclk_rga",
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"reserved", /*"g_aclk_rga",*/ "g_hclk_rga",
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"g_aclk_iep", "g_hclk_iep",
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"g_aclk_lcdc_iep", "g_aclk_lcdc0",
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@@ -2518,7 +2518,7 @@
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"g_hclk_lcdc1", "g_h_vio_ahb",
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"g_hclk_vio_niu", "g_aclk_vio0_niu",
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"g_aclk_vio1_niu", "g_aclk_vio2_niu",
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"g_aclk_vio1_niu", "reserved",/*"g_aclk_rga_niu",*/
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"g_aclk_vip", "g_hclk_vip";
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rockchip,suspend-clkgating-setting=<0x0 0x0>;
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@@ -2608,7 +2608,7 @@
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<&dummy>, <&dummy>;
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clock-output-names =
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"g_aclk_gpu", "reserved",
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"reserved", /*"g_aclk_gpu",*/ "reserved",
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"reserved", "reserved",
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"reserved", "reserved",
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@@ -471,6 +471,97 @@
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<&clk_tspout 80000000>, <&clk_mac 125000000>;
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};
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clocks-enable {
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compatible = "rockchip,clocks-enable";
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clocks =
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/*PD_CORE*/
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<&clk_gates0 2>, <&clk_core0>,
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<&clk_core1>, <&clk_core2>,
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<&clk_core3>, <&clk_l2ram>,
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<&aclk_core_m0>, <&aclk_core_mp>,
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<&atclk_core>, <&pclk_dbg_src>,
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/*PD_BUS*/
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<&aclk_bus>, <&clk_gates0 3>,
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<&hclk_bus>, <&pclk_bus>,
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<&clk_gates13 8>, <&clk_crypto>,
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<&clk_gates0 7>,
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/*TIMER*/
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<&clk_gates1 0>, <&clk_gates1 1>,
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<&clk_gates1 2>, <&clk_gates1 3>,
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<&clk_gates1 4>, <&clk_gates1 5>,
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<&pclk_pd_alive>, <&pclk_pd_pmu>,
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/*PD_PERI*/
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<&aclk_peri>, <&hclk_peri>,
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<&pclk_peri>,
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/*JTAG*/
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/*<&clk_gates4 14>,*/
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/*aclk_bus*/
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<&clk_gates10 5>,/*aclk_intmem0*/
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<&clk_gates10 6>,/*aclk_intmem1*/
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<&clk_gates10 7>,/*aclk_intmem2*/
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<&clk_gates10 12>,/*aclk_dma1*/
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<&clk_gates10 13>,/*aclk_strc_sys*/
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<&clk_gates10 4>,/*aclk_intmem*/
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<&clk_gates11 6>,/*aclk_crypto*/
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<&clk_gates11 8>,/*aclk_ccp*/
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/*hclk_bus*/
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<&clk_gates11 7>,/*hclk_crypto*/
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<&clk_gates10 9>,/*hclk_rom*/
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/*pclk_bus*/
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<&clk_gates10 1>,/*pclk_timer*/
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/*aclk_peri*/
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<&clk_gates6 2>,/*aclk_peri_axi_matrix*/
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<&clk_gates6 3>,/*aclk_dmac2*/
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<&clk_gates7 11>,/*aclk_peri_niu*/
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<&clk_gates8 12>,/*aclk_peri_mmu*/
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/*hclk_peri*/
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<&clk_gates6 0>,/*hclk_peri_matrix*/
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<&clk_gates7 10>,/*hclk_peri_ahb_arbi*/
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<&clk_gates7 12>,/*hclk_emem_peri*/
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<&clk_gates7 13>,/*hclk_mem_peri*/
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/*pclk_peri*/
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<&clk_gates6 1>,/*pclk_peri_axi_matrix*/
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/*pclk_pd_alive*/
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<&clk_gates14 11>,/*pclk_grf*/
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<&clk_gates14 12>,/*pclk_alive_niu*/
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/*pclk_pd_pmu*/
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<&clk_gates17 0>,/*pclk_pmu*/
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<&clk_gates17 1>,/*pclk_intmem1*/
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<&clk_gates17 2>,/*pclk_pmu_niu*/
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<&clk_gates17 3>,/*pclk_sgrf*/
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/*hclk_vio*/
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<&clk_gates15 9>,/*hclk_vio_ahb_arbi*/
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<&clk_gates15 10>,/*hclk_vio_niu*/
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<&clk_gates16 10>,/*hclk_vio2_h2p*/
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<&clk_gates16 11>,/*pclk_vio2_h2p*/
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/*aclk_vio0*/
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<&clk_gates15 11>,/*aclk_vio0_niu*/
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/*aclk_vio1*/
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<&clk_gates15 12>,/*aclk_vio1_niu*/
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/*HDMI*/
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<&clk_gates5 12>,/*hdmi_hdcp_clk*/
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/*UART*/
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<&clk_gates11 9>;/*pclk_uart2*/
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};
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i2c0: i2c@ff650000 {
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compatible = "rockchip,rk30-i2c";
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reg = <0xff650000 0x1000>;
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@@ -74,14 +74,14 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
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static int clk_gate_enable(struct clk_hw *hw)
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{
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//clk_gate_endisable(hw, 1);
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clk_gate_endisable(hw, 1);
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return 0;
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}
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static void clk_gate_disable(struct clk_hw *hw)
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{
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//clk_gate_endisable(hw, 0);
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clk_gate_endisable(hw, 0);
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}
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static int clk_gate_is_enabled(struct clk_hw *hw)
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@@ -1658,7 +1658,7 @@ void rk_clk_test(void) {}
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#endif
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EXPORT_SYMBOL_GPL(rk_clk_test);
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void rkclk_init_clks(struct device_node *node);
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void __init rkclk_init_clks(struct device_node *node);
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static struct device_node * clk_root_node=NULL;
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static void __init rk_clk_tree_init(struct device_node *np)
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@@ -1796,7 +1796,50 @@ const char *of_clk_init_parent_get_info(struct device_node *np, int index,
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return clk_name;
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}
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void rkclk_init_clks(struct device_node *np)
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static int __init rkclk_init_enable(void)
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{
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struct device_node *node;
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int cnt, i, ret = 0;
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const char *clk_name;
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struct clk *clk;
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node = of_find_node_by_name(NULL, "clocks-enable");
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if (!node) {
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clk_err("%s: can not get clocks-enable node\n", __func__);
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return -EINVAL;
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}
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cnt = of_count_phandle_with_args(node, "clocks", "#clock-cells");
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if (cnt < 0) {
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return -EINVAL;
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} else {
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clk_debug("%s: cnt = %d\n", __func__, cnt);
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}
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for (i = 0; i < cnt ; i++) {
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clk_name = of_clk_get_parent_name(node, i);
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clk = clk_get(NULL, clk_name);
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if (IS_ERR_OR_NULL(clk)) {
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clk_err("%s: fail to get %s\n", __func__, clk_name);
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return -EINVAL;
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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clk_err("%s: fail to prepare_enable %s\n", __func__,
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clk_name);
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return ret;
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} else {
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clk_debug("%s: prepare_enable %s OK\n", __func__,
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clk_name);
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}
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}
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return ret;
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}
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void __init rkclk_init_clks(struct device_node *np)
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{
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//struct device_node *np;
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int i,cnt_parent,cnt_rate;
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@@ -1855,6 +1898,8 @@ void rkclk_init_clks(struct device_node *np)
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clk_rate);
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}
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rkclk_init_enable();
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}
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u32 clk_suspend_clkgt_info_get(u32 *clk_ungt_msk,u32 *clk_ungt_msk_last,u32 buf_cnt)
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