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hdmirx: reset bandgap when aud pll error

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PD#171856: hdmirx: reset bandgap when aud pll error

Change-Id: I17970eeeea89726513dee61ea743769753a5e71a
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
This commit is contained in:
yicheng shen
2018-08-23 10:49:18 +08:00
committed by Jianxin Pan
parent a468c0df66
commit c233917f28
5 changed files with 38 additions and 16 deletions
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2
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
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@@ -34,7 +34,7 @@
#include "hdmi_rx_edid.h"
#define RX_VER0 "ver.2018-08-22"
#define RX_VER0 "ver.2018-09-07"
/*
*
*

18
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
View File

@@ -1862,6 +1862,19 @@ void rx_hdcp_init(void)
hdmirx_wr_bits_dwc(DWC_HDCP_CTRL, ENCRIPTION_ENABLE, 0);
}
/* need reset bandgap when
* aud_clk=0 & req_clk!=0
* according to analog team's request
*/
void rx_audio_bandgap_rst(void)
{
vdac_enable(0, 0x10);
udelay(20);
vdac_enable(1, 0x10);
if (log_level & AUDIO_LOG)
rx_pr("%s\n", __func__);
}
void rx_sw_reset(int level)
{
unsigned long data32 = 0;
@@ -2533,6 +2546,7 @@ int rx_get_aud_pll_err_sts(void)
{
int ret = E_AUDPLL_OK;
int32_t req_clk = hdmirx_get_mpll_div_clk();
int32_t aud_clk = hdmirx_get_audio_clock();
uint32_t phy_pll_rate = (hdmirx_rd_phy(PHY_MAINFSM_STATUS1)>>9)&0x3;
uint32_t aud_pll_cntl = (rd_reg_hhi(HHI_AUD_PLL_CNTL6)>>28)&0x3;
@@ -2546,6 +2560,10 @@ int rx_get_aud_pll_err_sts(void)
if (log_level & AUDIO_LOG)
rx_pr("pll rate chg,phy=%d,pll=%d\n",
phy_pll_rate, aud_pll_cntl);
} else if (aud_clk == 0) {
ret = E_AUDCLK_ERR;
if (log_level & AUDIO_LOG)
rx_pr("aud_clk=0\n");
}
return ret;

1
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h
View File

@@ -1101,6 +1101,7 @@ extern void cec_hw_reset(void);
extern void rx_force_hpd_cfg(uint8_t hpd_level);
extern void rx_force_rxsense_cfg(uint8_t level);
extern void rx_force_hpd_rxsense_cfg(uint8_t level);
extern void rx_audio_bandgap_rst(void);
#endif

32
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
View File

@@ -2241,23 +2241,23 @@ void rx_main_state_machine(void)
rx.aud_sr_unstable_cnt++;
if (rx.aud_sr_unstable_cnt > aud_sr_stb_max) {
unsigned int aud_sts = rx_get_aud_pll_err_sts();
if (aud_sts == E_REQUESTCLK_ERR) {
hdmirx_phy_init();
rx.state = FSM_WAIT_CLK_STABLE;
rx.pre_state = FSM_SIG_READY;
if (log_level & ERR_LOG)
rx_pr("reqclk err->wait_clk\n");
} else if (aud_sts == E_PLLRATE_CHG) {
rx_pr("reqclk err->wait_clk\n");
} else if (aud_sts == E_PLLRATE_CHG)
rx_aud_pll_ctl(1);
if (log_level & ERR_LOG)
rx_pr("pllrate err\n");
else if (aud_sts == E_AUDCLK_ERR) {
rx_audio_bandgap_rst();
rx.aud_sr_stable_cnt = 0;
} else {
rx_acr_info_sw_update();
rx_audio_pll_sw_update();
if (log_level & ERR_LOG)
if (log_level & AUDIO_LOG)
rx_pr("update audio-err\n");
}
rx.aud_sr_unstable_cnt = 0;
}
} else
@@ -2592,14 +2592,16 @@ void rx_main_state_machine(void)
rx.aud_sr_unstable_cnt++;
if (rx.aud_sr_unstable_cnt > aud_sr_stb_max) {
aud_pll_sts = rx_get_aud_pll_err_sts();
if (aud_pll_sts > E_AUDPLL_OK) {
if (aud_pll_sts == E_REQUESTCLK_ERR) {
hdmirx_phy_init();
rx.state = FSM_WAIT_CLK_STABLE;
rx.pre_state = FSM_SIG_READY;
rx_pr("reqclk err->wait_clk\n");
} else if (aud_pll_sts == E_PLLRATE_CHG)
rx_aud_pll_ctl(1);
if (aud_pll_sts == E_REQUESTCLK_ERR) {
hdmirx_phy_init();
rx.state = FSM_WAIT_CLK_STABLE;
rx.pre_state = FSM_SIG_READY;
rx_pr("reqclk err->wait_clk\n");
} else if (aud_pll_sts == E_PLLRATE_CHG)
rx_aud_pll_ctl(1);
else if (aud_pll_sts == E_AUDCLK_ERR) {
rx_audio_bandgap_rst();
rx.aud_sr_stable_cnt = 0;
} else {
rx_acr_info_sw_update();
rx_audio_pll_sw_update();

1
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.h
View File

@@ -100,6 +100,7 @@ enum aud_clk_err_e {
E_AUDPLL_OK,
E_REQUESTCLK_ERR,
E_PLLRATE_CHG,
E_AUDCLK_ERR,
};
/* signal */