shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-11 13:27:06 +09:00
Code Issues Packages Projects Releases Wiki Activity

FROMLIST: arm64: mm: Rename post_ttbr0_update_workaround

Browse Source 
The post_ttbr0_update_workaround hook applies to any change to TTBRx_EL1.
Since we're using TTBR1 for the ASID, rename the hook to make it clearer
as to what it's doing.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Laura Abbott <labbott@redhat.com>
Tested-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git
 commit 158d495899)

Change-Id: Iaf152ca1bd0a20bd15a77afac4ad4e9ea8ada08f
Signed-off-by: Greg Hackmann <ghackmann@google.com>
This commit is contained in:
Will Deacon
2017-08-10 13:34:30 +01:00
committed by Greg Hackmann
parent ca0ebb4ee2
commit c30184d9b6
3 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/include/asm/assembler.h
View File

@@ -399,9 +399,9 @@ alternative_endif
.endm
/*
* Errata workaround post TTBR0_EL1 update.
* Errata workaround post TTBRx_EL1 update.
*/
.macro post_ttbr0_update_workaround
.macro post_ttbr_update_workaround
#ifdef CONFIG_CAVIUM_ERRATUM_27456
alternative_if ARM64_WORKAROUND_CAVIUM_27456
ic iallu

2
arch/arm64/kernel/entry.S
View File

@@ -241,7 +241,7 @@ alternative_else_nop_endif
* Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
* corruption).
*/
post_ttbr0_update_workaround
post_ttbr_update_workaround
.endif
1:
.if \el != 0

2
arch/arm64/mm/proc.S
View File

@@ -145,7 +145,7 @@ ENTRY(cpu_do_switch_mm)
isb
msr ttbr0_el1, x0 // now update TTBR0
isb
post_ttbr0_update_workaround
post_ttbr_update_workaround
ret
ENDPROC(cpu_do_switch_mm)