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rk29: disable irq, delay more time and run in sram while power domain on/off

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This commit is contained in:
黄涛
2011-03-26 10:46:42 +08:00
parent 5ca77cf56a
commit c3370bfa7f
5 changed files with 37 additions and 28 deletions
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40
arch/arm/mach-rk29/clock.c
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@@ -31,6 +31,7 @@
#include <mach/rk29_iomap.h>
#include <mach/cru.h>
#include <mach/pmu.h>
#include <mach/sram.h>
/* Clock flags */
@@ -39,9 +40,6 @@
#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
#define IS_PD (1 << 2) /* Power Domain */
#define cru_readl(offset) readl(RK29_CRU_BASE + offset)
#define cru_writel(v, offset) writel(v, RK29_CRU_BASE + offset)
#define regfile_readl(offset) readl(RK29_GRF_BASE + offset)
#define pmu_readl(offset) readl(RK29_PMU_BASE + offset)
@@ -1699,6 +1697,38 @@ GATE_CLK(hclk_mmc1, hclk_periph, HCLK_MMC1);
GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
static void __sramfunc pmu_set_power_domain_sram(enum pmu_power_domain pd, bool on)
{
if (on)
writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << pd), RK29_PMU_BASE + PMU_PD_CON);
else
writel(readl(RK29_PMU_BASE + PMU_PD_CON) | (1 << pd), RK29_PMU_BASE + PMU_PD_CON);
dsb();
while (pmu_power_domain_is_on(pd) != on)
;
}
static noinline void do_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
{
static unsigned long save_sp;
DDR_SAVE_SP(save_sp);
pmu_set_power_domain_sram(pd, on);
DDR_RESTORE_SP(save_sp);
}
void pmu_set_power_domain(enum pmu_power_domain pd, bool on)
{
unsigned long flags;
local_irq_save(flags);
mdelay(10);
do_pmu_set_power_domain(pd, on);
mdelay(10);
local_irq_restore(flags);
}
static int pd_vcodec_mode(struct clk *clk, int on)
{
if (on) {
@@ -1713,8 +1743,6 @@ static int pd_vcodec_mode(struct clk *clk, int on)
pmu_set_power_domain(PD_VCODEC, true);
udelay(10);
cru_writel(cru_clkgate3_con_mirror, CRU_CLKGATE3_CON);
} else {
pmu_set_power_domain(PD_VCODEC, false);
@@ -1758,8 +1786,6 @@ static int pd_display_mode(struct clk *clk, int on)
pmu_set_power_domain(PD_DISPLAY, true);
udelay(10);
cru_writel(gate2, CRU_CLKGATE2_CON);
cru_writel(cru_clkgate3_con_mirror, CRU_CLKGATE3_CON);
} else {

3
arch/arm/mach-rk29/include/mach/cru.h
View File

@@ -296,6 +296,9 @@ enum cru_soft_reset {
#define CRU_SOFTRST1_CON 0x70
#define CRU_SOFTRST2_CON 0x74
#define cru_readl(offset) readl(RK29_CRU_BASE + offset)
#define cru_writel(v, offset) do { writel(v, RK29_CRU_BASE + offset); dsb(); } while (0)
extern volatile u32 cru_clkgate3_con_mirror;
void cru_set_soft_reset(enum cru_soft_reset idx, bool on);

15
arch/arm/mach-rk29/include/mach/pmu.h
View File

@@ -45,19 +45,6 @@ static inline bool pmu_power_domain_is_on(enum pmu_power_domain pd)
return !(readl(RK29_PMU_BASE + PMU_PD_ST) & (1 << pd));
}
static inline void pmu_set_power_domain(enum pmu_power_domain pd, bool on)
{
unsigned long flags;
local_irq_save(flags);
if (on)
writel(readl(RK29_PMU_BASE + PMU_PD_CON) & ~(1 << pd), RK29_PMU_BASE + PMU_PD_CON);
else
writel(readl(RK29_PMU_BASE + PMU_PD_CON) | (1 << pd), RK29_PMU_BASE + PMU_PD_CON);
local_irq_restore(flags);
while (pmu_power_domain_is_on(pd) != on)
;
}
void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
#endif

4
arch/arm/mach-rk29/pm.c
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@@ -27,10 +27,6 @@
#include <mach/ddr.h>
#include <mach/memtester.h>
#define cru_readl(offset) readl(RK29_CRU_BASE + offset)
#define cru_writel(v, offset) do { writel(v, RK29_CRU_BASE + offset); readl(RK29_CRU_BASE + offset); } while (0)
#define pmu_readl(offset) readl(RK29_PMU_BASE + offset)
#define pmu_writel(v, offset) do { writel(v, RK29_PMU_BASE + offset); readl(RK29_PMU_BASE + offset); } while (0)
static unsigned long save_sp;
#define LOOPS_PER_USEC 13

3
arch/arm/mach-rk29/reset.c
View File

@@ -21,9 +21,6 @@
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>
#define cru_readl(offset) readl(RK29_CRU_BASE + offset)
#define cru_writel(v, offset) do { writel(v, RK29_CRU_BASE + offset); readl(RK29_CRU_BASE + offset); } while (0)
static inline void delay_500ns(void)
{
int delay = 13;