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soc: rockchip: debug: access dbgpcsr when cpu is up
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com> Change-Id: I8ac1e3dba85c69e6a1febf9e3259bb0417fc6509
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@@ -62,6 +62,9 @@
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#define EDLAR 0xfb0
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#define EDLAR_UNLOCK 0xc5acce55
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#define EDPRSR 0x314
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#define EDPRSR_PU 0x1
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#define NUM_CPU_SAMPLES 100
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#define NUM_SAMPLES_TO_PRINT 32
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@@ -71,14 +74,22 @@ static void __iomem *rockchip_cpu_debug[16];
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int rockchip_debug_dump_pcsr(struct fiq_debugger_output *output)
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{
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unsigned long dbgpcsr;
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int i = 0, j;
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int i = 0, j = 0;
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void *pc = NULL;
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void *prev_pc = NULL;
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int printed = 0;
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void __iomem *base;
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u32 pu = 0;
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while (rockchip_cpu_debug[i]) {
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base = rockchip_cpu_debug[i];
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pu = (u32)readl(base + EDPRSR) & EDPRSR_PU;
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if (pu != EDPRSR_PU) {
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i++;
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continue;
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}
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/* Unlock EDLSR.SLK so that EDPCSRhi gets populated */
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writel(EDLAR_UNLOCK, base + EDLAR);
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@@ -123,6 +134,7 @@ static int rockchip_panic_notify(struct notifier_block *nb, unsigned long event,
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void *prev_pc = NULL;
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int printed = 0;
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void __iomem *base;
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u32 pu = 0;
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/*
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* The panic handler will try to shut down the other CPUs.
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@@ -133,6 +145,13 @@ static int rockchip_panic_notify(struct notifier_block *nb, unsigned long event,
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while (rockchip_cpu_debug[i]) {
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base = rockchip_cpu_debug[i];
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pu = (u32)readl(base + EDPRSR) & EDPRSR_PU;
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if (pu != EDPRSR_PU) {
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i++;
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continue;
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}
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/* Unlock EDLSR.SLK so that EDPCSRhi gets populated */
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writel(EDLAR_UNLOCK, base + EDLAR);
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