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di: G12A add di support

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PD#156734: G12A add di support
1) add new mtn&cont&mcinfo&mv&if0 mif
2) add nr downscale
3) post viu link case
4) add pps

Change-Id: Id9ce920323d4324f0e1429df787f8af2dad07318
Signed-off-by: kele bai <kele.bai@amlogic.com>
This commit is contained in:
kele bai
2018-01-04 19:20:30 +08:00
committed by Yixun Lan
parent 54bbddc7fc
commit c3edb7d03b
19 changed files with 3301 additions and 649 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
MAINTAINERS
View File

@@ -13666,12 +13666,14 @@ AMLOGIC VRTC DRIVER
M: Yun Cai <yun.cai@amlogic.com>
F: drivers/amlogic/vrtc/
AMLOGIC DEINTERLACE, NR, CUE, Field Detection, VOF DRIVERS
AMLOGIC DEINTERLACE, NR, CUE, Field Detection, NR DS, PPS, VOF DRIVERS
M: Kele Bai <kele.bai@amlogic.com>
F: drivers/amlogic/deinterlace/*
F: drivers/amlogic/media/deinterlace/film_mode_fmw/*
F: include/linux/amlogic/media/amvecm/amvecm.h
F: arch/arm64/boot/dts/amlogic/txlx_t962e_r321.dts
F: arch/arm64/boot/dts/amlogic/txlx_t962x_r311.dts
F: arch/arm64/boot/dts/amlogic/g12a_pxp.dts
AMLOGIC TVIN
M: Dezhi Kong <dezhi.kong@amlogic.com>

55
arch/arm64/boot/dts/amlogic/g12a_pxp.dts
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@@ -67,6 +67,32 @@
size = <0x0 0x8000000>;
alignment = <0x0 0x400000>;
};
//di_reserved:linux,di {
//compatible = "amlogic, di-mem";
/* buffer_size = 3621952(yuv422 8bit) */
/* 4179008(yuv422 10bit full pack mode) */
/** 10x3621952=34.6M(0x23) support 8bit **/
/** 10x4736064=45.2M(0x2e) support 12bit **/
/** 10x4179008=40M(0x28) support 10bit **/
//size = <0x0 0x2800000>;
//no-map;
//};
/*di CMA pool */
di_cma_reserved:linux,di_cma {
compatible = "shared-dma-pool";
reusable;
/* buffer_size = 3621952(yuv422 8bit)
* | 4736064(yuv422 10bit)
* | 4074560(yuv422 10bit full pack mode)
* 10x3621952=34.6M(0x23) support 8bit
* 10x4736064=45.2M(0x2e) support 12bit
* 10x4074560=40M(0x28) support 10bit
*/
size = <0x0 0x02900000>;
alignment = <0x0 0x400000>;
};
};
vout {
@@ -208,6 +234,35 @@
reg = <0x0 0xff940000 0x0 0x10000>;
};
deinterlace {
compatible = "amlogic, deinterlace";
status = "okay";
/* 0:use reserved; 1:use cma; 2:use cma as reserved */
flag_cma = <1>;
//memory-region = <&di_reserved>;
memory-region = <&di_cma_reserved>;
interrupts = <0 46 1
0 40 1>;
interrupt-names = "pre_irq", "post_irq";
clocks = <&clkc CLKID_VPU_MUX>,
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_VPU_CLKB_TMP_COMP>,
<&clkc CLKID_VPU_CLKB_COMP>;
clock-names = "vpu_mux",
"fclk_div4",
"vpu_clkb_tmp_composite",
"vpu_clkb_composite";
clock-range = <333 666>;
/* buffer-size = <3621952>;(yuv422 8bit) */
buffer-size = <4074560>;/*yuv422 fullpack*/
/* reserve-iomap = "true"; */
/* if enable nr10bit, set nr10bit-support to 1 */
post-wr-support = <1>;
nr10bit-support = <1>;
nrds-enable = <1>;
pps-enable = <1>;
};
amlvecm {
compatible = "amlogic, vecm";
dev_name = "aml_vecm";

1
arch/arm64/boot/dts/amlogic/txlx_t962e_r321.dts
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@@ -386,6 +386,7 @@
"fclk_div4",
"vpu_clkb_tmp_composite",
"vpu_clkb_composite";
clock-range = <250 500>;
/* buffer-size = <3621952>;(yuv422 8bit) */
buffer-size = <4179008>;/*yuv422 fullpack*/
/* reserve-iomap = "true"; */

1
arch/arm64/boot/dts/amlogic/txlx_t962x_r311_2g.dts
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@@ -387,6 +387,7 @@
"fclk_div4",
"vpu_clkb_tmp_composite",
"vpu_clkb_composite";
clock-range = <250 500>;
/* buffer-size = <3621952>;(yuv422 8bit) */
buffer-size = <4179008>;/*yuv422 fullpack*/
/* reserve-iomap = "true"; */

3
drivers/amlogic/media/deinterlace/Makefile
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@@ -12,6 +12,7 @@ di-objs += deinterlace_dbg.o
di-objs += nr_drv.o
di-objs += pulldown_drv.o
di-objs += detect3d.o
di-objs += detect3d.o
di-objs += nr_downscale.o
di-objs += di_pps.o
ccflags-y += -Idrivers/amlogic/media/common/rdma/

527
drivers/amlogic/media/deinterlace/deinterlace.c
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File diff suppressed because it is too large Load Diff

18
drivers/amlogic/media/deinterlace/deinterlace.h
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@@ -18,6 +18,7 @@
#ifndef _DI_H
#define _DI_H
#include <linux/cdev.h>
#include <linux/types.h>
#include <linux/amlogic/media/vfm/vframe.h>
#include <linux/amlogic/media/video_sink/video.h>
@@ -50,7 +51,7 @@
/* buffer management related */
#define MAX_IN_BUF_NUM 20
#define MAX_LOCAL_BUF_NUM 12
#define MAX_LOCAL_BUF_NUM 10
#define MAX_POST_BUF_NUM 16
#define VFRAME_TYPE_IN 1
@@ -65,7 +66,7 @@
#define DI_USE_FIXED_CANVAS_IDX
#define DET3D
#undef SUPPORT_MPEG_TO_VDIN
#define CLK_TREE_SUPPORT
#ifndef CONFIG_AMLOGIC_MEDIA_RDMA
#ifndef VSYNC_WR_MPEG_REG
#define VSYNC_WR_MPEG_REG(adr, val) aml_write_vcbus(adr, val)
@@ -203,7 +204,8 @@ struct di_dev_s {
struct list_head pq_table_list;
atomic_t pq_flag;
unsigned char di_event;
unsigned int di_irq;
unsigned int pre_irq;
unsigned int post_irq;
unsigned int flags;
unsigned long jiffy;
unsigned long mem_start;
@@ -216,6 +218,8 @@ struct di_dev_s {
unsigned int nr10bit_support;
/* is DI support post wr to mem for OMX */
unsigned int post_wr_support;
unsigned int nrds_enable;
unsigned int pps_enable;
struct mutex cma_mutex;
unsigned int flag_cma;
struct page *total_pages;
@@ -293,13 +297,15 @@ struct di_pre_stru_s {
/* alloc di buf as p or i;0: alloc buf as i;
* 1: alloc buf as p;
*/
unsigned char enable_mtnwr;
unsigned char enable_pulldown_check;
unsigned char madi_enable;
unsigned char mcdi_enable;
unsigned int pps_dstw;
unsigned int pps_dsth;
int left_right;/*1,left eye; 0,right eye in field alternative*/
/*input2pre*/
int bypass_start_count;
/* need discard some vframe when input2pre => bypass */
int vdin2nr;
unsigned char vdin2nr;
enum tvin_trans_fmt source_trans_fmt;
enum tvin_trans_fmt det3d_trans_fmt;
unsigned int det_lr;

281
drivers/amlogic/media/deinterlace/deinterlace_dbg.c
View File

@@ -32,8 +32,10 @@
#include <linux/uaccess.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include "deinterlace_dbg.h"
#include "register.h"
#include "deinterlace_dbg.h"
#include "di_pps.h"
#include "nr_downscale.h"
void parse_cmd_params(char *buf_orig, char **parm)
{
@@ -57,7 +59,7 @@ void parse_cmd_params(char *buf_orig, char **parm)
void dump_di_reg(void)
{
unsigned int i = 0, base_addr = 0;
unsigned int size_reg_addr[57] = {
unsigned int size_reg_addr[] = {
0x1702, 0x1703, 0x2d01,
0x2d01, 0x2d8f, 0x2d08,
0x2d09, 0x2f00, 0x2f01,
@@ -76,7 +78,18 @@ void dump_di_reg(void)
0x1a53, 0x1a54, 0x1a55,
0x1a56, 0x17ea, 0x17eb,
0x17ec, 0x17ed, 0x2012,
0x2013, 0x2014, 0x2015
0x2013, 0x2014, 0x2015,
0x37d2, 0x37d3, 0x37d7,
0x37d8, 0x37dc, 0x37dd,
0x37e1, 0x37e2, 0x37e6,
0x37e7, 0x37e9, 0x37ea,
0x37ed, 0x37ee, 0x37f1,
0x37f2, 0x37f4, 0x37f5,
0x37f6, 0x37f8, 0x3751,
0x3752, 0x376e, 0x376f,
0x37f9, 0x37fa, 0x37fc,
0x3740, 0x3757, 0x3762,
0xffff
};
if (is_meson_txlx_cpu() || is_meson_txhd_cpu())
base_addr = 0xff900000;
@@ -85,7 +98,7 @@ void dump_di_reg(void)
pr_info("----dump di reg----\n");
pr_info("----dump size reg---");
for (i = 0; i < 57; i++)
for (i = 0; size_reg_addr[i] != 0xffff; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((size_reg_addr[i]) << 2),
size_reg_addr[i], RDMA_RD(size_reg_addr[i]));
@@ -102,6 +115,11 @@ void dump_di_reg(void)
base_addr + ((0x1700 + i) << 2),
0x1700 + i, RDMA_RD(0x1700 + i));
}
for (i = 0; i < 4; i++) {
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x20ab + i) << 2),
0x20ab + i, RDMA_RD(0x20ab + i));
}
pr_info("----dump mcdi reg----\n");
for (i = 0; i < 201; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
@@ -171,6 +189,192 @@ void dump_di_reg(void)
pr_info("----dump reg done----\n");
}
void dump_di_reg_g12(void)
{
unsigned int i = 0, base_addr = 0;
unsigned int size_reg_addr[] = {
0x1700, 0x1701, 0x1702,
0x1703, 0x37d2, 0x27d3,
0x37d7, 0x37d8, 0x37dc,
0x37dd, 0x37e1, 0x37e2,
0x37e6, 0x37e7, 0x37e9,
0x37ea, 0x37ec, 0x37ed,
0x37ee, 0x37f0, 0x37f1,
0x37f2, 0x37f4, 0x37f5,
0x37f6, 0x37f8, 0x2032,
0x2033, 0x2034, 0x2035,
0x2d01, 0x2d02, 0x2d8f,
0x2d08, 0x2d09, 0x2f00,
0x2f01, 0x17d0, 0x17d1,
0x17d2, 0x17d3, 0x17dd,
0x17de, 0x17df, 0x17e0,
0x17f7, 0x17f8, 0x17f9,
0x17fa, 0x17c0, 0x17c1,
0x17c6, 0x17c7, 0x3253,
0x3254, 0x3255, 0x3256,
0x17ea, 0x17eb, 0x17ec,
0x17ed, 0x2012, 0x2013,
0x2014, 0x2015, 0x37d2,
0x37d3, 0x37d7, 0x37d8,
0x37dc, 0x37dd, 0x37e1,
0x37e2, 0x37e6, 0x37e7,
0x37e9, 0x37ea, 0x37ed,
0x37ee, 0x37f1, 0x37f2,
0x37f4, 0x37f5, 0x37f6,
0x37f8, 0x3751, 0x3752,
0x376e, 0x376f, 0x37f9,
0x37fa, 0x37fc, 0x3740,
0x3757, 0x3762, 0x3755,
0x3757, 0x3760, 0x3762,
0x376e, 0x376f, 0x37f9,
0x37fa, 0x37fc, 0xffff
};
if (is_meson_txlx_cpu() ||
is_meson_txhd_cpu() ||
is_meson_g12a_cpu())
base_addr = 0xff900000;
else
base_addr = 0xd0100000;
pr_info("----dump di reg----\n");
pr_info("----dump size reg---");
for (i = 0; size_reg_addr[i] != 0xffff; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((size_reg_addr[i]) << 2),
size_reg_addr[i], RDMA_RD(size_reg_addr[i]));
for (i = 0; i < 255; i++) {
if (i == 0x45)
pr_info("----nr reg----");
if (i == 0x80)
pr_info("----3d reg----");
if (i == 0x9e)
pr_info("---nr reg done---");
if (i == 0x9c)
pr_info("---3d reg done---");
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x1700 + i) << 2),
0x1700 + i, RDMA_RD(0x1700 + i));
}
dump_pps_reg(base_addr);
dump_nrds_reg(base_addr);
pr_info("----dump mcdi reg----\n");
for (i = 0; i < 201; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x2f00 + i) << 2),
0x2f00 + i, RDMA_RD(0x2f00 + i));
pr_info("----dump pulldown reg----\n");
for (i = 0; i < 26; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x2fd0 + i) << 2),
0x2fd0 + i, RDMA_RD(0x2fd0 + i));
pr_info("----dump bit mode reg----\n");
for (i = 0; i < 4; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x20a7 + i) << 2),
0x20a7 + i, RDMA_RD(0x20a7 + i));
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + (0x2022 << 2),
0x2022, RDMA_RD(0x2022));
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + (0x17c1 << 2),
0x17c1, RDMA_RD(0x17c1));
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + (0x17c2 << 2),
0x17c2, RDMA_RD(0x17c2));
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + (0x1aa7 << 2),
0x1aa7, RDMA_RD(0x1aa7));
pr_info("----dump dnr reg----\n");
for (i = 0; i < 29; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x2d00 + i) << 2),
0x2d00 + i, RDMA_RD(0x2d00 + i));
pr_info("----dump if0 reg----\n");
for (i = 0; i < 26; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x3200 + i) << 2),
0x3200 + i, RDMA_RD(0x3200 + i));
pr_info("----dump gate reg----\n");
pr_info("[0x%x][0x1718]=0x%x\n",
base_addr + ((0x1718) << 2),
RDMA_RD(0x1718));
for (i = 0; i < 5; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x2006 + i) << 2),
0x2006 + i, RDMA_RD(0x2006 + i));
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x2dff) << 2),
0x2dff, RDMA_RD(0x2dff));
pr_info("----dump if2 reg----\n");
for (i = 0; i < 29; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x2010 + i) << 2),
0x2010 + i, RDMA_RD(0x2010 + i));
pr_info("----dump nr4 reg----\n");
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x2fff) << 2),
0x2fff, RDMA_RD(0x2fff));
for (i = 0x2da4; i < 0x2df6; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + (i << 2),
i, RDMA_RD(i));
for (i = 0x3700; i < 0x373f; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + (i << 2),
i, RDMA_RD(i));
for (i = 0; i < 57; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((size_reg_addr[i]) << 2),
size_reg_addr[i], RDMA_RD(size_reg_addr[i]));
pr_info("----dump arb reg----\n");
for (i = 0; i < 14; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x3750 + i) << 2),
0x3750 + i, RDMA_RD(0x3750 + i));
for (i = 0; i < 14; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x37c0 + i) << 2),
0x37c0 + i, RDMA_RD(0x37c0 + i));
pr_info("----dump pps reg----\n");
for (i = 0; i < 32; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x374e + i) << 2),
0x374e + i, RDMA_RD(0x374e + i));
pr_info("----dump di hdr reg----\n");
for (i = 0; i < 62; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + ((0x376e + i) << 2),
0x376e + i, RDMA_RD(0x376e + i));
pr_info("----dump reg done----\n");
}
static void dump_mif_state(struct DI_MIF_s *mif)
{
pr_info("luma <%u, %u> <%u %u>.\n",
mif->luma_x_start0, mif->luma_x_end0,
mif->luma_y_start0, mif->luma_y_end0);
pr_info("if0 chroma <%u, %u> <%u %u>.\n",
mif->chroma_x_start0, mif->chroma_x_end0,
mif->chroma_y_start0, mif->chroma_y_end0);
}
static void dump_simple_mif_state(struct DI_SIM_MIF_s *simp_mif)
{
pr_info("<%u %u> <%u %u>.\n",
simp_mif->start_x, simp_mif->end_x,
simp_mif->start_y, simp_mif->end_y);
}
static void dump_mc_mif_state(struct DI_MC_MIF_s *mc_mif)
{
pr_info("startx %u,<%u %u>, size <%u %u>.\n",
mc_mif->start_x, mc_mif->start_y,
mc_mif->end_y, mc_mif->size_x,
mc_mif->size_y);
}
void dump_di_pre_stru(struct di_pre_stru_s *di_pre_stru_p)
{
pr_info("di_pre_stru:\n");
@@ -214,10 +418,10 @@ void dump_di_pre_stru(struct di_pre_stru_s *di_pre_stru_p)
di_pre_stru_p->source_change_flag);
pr_info("prog_proc_type = %d\n",
di_pre_stru_p->prog_proc_type);
pr_info("enable_mtnwr = %d\n",
di_pre_stru_p->enable_mtnwr);
pr_info("enable_pulldown_check = %d\n",
di_pre_stru_p->enable_pulldown_check);
pr_info("madi_enable = %u\n",
di_pre_stru_p->madi_enable);
pr_info("mcdi_enable = %u\n",
di_pre_stru_p->mcdi_enable);
#ifdef DET3D
pr_info("vframe_interleave_flag = %d\n",
di_pre_stru_p->vframe_interleave_flag);
@@ -232,21 +436,55 @@ void dump_di_pre_stru(struct di_pre_stru_s *di_pre_stru_p)
di_pre_stru_p->bypass_pre ? "true" : "false");
pr_info("invert_flag = %s\n",
di_pre_stru_p->invert_flag ? "true" : "false");
pr_info("inp mif:\n");
dump_mif_state(&di_pre_stru_p->di_inp_mif);
pr_info("mem mif:\n");
dump_mif_state(&di_pre_stru_p->di_mem_mif);
pr_info("chan2 mif:\n");
dump_mif_state(&di_pre_stru_p->di_chan2_mif);
pr_info("nrwr mif:\n");
dump_simple_mif_state(&di_pre_stru_p->di_nrwr_mif);
pr_info("mtnwr mif:\n");
dump_simple_mif_state(&di_pre_stru_p->di_mtnwr_mif);
pr_info("contp2rd mif:\n");
dump_simple_mif_state(&di_pre_stru_p->di_contp2rd_mif);
pr_info("contprd mif:\n");
dump_simple_mif_state(&di_pre_stru_p->di_contprd_mif);
pr_info("contwr mif:\n");
dump_simple_mif_state(&di_pre_stru_p->di_contwr_mif);
pr_info("mcinford mif:\n");
dump_mc_mif_state(&di_pre_stru_p->di_mcinford_mif);
pr_info("mcinfowr mif:\n");
dump_mc_mif_state(&di_pre_stru_p->di_mcinfowr_mif);
pr_info("mcvecwr mif:\n");
dump_mc_mif_state(&di_pre_stru_p->di_mcvecwr_mif);
}
void dump_di_post_stru(struct di_post_stru_s *di_post_stru_p)
{
di_pr_info("\ndi_post_stru:\n");
di_pr_info("run_early_proc_fun_flag = %d\n",
pr_info("\ndi_post_stru:\n");
pr_info("run_early_proc_fun_flag = %d\n",
di_post_stru_p->run_early_proc_fun_flag);
di_pr_info("cur_disp_index = %d\n",
pr_info("cur_disp_index = %d\n",
di_post_stru_p->cur_disp_index);
di_pr_info("post_de_busy = %d\n",
pr_info("post_de_busy = %d\n",
di_post_stru_p->post_de_busy);
di_pr_info("de_post_process_done = %d\n",
pr_info("de_post_process_done = %d\n",
di_post_stru_p->de_post_process_done);
di_pr_info("cur_post_buf = 0x%p\n,",
pr_info("cur_post_buf = 0x%p\n,",
di_post_stru_p->cur_post_buf);
pr_info("if0 mif:\n");
dump_mif_state(&di_post_stru_p->di_buf0_mif);
pr_info("if1 mif:\n");
dump_mif_state(&di_post_stru_p->di_buf1_mif);
pr_info("if2 mif:\n");
dump_mif_state(&di_post_stru_p->di_buf2_mif);
pr_info("diwr mif:\n");
dump_simple_mif_state(&di_post_stru_p->di_diwr_mif);
pr_info("mtnprd mif:\n");
dump_simple_mif_state(&di_post_stru_p->di_mtnprd_mif);
pr_info("mcvecrd mif:\n");
dump_mc_mif_state(&di_post_stru_p->di_mcvecrd_mif);
}
void dump_di_buf(struct di_buf_s *di_buf)
@@ -442,3 +680,18 @@ void dump_post_mif_reg(void)
pr_info("DI_DIWR_X=0x%x.\n", Rd(DI_DIWR_X));
}
void dump_buf_addr(struct di_buf_s *di_buf, unsigned int num)
{
unsigned int i = 0;
struct di_buf_s *di_buf_p = NULL;
for (i = 0; i < num; i++) {
di_buf_p = (di_buf+i);
pr_info("di_buf[%d] nr_addr 0x%lx,",
di_buf_p->index, di_buf_p->nr_adr);
pr_info("mtn_addr 0x%lx, cnt_adr 0x%lx,",
di_buf_p->mtn_adr, di_buf_p->cnt_adr);
pr_info("mv_adr 0x%lx, mcinfo_adr 0x%lx.\n",
di_buf_p->mcvec_adr, di_buf_p->mcinfo_adr);
}
}

2
drivers/amlogic/media/deinterlace/deinterlace_dbg.h
View File

@@ -25,9 +25,11 @@ void dump_di_buf(struct di_buf_s *di_buf);
void dump_pool(struct queue_s *q);
void dump_vframe(vframe_t *vf);
void dump_di_reg(void);
void dump_di_reg_g12(void);
void print_di_buf(struct di_buf_s *di_buf, int format);
void dump_pre_mif_state(void);
void dump_post_mif_reg(void);
void dump_buf_addr(struct di_buf_s *di_buf, unsigned int num);
void debug_device_files_add(struct device *dev);
void debug_device_files_del(struct device *dev);
#endif

990
drivers/amlogic/media/deinterlace/deinterlace_hw.c
View File

File diff suppressed because it is too large Load Diff

27
drivers/amlogic/media/deinterlace/deinterlace_hw.h
View File

@@ -97,25 +97,33 @@ void combing_pd22_window_config(unsigned int width, unsigned int height);
void di_hw_init(bool pulldown_en, bool mc_enable);
void di_hw_uninit(void);
void enable_di_pre_aml(
struct DI_MIF_s *di_inp_mif,
struct DI_MIF_s *di_mem_mif,
struct DI_MIF_s *di_chan2_mif,
struct DI_SIM_MIF_s *di_nrwr_mif,
struct DI_SIM_MIF_s *di_mtnwr_mif,
struct DI_MIF_s *di_inp_mif,
struct DI_MIF_s *di_mem_mif,
struct DI_MIF_s *di_chan2_mif,
struct DI_SIM_MIF_s *di_nrwr_mif,
struct DI_SIM_MIF_s *di_mtnwr_mif,
struct DI_SIM_MIF_s *di_contp2rd_mif,
struct DI_SIM_MIF_s *di_contprd_mif,
struct DI_SIM_MIF_s *di_contwr_mif,
int nr_en, int mtn_en, int pd32_check_en, int pd22_check_en,
int hist_check_en, int pre_field_num, int pre_vdin_link,
int hold_line, int urgent);
unsigned char madi_en, unsigned char pre_field_num,
unsigned char pre_vdin_link);
void enable_afbc_input(struct vframe_s *vf);
void mc_pre_mv_irq(void);
void enable_mc_di_pre(struct DI_MC_MIF_s *di_mcinford_mif,
struct DI_MC_MIF_s *di_mcinfowr_mif,
struct DI_MC_MIF_s *di_mcvecwr_mif, int urgent);
struct DI_MC_MIF_s *di_mcvecwr_mif,
unsigned char mcdi_en);
void enable_mc_di_pre_g12(struct DI_MC_MIF_s *di_mcinford_mif,
struct DI_MC_MIF_s *di_mcinfowr_mif,
struct DI_MC_MIF_s *di_mcvecwr_mif,
unsigned char mcdi_en);
void enable_mc_di_post(struct DI_MC_MIF_s *di_mcvecrd_mif,
int urgent, bool reverse, int invert_mv);
void enable_mc_di_post_g12(struct DI_MC_MIF_s *di_mcvecrd_mif,
int urgent, bool reverse, int invert_mv);
void disable_post_deinterlace_2(void);
void initial_di_post_2(int hsize_post, int vsize_post,
int hold_line, bool write_en);
@@ -154,7 +162,6 @@ void di_hw_disable(bool mc_enable);
void enable_di_pre_mif(bool enable, bool mc_enable);
void enable_di_post_mif(enum gate_mode_e mode);
void di_hw_uninit(void);
void di_load_regs(struct di_pq_parm_s *di_pq_ptr);
void combing_pd22_window_config(unsigned int width, unsigned int height);
void calc_lmv_init(void);
void calc_lmv_base_mcinfo(unsigned int vf_height, unsigned long mcinfo_adr);

1319
drivers/amlogic/media/deinterlace/di_pps.c Normal file
View File

File diff suppressed because it is too large Load Diff

101
drivers/amlogic/media/deinterlace/di_pps.h Normal file
View File

@@ -0,0 +1,101 @@
/*
* drivers/amlogic/media/deinterlace/di_pps.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef DI_PPS_H
#define DI_PPS_H
#include <linux/amlogic/media/video_sink/video.h>
#if 0
#define VPP_FLAG_WIDEMODE_MASK 0x0000000F
#define VPP_FLAG_INTERLACE_OUT 0x00000010
#define VPP_FLAG_INTERLACE_IN 0x00000020
#define VPP_FLAG_CBCR_SEPARATE 0x00000040
#define VPP_FLAG_ZOOM_SHORTSIDE 0x00000080
#define VPP_FLAG_AR_MASK 0x0003ff00
#define VPP_FLAG_AR_BITS 8
#define VPP_FLAG_PORTRAIT_MODE 0x00040000
#define VPP_FLAG_VSCALE_DISABLE 0x00080000
#define IDX_H (2 << 8)
#define IDX_V_Y (1 << 13)
#define IDX_V_CBCR ((1 << 13) | (1 << 8))
#define ASPECT_4_3 ((3<<8)/4)
#define ASPECT_16_9 ((9<<8)/16)
#define SPEED_CHECK_DONE 0
#define SPEED_CHECK_HSKIP 1
#define SPEED_CHECK_VSKIP 2
enum f2v_vphase_type_e {
F2V_IT2IT = 0,
F2V_IB2IB,
F2V_IT2IB,
F2V_IB2IT,
F2V_P2IT,
F2V_P2IB,
F2V_IT2P,
F2V_IB2P,
F2V_P2P,
F2V_TYPE_MAX
}; /* frame to video conversion type */
#endif
struct pps_f2v_vphase_s {
unsigned char rcv_num;
unsigned char rpt_num;
unsigned short phase;
};
struct ppsfilter_mode_s {
u32 pps_hf_start_phase_step;
u32 pps_hf_start_phase_slope;
u32 pps_hf_end_phase_slope;
const u32 *pps_vert_coeff;
const u32 *pps_horz_coeff;
u32 pps_sc_misc_;
u32 pps_vsc_start_phase_step;
u32 pps_hsc_start_phase_step;
bool pps_pre_vsc_en;
bool pps_pre_hsc_en;
u32 pps_vert_filter;
u32 pps_horz_filter;
const u32 *pps_chroma_coeff;
u32 pps_chroma_filter_en;
};
struct pps_frame_par_s {
u32 pps_vsc_startp;
u32 pps_vsc_endp;
u32 pps_hsc_startp;
u32 pps_hsc_linear_startp;
u32 pps_hsc_linear_endp;
u32 pps_hsc_endp;
u32 VPP_hf_ini_phase_;
struct f2v_vphase_s VPP_vf_ini_phase_[9];
u32 pps_pic_in_height_;
u32 pps_line_in_length_;
struct ppsfilter_mode_s pps_filter;
u32 pps_3d_mode;
u32 trans_fmt;
/* bit[1:0] 0: 1 pic,1:two pic one buf,2:tow pic two buf */
/* bit[2]0:select pic0,1:select pic1 */
/* bit[3]0:pic0 first,1:pic1 first */
bool pps_3d_scale;
};
void di_pps_config(unsigned char path, int src_w, int src_h,
int dst_w, int dst_h);
void dump_pps_reg(unsigned int base_addr);
#endif

187
drivers/amlogic/media/deinterlace/nr_downscale.c Normal file
View File

@@ -0,0 +1,187 @@
/*
* drivers/amlogic/media/deinterlace/nr_downscale.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/vmalloc.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/dma-contiguous.h>
#include <linux/amlogic/iomap.h>
#include <linux/amlogic/media/canvas/canvas.h>
#include <linux/amlogic/media/canvas/canvas_mgr.h>
#include "register.h"
#include "nr_downscale.h"
static struct nr_ds_s nrds_dev;
static void nr_ds_hw_init(unsigned int width, unsigned int height)
{
unsigned char h_step = 0, v_step = 0;
unsigned int width_out, height_out;
width_out = NR_DS_WIDTH;
height_out = NR_DS_HEIGHT;
h_step = width/width_out;
v_step = height/height_out;
RDMA_WR_BITS(VIUB_MISC_CTRL0, 3, 5, 2); //Switch MIF to NR_DS
RDMA_WR_BITS(NR_DS_BUF_SIZE_REG, width_out, 0, 8); // config dsbuf_ocol
RDMA_WR_BITS(NR_DS_BUF_SIZE_REG, height_out, 0, 8); // config dsbuf_orow
RDMA_WR_BITS(NRDSWR_X, (width_out-1), 0, 13);
RDMA_WR_BITS(NRDSWR_Y, (height_out-1), 0, 13);
RDMA_WR_BITS(NRDSWR_CAN_SIZE, (height_out-1), 0, 13);
RDMA_WR_BITS(NRDSWR_CAN_SIZE, (width_out-1), 16, 13);
RDMA_WR_BITS(NR_DS_CTRL, v_step, 16, 6);
RDMA_WR_BITS(NR_DS_CTRL, h_step, 24, 6);
}
/*
* init nr ds buffer
*/
void nr_ds_buf_init(unsigned int cma_flag, unsigned long mem_start,
struct device *dev)
{
unsigned int i = 0;
if (cma_flag == 0) {
nrds_dev.nrds_addr = mem_start;
} else {
nrds_dev.nrds_pages = dma_alloc_from_contiguous(dev,
NR_DS_PAGE_NUM, 0);
if (nrds_dev.nrds_pages)
nrds_dev.nrds_addr = page_to_phys(nrds_dev.nrds_pages);
else
pr_err("DI: alloc nr ds mem error.\n");
}
for (i = 0; i < NR_DS_BUF_NUM; i++)
nrds_dev.buf[i] = nrds_dev.nrds_addr + (NR_DS_BUF_SIZE*i);
nrds_dev.cur_buf_idx = 0;
}
void nr_ds_buf_uninit(unsigned int cma_flag, struct device *dev)
{
unsigned int i = 0;
if (cma_flag == 0) {
nrds_dev.nrds_addr = 0;
} else {
if (nrds_dev.nrds_pages) {
dma_release_from_contiguous(dev,
nrds_dev.nrds_pages,
NR_DS_PAGE_NUM);
nrds_dev.nrds_addr = 0;
nrds_dev.nrds_pages = NULL;
} else
pr_err("DI: release nr ds mem error.\n");
}
for (i = 0; i < NR_DS_BUF_NUM; i++)
nrds_dev.buf[i] = 0;
nrds_dev.cur_buf_idx = 0;
}
/*
* hw config, alloc canvas
*/
void nr_ds_init(unsigned int width, unsigned int height)
{
nr_ds_hw_init(width, height);
nrds_dev.field_num = 0;
if (nrds_dev.canvas_idx != 0)
return;
if (canvas_pool_alloc_canvas_table("nr_ds",
&nrds_dev.canvas_idx, 1, CANVAS_MAP_TYPE_1)) {
pr_err("%s alloc nrds canvas error.\n", __func__);
return;
}
pr_info("%s alloc nrds canvas %u.\n",
__func__, nrds_dev.canvas_idx);
}
/*
* config nr ds mif, switch buffer
*/
void nr_ds_mif_config(void)
{
unsigned long mem_addr = 0;
mem_addr = nrds_dev.buf[nrds_dev.cur_buf_idx];
canvas_config(nrds_dev.canvas_idx, mem_addr,
NR_DS_WIDTH, NR_DS_HEIGHT, 0, 0);
RDMA_WR_BITS(NRDSWR_CTRL,
nrds_dev.canvas_idx, 0, 8);
RDMA_WR_BITS(DI_PRE_CTRL, 1, 11, 1);
nr_ds_hw_ctrl(true);
}
/*
* enable/disable nr ds mif&hw
*/
void nr_ds_hw_ctrl(bool enable)
{
RDMA_WR_BITS(VIUB_MISC_CTRL0, enable?3:2, 5, 2); //Switch MIF to NR_DS
RDMA_WR_BITS(NRDSWR_CTRL, enable?1:0, 12, 1);
RDMA_WR_BITS(NR_DS_CTRL, enable?1:0, 30, 1);
}
/*
* process in irq
*/
void nr_ds_irq(void)
{
nr_ds_hw_ctrl(false);
nrds_dev.field_num++;
nrds_dev.cur_buf_idx++;
if (nrds_dev.cur_buf_idx >= NR_DS_BUF_NUM)
nrds_dev.cur_buf_idx = 0;
}
/*
* get buf addr&size for dump
*/
void get_nr_ds_buf(unsigned long *addr, unsigned long *size)
{
*addr = nrds_dev.nrds_addr;
*size = NR_DS_BUF_SIZE;
pr_info("%s addr 0x%lx, size 0x%lx.\n",
__func__, *addr, *size);
}
/*
* 0x37f9 ~ 0x37fc 0x3740 ~ 0x3743 8 regs
*/
void dump_nrds_reg(unsigned int base_addr)
{
unsigned int i = 0x37f9;
pr_info("-----nrds reg start-----\n");
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + (0x2006 << 2), i, RDMA_RD(0x2006));
for (i = 0x37f9; i < 0x37fd; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + (i << 2), i, RDMA_RD(i));
for (i = 0x3740; i < 0x3744; i++)
pr_info("[0x%x][0x%x]=0x%x\n",
base_addr + (i << 2), i, RDMA_RD(i));
pr_info("-----nrds reg end-----\n");
}

45
drivers/amlogic/media/deinterlace/nr_downscale.h Normal file
View File

@@ -0,0 +1,45 @@
/*
* drivers/amlogic/media/deinterlace/nr_downscale.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef _NR_DS_H
#define _NR_DS_H
#define NR_DS_WIDTH 128
#define NR_DS_HEIGHT 96
#define NR_DS_BUF_SIZE (96<<7)
#define NR_DS_BUF_NUM 6
#define NR_DS_MEM_SIZE (NR_DS_BUF_SIZE * NR_DS_BUF_NUM)
#define NR_DS_PAGE_NUM (NR_DS_MEM_SIZE>>PAGE_SHIFT)
struct nr_ds_s {
unsigned int field_num;
unsigned long nrds_addr;
struct page *nrds_pages;
unsigned int canvas_idx;
unsigned char cur_buf_idx;
unsigned long buf[NR_DS_BUF_NUM];
};
void nr_ds_buf_init(unsigned int cma_flag, unsigned long mem_start,
struct device *dev);
void nr_ds_buf_uninit(unsigned int cma_flag, struct device *dev);
void nr_ds_init(unsigned int width, unsigned int height);
void nr_ds_mif_config(void);
void nr_ds_hw_ctrl(bool enable);
void nr_ds_irq(void);
void get_nr_ds_buf(unsigned long *addr, unsigned long *size);
void dump_nrds_reg(unsigned int base_addr);
#endif

8
drivers/amlogic/media/deinterlace/nr_drv.c
View File

@@ -350,7 +350,7 @@ static void linebuffer_config(unsigned short width)
static void nr2_config(unsigned short width, unsigned short height)
{
if (is_meson_txlx_cpu())
if (is_meson_txlx_cpu() || is_meson_g12a_cpu())
DI_Wr_reg_bits(NR4_TOP_CTRL, nr2_en, 2, 1);
else {
/*set max height to disable nfram cnt in cue*/
@@ -397,7 +397,7 @@ void nr_all_config(unsigned short width, unsigned short height,
if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX))
cue_config(nr_param.pcue_parm, field_type);
if (is_meson_txlx_cpu()) {
if (is_meson_txlx_cpu() || is_meson_g12a_cpu()) {
linebuffer_config(width);
nr4_config(nr_param.pnr4_parm, width, height);
}
@@ -733,7 +733,7 @@ void nr_process_in_irq(void)
cue_process_irq();
if (dnr_en)
dnr_process(&dnr_param);
if (is_meson_txlx_cpu()) {
if (is_meson_txlx_cpu() || is_meson_g12a_cpu()) {
noise_meter_process(nr_param.pnr4_parm, nr_param.frame_count);
luma_enhancement_process(nr_param.pnr4_parm,
nr_param.frame_count);
@@ -1069,7 +1069,7 @@ void nr_hw_init(void)
}
void nr_gate_control(bool gate)
{
if (!is_meson_txlx_cpu())
if (!is_meson_txlx_cpu() && !is_meson_g12a_cpu())
return;
if (gate) {
/* enable nr auto gate */

208
drivers/amlogic/media/deinterlace/register.h
View File

@@ -38,7 +38,7 @@ void DI_Wr_reg_bits(unsigned int adr, unsigned int val,
void DI_VSYNC_WR_MPEG_REG(unsigned int addr, unsigned int val);
void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr,
unsigned int val, unsigned int start, unsigned int len);
#define HHI_VPU_CLKB_CNTL 0x83
#define VPU_WRARB_REQEN_SLV_L1C1 ((0x2795)) /* << 2) + 0xd0100000) */
#define VPU_ARB_DBG_STAT_L1C1 ((0x27b4)) /* << 2) + 0xd0100000) */
#define SRSHARP0_SHARP_SR2_CTRL ((0x3257)) /* << 2) + 0xd0100000) */
@@ -359,6 +359,10 @@ void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr,
/* viu mux */
#define VIU_MISC_CTRL0 0x1a06
/* 0xd0106818 */
#define VIU_MISC_CTRL1 0x1a07
#define VD1_AFBCD0_MISC_CTRL 0x1a0a
#define VIUB_SW_RESET 0x2001
#define VIUB_SW_RESET0 0x2002
#define VIUB_MISC_CTRL0 0x2006
/* 0xd0108018 */
#define VIUB_GCLK_CTRL0 0x2007
@@ -386,6 +390,208 @@ void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr,
#define DI_IF2_GEN_REG3 0x2022
/*txl new add end*/
/* g12 new added */
/* IF0 MIF */
#define DI_IF0_GEN_REG 0x2030
#define DI_IF0_CANVAS0 0x2031
#define DI_IF0_LUMA_X0 0x2032
#define DI_IF0_LUMA_Y0 0x2033
#define DI_IF0_CHROMA_X0 0x2034
#define DI_IF0_CHROMA_Y0 0x2035
#define DI_IF0_REPEAT_LOOP 0x2036
#define DI_IF0_LUMA0_RPT_PAT 0x2037
#define DI_IF0_CHROMA0_RPT_PAT 0x2038
#define DI_IF0_DUMMY_PIXEL 0x2039
#define DI_IF0_LUMA_FIFO_SIZE 0x203A
#define DI_IF0_RANGE_MAP_Y 0x203B
#define DI_IF0_RANGE_MAP_CB 0x203C
#define DI_IF0_RANGE_MAP_CR 0x203D
#define DI_IF0_GEN_REG2 0x203E
#define DI_IF0_FMT_CTRL 0x203F
#define DI_IF0_FMT_W 0x2040
#define DI_IF0_FMT_W 0x2040
#define DI_IF0_URGENT_CTRL 0x2041
#define DI_IF0_GEN_REG3 0x2042
/* AXI ARB */
#define DI_RDARB_MODE_L1C1 0x2050
#define DI_RDARB_REQEN_SLV_L1C1 0x2051
#define DI_RDARB_WEIGH0_SLV_L1C1 0x2052
#define DI_RDARB_WEIGH1_SLV_L1C1 0x2053
#define DI_WRARB_MODE_L1C1 0x2054
#define DI_WRARB_REQEN_SLV_L1C1 0x2055
#define DI_WRARB_WEIGH0_SLV_L1C1 0x2056
#define DI_WRARB_WEIGH1_SLV_L1C1 0x2057
#define DI_RDWR_ARB_STATUS_L1C1 0x2058
#define DI_ARB_DBG_CTRL_L1C1 0x2059
#define DI_ARB_DBG_STAT_L1C1 0x205a
#define DI_RDARB_UGT_L1C1 0x205b
#define DI_RDARB_LIMT0_L1C1 0x205c
#define DI_WRARB_UGT_L1C1 0x205d
#define DI_PRE_GL_CTRL 0x20ab
#define DI_PRE_GL_THD 0x20ac
#define DI_POST_GL_CTRL 0x20ad
#define DI_POST_GL_THD 0x20ae
#define DI_SUB_RDARB_MODE 0x37c0
#define DI_SUB_RDARB_REQEN_SLV 0x37c1
#define DI_SUB_RDARB_WEIGH0_SLV 0x37c2
#define DI_SUB_RDARB_WEIGH1_SLV 0x37c3
#define DI_SUB_RDARB_UGT 0x37c4
#define DI_SUB_RDARB_LIMT0 0x37c5
#define DI_SUB_WRARB_MODE 0x37c6
#define DI_SUB_WRARB_REQEN_SLV 0x37c7
#define DI_SUB_WRARB_WEIGH0_SLV 0x37c8
#define DI_SUB_WRARB_WEIGH1_SLV 0x37c9
#define DI_SUB_WRARB_UGT 0x37ca
#define DI_SUB_RDWR_ARB_STATUS 0x37cb
#define DI_SUB_ARB_DBG_CTRL 0x37cc
#define DI_SUB_ARB_DBG_STAT 0x37cd
#define CONTRD_CTRL1 0x37d0
#define CONTRD_CTRL2 0x37d1
#define CONTRD_SCOPE_X 0x37d2
#define CONTRD_SCOPE_Y 0x37d3
#define CONTRD_RO_STAT 0x37d4
#define CONT2RD_CTRL1 0x37d5
#define CONT2RD_CTRL2 0x37d6
#define CONT2RD_SCOPE_X 0x37d7
#define CONT2RD_SCOPE_Y 0x37d8
#define CONT2RD_RO_STAT 0x37d9
#define MTNRD_CTRL1 0x37da
#define MTNRD_CTRL2 0x37db
#define MTNRD_SCOPE_X 0x37dc
#define MTNRD_SCOPE_Y 0x37dd
#define MTNRD_RO_STAT 0x37de
#define MCVECRD_CTRL1 0x37df
#define MCVECRD_CTRL2 0x37e0
#define MCVECRD_SCOPE_X 0x37e1
#define MCVECRD_SCOPE_Y 0x37e2
#define MCVECRD_RO_STAT 0x37e3
#define MCINFRD_CTRL1 0x37e4
#define MCINFRD_CTRL2 0x37e5
#define MCINFRD_SCOPE_X 0x37e6
#define MCINFRD_SCOPE_Y 0x37e7
#define MCINFRD_RO_STAT 0x37e8
#define CONTWR_X 0x37e9
#define CONTWR_Y 0x37ea
#define CONTWR_CTRL 0x37eb
#define CONTWR_CAN_SIZE 0x37ec
#define MTNWR_X 0x37ed
#define MTNWR_Y 0x37ee
#define MTNWR_CTRL 0x37ef
#define MTNWR_CAN_SIZE 0x37f0
#define MCVECWR_X 0x37f1
#define MCVECWR_Y 0x37f2
#define MCVECWR_CTRL 0x37f3
#define MCVECWR_CAN_SIZE 0x37f4
#define MCINFWR_X 0x37f5
#define MCINFWR_Y 0x37f6
#define MCINFWR_CTRL 0x37f7
#define MCINFWR_CAN_SIZE 0x37f8
/* DI SCALE */
#define DI_SCO_FIFO_CTRL 0x374e
#define DI_SC_TOP_CTRL 0x374f
#define DI_SC_DUMMY_DATA 0x3750
#define DI_SC_LINE_IN_LENGTH 0x3751
#define DI_SC_PIC_IN_HEIGHT 0x3752
#define DI_SC_COEF_IDX 0x3753
#define DI_SC_COEF 0x3754
#define DI_VSC_REGION12_STARTP 0x3755
#define DI_VSC_REGION34_STARTP 0x3756
#define DI_VSC_REGION4_ENDP 0x3757
#define DI_VSC_START_PHASE_STEP 0x3758
#define DI_VSC_REGION0_PHASE_SLOPE 0x3759
#define DI_VSC_REGION1_PHASE_SLOPE 0x375a
#define DI_VSC_REGION3_PHASE_SLOPE 0x375b
#define DI_VSC_REGION4_PHASE_SLOPE 0x375c
#define DI_VSC_PHASE_CTRL 0x375d
#define DI_VSC_INI_PHASE 0x375e
#define DI_HSC_REGION12_STARTP 0x3760
#define DI_HSC_REGION34_STARTP 0x3761
#define DI_HSC_REGION4_ENDP 0x3762
#define DI_HSC_START_PHASE_STEP 0x3763
#define DI_HSC_REGION0_PHASE_SLOPE 0x3764
#define DI_HSC_REGION1_PHASE_SLOPE 0x3765
#define DI_HSC_REGION3_PHASE_SLOPE 0x3766
#define DI_HSC_REGION4_PHASE_SLOPE 0x3767
#define DI_HSC_PHASE_CTRL 0x3768
#define DI_SC_MISC 0x3769
#define DI_HSC_PHASE_CTRL1 0x376a
#define DI_HSC_INI_PAT_CTRL 0x376b
#define DI_SC_GCLK_CTRL 0x376c
#define DI_SC_HOLD_LINE 0x376d
/* DI HDR */
#define DI_HDR_IN_HSIZE 0x376e
#define DI_HDR_IN_VSIZE 0x376f
#define DI_HDR2_CTRL 0x3800
#define DI_HDR2_CLK_GATE 0x3881
#define DI_HDR2_MATRIXI_COEF00_01 0x3882
#define DI_HDR2_MATRIXI_COEF02_10 0x3883
#define DI_HDR2_MATRIXI_COEF11_12 0x3884
#define DI_HDR2_MATRIXI_COEF20_21 0x3885
#define DI_HDR2_MATRIXI_COEF22 0x3886
#define DI_HDR2_MATRIXI_COEF30_31 0x3887
#define DI_HDR2_MATRIXI_COEF32_40 0x3888
#define DI_HDR2_MATRIXI_COEF41_42 0x3889
#define DI_HDR2_MATRIXI_OFFSET0_1 0x388A
#define DI_HDR2_MATRIXI_OFFSET2 0x388B
#define DI_HDR2_MATRIXI_PRE_OFFSET0_1 0x388C
#define DI_HDR2_MATRIXI_PRE_OFFSET2 0x388D
#define DI_HDR2_MATRIXO_COEF00_01 0x388E
#define DI_HDR2_MATRIXO_COEF02_10 0x388F
#define DI_HDR2_MATRIXO_COEF11_12 0x3890
#define DI_HDR2_MATRIXO_COEF20_21 0x3891
#define DI_HDR2_MATRIXO_COEF22 0x3892
#define DI_HDR2_MATRIXO_COEF30_31 0x3893
#define DI_HDR2_MATRIXO_COEF32_40 0x3894
#define DI_HDR2_MATRIXO_COEF41_42 0x3895
#define DI_HDR2_MATRIXO_OFFSET0_1 0x3896
#define DI_HDR2_MATRIXO_OFFSET2 0x3897
#define DI_HDR2_MATRIXO_PRE_OFFSET0_1 0x3898
#define DI_HDR2_MATRIXO_PRE_OFFSET2 0x3899
#define DI_HDR2_MATRIXI_CLIP 0x389A
#define DI_HDR2_MATRIXO_CLIP 0x389B
#define DI_HDR2_CGAIN_OFFT 0x389C
#define DI_EOTF_LUT_ADDR_PORT 0x389E
#define DI_EOTF_LUT_DATA_PORT 0x389F
#define DI_OETF_LUT_ADDR_PORT 0x38A0
#define DI_OETF_LUT_DATA_PORT 0x38A1
#define DI_CGAIN_LUT_ADDR_PORT 0x38A2
#define DI_CGAIN_LUT_DATA_PORT 0x38A3
#define DI_HDR2_CGAIN_COEF0 0x38A4
#define DI_HDR2_CGAIN_COEF1 0x38A5
#define DI_OGAIN_LUT_ADDR_PORT 0x38A6
#define DI_OGAIN_LUT_DATA_PORT 0x38A7
#define DI_HDR2_ADPS_CTRL 0x38A8
#define DI_HDR2_ADPS_ALPHA0 0x38A9
#define DI_HDR2_ADPS_ALPHA1 0x38AA
#define DI_HDR2_ADPS_BETA0 0x38AB
#define DI_HDR2_ADPS_BETA1 0x38AC
#define DI_HDR2_ADPS_BETA2 0x38AD
#define DI_HDR2_ADPS_COEF0 0x38AE
#define DI_HDR2_ADPS_COEF1 0x38AF
#define DI_HDR2_GMUT_CTRL 0x38B0
#define DI_HDR2_GMUT_COEF0 0x38B1
#define DI_HDR2_GMUT_COEF1 0x38B2
#define DI_HDR2_GMUT_COEF2 0x38B3
#define DI_HDR2_GMUT_COEF3 0x38B4
#define DI_HDR2_GMUT_COEF4 0x38B5
#define DI_HDR2_PIPE_CTRL1 0x38B6
#define DI_HDR2_PIPE_CTRL2 0x38B7
#define DI_HDR2_PIPE_CTRL3 0x38B8
#define DI_HDR2_PROC_WIN1 0x38B9
#define DI_HDR2_PROC_WIN2 0x38BA
#define DI_HDR2_MATRIXI_EN_CTRL 0x38BB
#define DI_HDR2_MATRIXO_EN_CTRL 0x38BC
/* NR DOWNSAMPLE */
#define NRDSWR_X 0x37f9
#define NRDSWR_Y 0x37fa
#define NRDSWR_CTRL 0x37fb
#define NRDSWR_CAN_SIZE 0x37fc
#define NR_DS_BUF_SIZE_REG 0x3740
#define NR_DS_CTRL 0x3741
#define NR_DS_OFFSET 0x3742
#define NR_DS_BLD_COEF 0x3743
/* di */
#define DI_IF1_URGENT_CTRL (0x20a3) /* << 2 + 0xd0100000*/
/* bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 ,

8
drivers/amlogic/media/video_sink/video.c
View File

@@ -2685,9 +2685,13 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
}
DI_POST_WR_REG_BITS(DI_IF1_GEN_REG3,
(bit_mode&0x3), 8, 2);
if (is_meson_txl_cpu() || is_meson_txlx_cpu())
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX))
DI_POST_WR_REG_BITS(DI_IF2_GEN_REG3,
(bit_mode & 0x3), 8, 2);
(bit_mode & 0x3), 8, 2);
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
DI_POST_WR_REG_BITS(DI_IF0_GEN_REG3,
(bit_mode & 0x3), 8, 2);
vd1_path_select(false);
VSYNC_WR_MPEG_REG(AFBC_ENABLE, 0);
}

165
include/linux/amlogic/media/registers/regs/di_regs.h
View File

@@ -18,172 +18,8 @@
#ifndef DI_REGS_HEADER_
#define DI_REGS_HEADER_
#define DI_PRE_CTRL 0x1700
#define DI_POST_CTRL 0x1701
#define DI_POST_SIZE 0x1702
#define DI_PRE_SIZE 0x1703
#define DI_EI_CTRL0 0x1704
#define DI_EI_CTRL1 0x1705
#define DI_EI_CTRL2 0x1706
#define DI_NR_CTRL0 0x1707
#define DI_NR_CTRL1 0x1708
#define DI_NR_CTRL2 0x1709
#define DI_NR_CTRL3 0x170a
#define DI_MTN_CTRL 0x170b
#define DI_MTN_CTRL1 0x170c
#define DI_BLEND_CTRL 0x170d
#define DI_BLEND_CTRL1 0x170e
#define DI_BLEND_CTRL2 0x170f
#define DI_BLEND_REG0_X 0x1710
#define DI_BLEND_REG0_Y 0x1711
#define DI_BLEND_REG1_X 0x1712
#define DI_BLEND_REG1_Y 0x1713
#define DI_BLEND_REG2_X 0x1714
#define DI_BLEND_REG2_Y 0x1715
#define DI_BLEND_REG3_X 0x1716
#define DI_BLEND_REG3_Y 0x1717
#define DI_CLKG_CTRL 0x1718
#define DI_EI_CTRL3 0x1719
#define DI_EI_CTRL4 0x171a
#define DI_EI_CTRL5 0x171b
#define DI_EI_CTRL6 0x171c
#define DI_EI_CTRL7 0x171d
#define DI_EI_CTRL8 0x171e
#define DI_EI_CTRL9 0x171f
#define DI_EI_CTRL10 0x1793
#define DI_EI_CTRL11 0x179e
#define DI_EI_CTRL12 0x179f
#define DI_EI_CTRL13 0x17a8
#define DI_EI_XWIN0 0x1798
#define DI_EI_XWIN1 0x1799
#define DI_MC_REG0_X 0x1720
#define DI_MC_REG0_Y 0x1721
#define DI_MC_REG1_X 0x1722
#define DI_MC_REG1_Y 0x1723
#define DI_MC_REG2_X 0x1724
#define DI_MC_REG2_Y 0x1725
#define DI_MC_REG3_X 0x1726
#define DI_MC_REG3_Y 0x1727
#define DI_MC_REG4_X 0x1728
#define DI_MC_REG4_Y 0x1729
#define DI_MC_32LVL0 0x172a
#define DI_MC_32LVL1 0x172b
#define DI_MC_22LVL0 0x172c
#define DI_MC_22LVL1 0x172d
#define DI_MC_22LVL2 0x172e
#define DI_MC_CTRL 0x172f
#define DI_INTR_CTRL 0x1730
#define DI_INFO_ADDR 0x1731
#define DI_INFO_DATA 0x1732
#define DI_PRE_HOLD 0x1733
#define DI_MTN_1_CTRL1 0x1740
#define DI_MTN_1_CTRL2 0x1741
#define DI_MTN_1_CTRL3 0x1742
#define DI_MTN_1_CTRL4 0x1743
#define DI_MTN_1_CTRL5 0x1744
#define DI_MTN_1_CTRL6 0x17a9
#define DI_MTN_1_CTRL7 0x17aa
#define DI_MTN_1_CTRL8 0x17ab
#define DI_MTN_1_CTRL9 0x17ac
#define DI_MTN_1_CTRL10 0x17ad
#define DI_MTN_1_CTRL11 0x17ae
#define DI_MTN_1_CTRL12 0x17af
#define DET3D_MOTN_CFG 0x1734
#define DET3D_CB_CFG 0x1735
#define DET3D_SPLT_CFG 0x1736
#define DET3D_HV_MUTE 0x1737
#define DET3D_MAT_STA_P1M1 0x1738
#define DET3D_MAT_STA_P1TH 0x1739
#define DET3D_MAT_STA_M1TH 0x173a
#define DET3D_MAT_STA_RSFT 0x173b
#define DET3D_MAT_SYMTC_TH 0x173c
#define DET3D_RO_DET_CB_HOR 0x173d
#define DET3D_RO_DET_CB_VER 0x173e
#define DET3D_RO_SPLT_HT 0x173f
#define NR2_MET_NM_CTRL 0x1745
#define NR2_MET_NM_YCTRL 0x1746
#define NR2_MET_NM_CCTRL 0x1747
#define NR2_MET_NM_TNR 0x1748
#define NR2_MET_NMFRM_TNR_YLEV 0x1749
#define NR2_MET_NMFRM_TNR_YCNT 0x174a
#define NR2_MET_NMFRM_TNR_CLEV 0x174b
#define NR2_MET_NMFRM_TNR_CCNT 0x174c
#define NR2_3DEN_MODE 0x174d
#define NR2_IIR_CTRL 0x174e
#define NR2_SW_EN 0x174f
#define NR2_FRM_SIZE 0x1750
#define NR2_SNR_SAD_CFG 0x1751
#define NR2_MATNR_SNR_OS 0x1752
#define NR2_MATNR_SNR_NRM_CFG 0x1753
#define NR2_MATNR_SNR_NRM_GAIN 0x1754
#define NR2_MATNR_SNR_LPF_CFG 0x1755
#define NR2_MATNR_SNR_USF_GAIN 0x1756
#define NR2_MATNR_SNR_EDGE2B 0x1757
#define NR2_MATNR_BETA_EGAIN 0x1758
#define NR2_MATNR_BETA_BRT 0x1759
#define NR2_MATNR_XBETA_CFG 0x175a
#define NR2_MATNR_YBETA_SCL 0x175b
#define NR2_MATNR_CBETA_SCL 0x175c
#define NR2_SNR_MASK 0x175d
#define NR2_SAD2NORM_LUT0 0x175e
#define NR2_SAD2NORM_LUT1 0x175f
#define NR2_SAD2NORM_LUT2 0x1760
#define NR2_SAD2NORM_LUT3 0x1761
#define NR2_EDGE2BETA_LUT0 0x1762
#define NR2_EDGE2BETA_LUT1 0x1763
#define NR2_EDGE2BETA_LUT2 0x1764
#define NR2_EDGE2BETA_LUT3 0x1765
#define NR2_MOTION2BETA_LUT0 0x1766
#define NR2_MOTION2BETA_LUT1 0x1767
#define NR2_MOTION2BETA_LUT2 0x1768
#define NR2_MOTION2BETA_LUT3 0x1769
#define NR2_MATNR_MTN_CRTL 0x176a
#define NR2_MATNR_MTN_CRTL2 0x176b
#define NR2_MATNR_MTN_COR 0x176c
#define NR2_MATNR_MTN_GAIN 0x176d
#define NR2_MATNR_DEGHOST 0x176e
#define NR2_MATNR_ALPHALP_LUT0 0x176f
#define NR2_MATNR_ALPHALP_LUT1 0x1770
#define NR2_MATNR_ALPHALP_LUT2 0x1771
#define NR2_MATNR_ALPHALP_LUT3 0x1772
#define NR2_MATNR_ALPHAHP_LUT0 0x1773
#define NR2_MATNR_ALPHAHP_LUT1 0x1774
#define NR2_MATNR_ALPHAHP_LUT2 0x1775
#define NR2_MATNR_ALPHAHP_LUT3 0x1776
#define NR2_MATNR_MTNB_BRT 0x1777
#define NR2_CUE_MODE 0x1778
#define NR2_CUE_CON_MOT_TH 0x1779
#define NR2_CUE_CON_DIF0 0x177a
#define NR2_CUE_CON_DIF1 0x177b
#define NR2_CUE_CON_DIF2 0x177c
#define NR2_CUE_CON_DIF3 0x177d
#define NR2_CUE_PRG_DIF 0x177e
#define NR2_CONV_MODE 0x177f
#define DET3D_RO_SPLT_HB 0x1780
#define DET3D_RO_SPLT_VL 0x1781
#define DET3D_RO_SPLT_VR 0x1782
#define DET3D_RO_MAT_LUMA_LR 0x1783
#define DET3D_RO_MAT_LUMA_TB 0x1784
#define DET3D_RO_MAT_CHRU_LR 0x1785
#define DET3D_RO_MAT_CHRU_TB 0x1786
#define DET3D_RO_MAT_CHRV_LR 0x1787
#define DET3D_RO_MAT_CHRV_TB 0x1788
#define DET3D_RO_MAT_HEDG_LR 0x1789
#define DET3D_RO_MAT_HEDG_TB 0x178a
#define DET3D_RO_MAT_VEDG_LR 0x178b
#define DET3D_RO_MAT_VEDG_TB 0x178c
#define DET3D_RO_MAT_MOTN_LR 0x178d
#define DET3D_RO_MAT_MOTN_TB 0x178e
#define DET3D_RO_FRM_MOTN 0x178f
#define DET3D_RAMRD_ADDR_PORT 0x179a
#define DET3D_RAMRD_DATA_PORT 0x179b
#define NR2_CFR_PARA_CFG0 0x179c
#define NR2_CFR_PARA_CFG1 0x179d
#define DI_NR_1_CTRL0 0x1794
#define DI_NR_1_CTRL1 0x1795
#define DI_NR_1_CTRL2 0x1796
#define DI_NR_1_CTRL3 0x1797
#define DI_CONTWR_X 0x17a0
#define DI_CONTWR_Y 0x17a1
#define DI_CONTWR_CTRL 0x17a2
@@ -278,6 +114,7 @@
#define VD1_IF0_GEN_REG3 0x1aa7
#define DI_IF1_GEN_REG3 0x20a7
#define DI_IF2_GEN_REG3 0x2022
#define DI_IF0_GEN_REG3 0x2042
#endif