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Document: update dw_mipi_dsi document for RK3399

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There is a phy config clock in RK3399, it must be control by mipi
driver.

Change-Id: I5c029b79ae5867b652ab761dc7416f78f8e070d2
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
This commit is contained in:
Chris Zhong
2016-03-31 14:42:36 +08:00
committed by Huang, Tao
parent 596bbbc157
commit c59cd1723a
1 changed files with 9 additions and 3 deletions
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12
Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
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@@ -5,14 +5,19 @@ Required properties:
- #address-cells: Should be <1>.
- #size-cells: Should be <0>.
- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
or "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
- reg: Represent the physical address range of the controller.
- interrupts: Represent the controller's interrupt to the CPU(s).
- clocks, clock-names: Phandles to the controller's pll reference
clock(ref) and APB clock(pclk), as described in [1].
clock(ref) and APB clock(pclk) as described in [1].
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
- ports: contain a port node with endpoint definitions as defined in [2].
For vopb,set the reg = <0> and set the reg = <1> for vopl.
Optional properties
- clocks, clock-names: phandle to the mipi dsi phy config clock, name should be
"phy_cfg".
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/media/video-interfaces.txt
@@ -23,8 +28,9 @@ Example:
compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0xff960000 0x4000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
clock-names = "ref", "pclk";
clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>,
<&cru SCLK_DPHY_TX0_CFG>;
clock-names = "ref", "pclk", "phy_cfg";
rockchip,grf = <&grf>;
status = "okay";