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ARM: dts: rockchip: add support of dwc2 controller for rk3128

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This patch add the node of dwc2 controller and u2phy for rk3128.

Change-Id: Iafc6b71d0dda9c9e46fa925a2d21e4bf59a1adee
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
This commit is contained in:
Meng Dongyang
2017-09-14 15:54:03 +08:00
parent 30bc22da1b
commit c5bbe16d4f
1 changed files with 46 additions and 0 deletions
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46
arch/arm/boot/dts/rk312x.dtsi
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@@ -343,6 +343,23 @@
interrupts = <GIC_PPI 9 0xf04>;
};
usb_otg: usb@10180000 {
compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb",
"snps,dwc2";
reg = <0x10180000 0x40000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG>;
clock-names = "otg";
dr_mode = "otg";
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <275>;
g-tx-fifo-size = <256 128 128 64 64 32>;
g-use-dma;
phys = <&u2phy_otg>;
phy-names = "usb2-phy";
status = "disabled";
};
sdmmc: dwmmc@10214000 {
compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
@@ -411,6 +428,35 @@
grf: syscon@20008000 {
compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
reg = <0x20008000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
u2phy: usb2-phy@17c {
compatible = "rockchip,rk3128-usb2phy";
reg = <0x017c 0x0c>;
clocks = <&cru SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
clock-output-names = "usb480m_phy";
status = "disabled";
u2phy_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "otg-bvalid", "otg-id",
"linestate";
status = "disabled";
};
u2phy_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "linestate";
status = "disabled";
};
};
};
lvds: lvds@20038000 {