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clk: rockchip: rv1126: Add CLK_SET_RATE_PARENT for frac clocks

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Change-Id: I42246998087b2277cfd2bc66bbd65b16f6418ddb
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2020-04-09 21:22:39 +08:00
committed by Tao Huang
parent b6373f87a9
commit c5f8db9979
1 changed files with 11 additions and 11 deletions
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22
drivers/clk/rockchip/clk-rv1126.c
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@@ -346,7 +346,7 @@ static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
COMPOSITE(SCLK_UART1_DIV, "sclk_uart1_div", mux_gpll_usb480m_cpll_xin24m_p, 0,
RV1126_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS,
RV1126_PMU_CLKGATE_CON(0), 12, GFLAGS),
COMPOSITE_FRACMUX(SCLK_UART1_FRACDIV, "sclk_uart1_fracdiv", "sclk_uart1_div", 0,
COMPOSITE_FRACMUX(SCLK_UART1_FRACDIV, "sclk_uart1_fracdiv", "sclk_uart1_div", CLK_SET_RATE_PARENT,
RV1126_PMU_CLKSEL_CON(5), 0,
RV1126_PMU_CLKGATE_CON(0), 13, GFLAGS,
&rv1126_uart1_fracmux, RV1126_FRAC_MAX_PRATE),
@@ -540,7 +540,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
COMPOSITE(SCLK_UART0_DIV, "sclk_uart0_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
RV1126_CLKSEL_CON(10), 8, 2, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(5), 1, GFLAGS),
COMPOSITE_FRACMUX(SCLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", 0,
COMPOSITE_FRACMUX(SCLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(11), 0,
RV1126_CLKGATE_CON(5), 2, GFLAGS,
&rv1126_uart0_fracmux, RV1126_FRAC_MAX_PRATE),
@@ -551,7 +551,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
COMPOSITE(SCLK_UART2_DIV, "sclk_uart2_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
RV1126_CLKSEL_CON(12), 8, 2, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(5), 5, GFLAGS),
COMPOSITE_FRACMUX(SCLK_UART2_FRAC, "sclk_uart2_frac", "sclk_uart2_div", 0,
COMPOSITE_FRACMUX(SCLK_UART2_FRAC, "sclk_uart2_frac", "sclk_uart2_div", CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(13), 0,
RV1126_CLKGATE_CON(5), 6, GFLAGS,
&rv1126_uart2_fracmux, RV1126_FRAC_MAX_PRATE),
@@ -562,7 +562,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
COMPOSITE(SCLK_UART3_DIV, "sclk_uart3_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
RV1126_CLKSEL_CON(14), 8, 2, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(5), 9, GFLAGS),
COMPOSITE_FRACMUX(SCLK_UART3_FRAC, "sclk_uart3_frac", "sclk_uart3_div", 0,
COMPOSITE_FRACMUX(SCLK_UART3_FRAC, "sclk_uart3_frac", "sclk_uart3_div", CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(15), 0,
RV1126_CLKGATE_CON(5), 10, GFLAGS,
&rv1126_uart3_fracmux, RV1126_FRAC_MAX_PRATE),
@@ -573,7 +573,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
COMPOSITE(SCLK_UART4_DIV, "sclk_uart4_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
RV1126_CLKSEL_CON(16), 8, 2, MFLAGS, 0, 7,
DFLAGS, RV1126_CLKGATE_CON(5), 13, GFLAGS),
COMPOSITE_FRACMUX(SCLK_UART4_FRAC, "sclk_uart4_frac", "sclk_uart4_div", 0,
COMPOSITE_FRACMUX(SCLK_UART4_FRAC, "sclk_uart4_frac", "sclk_uart4_div", CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(17), 0,
RV1126_CLKGATE_CON(5), 14, GFLAGS,
&rv1126_uart4_fracmux, RV1126_FRAC_MAX_PRATE),
@@ -584,7 +584,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
COMPOSITE(SCLK_UART5_DIV, "sclk_uart5_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
RV1126_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7,
DFLAGS, RV1126_CLKGATE_CON(6), 1, GFLAGS),
COMPOSITE_FRACMUX(SCLK_UART5_FRAC, "sclk_uart5_frac", "sclk_uart5_div", 0,
COMPOSITE_FRACMUX(SCLK_UART5_FRAC, "sclk_uart5_frac", "sclk_uart5_div", CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(19), 0,
RV1126_CLKGATE_CON(6), 2, GFLAGS,
&rv1126_uart5_fracmux, RV1126_FRAC_MAX_PRATE),
@@ -745,7 +745,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
COMPOSITE(MCLK_I2S0_TX_DIV, "mclk_i2s0_tx_div", mux_cpll_gpll_p, 0,
RV1126_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(9), 5, GFLAGS),
COMPOSITE_FRACMUX(MCLK_I2S0_TX_FRACDIV, "mclk_i2s0_tx_fracdiv", "mclk_i2s0_tx_div", 0,
COMPOSITE_FRACMUX(MCLK_I2S0_TX_FRACDIV, "mclk_i2s0_tx_fracdiv", "mclk_i2s0_tx_div", CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(28), 0,
RV1126_CLKGATE_CON(9), 6, GFLAGS,
&rv1126_i2s0_tx_fracmux, RV1126_FRAC_MAX_PRATE),
@@ -754,7 +754,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
COMPOSITE(MCLK_I2S0_RX_DIV, "mclk_i2s0_rx_div", mux_cpll_gpll_p, 0,
RV1126_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 7, DFLAGS,
RV1126_CLKGATE_CON(9), 7, GFLAGS),
COMPOSITE_FRACMUX(MCLK_I2S0_RX_FRACDIV, "mclk_i2s0_rx_fracdiv", "mclk_i2s0_rx_div", 0,
COMPOSITE_FRACMUX(MCLK_I2S0_RX_FRACDIV, "mclk_i2s0_rx_fracdiv", "mclk_i2s0_rx_div", CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(29), 0,
RV1126_CLKGATE_CON(9), 8, GFLAGS,
&rv1126_i2s0_rx_fracmux, RV1126_FRAC_MAX_PRATE),
@@ -786,7 +786,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
COMPOSITE(MCLK_I2S2_DIV, "mclk_i2s2_div", mux_cpll_gpll_p, 0,
RV1126_CLKSEL_CON(33), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(10), 6, GFLAGS),
COMPOSITE_FRACMUX(MCLK_I2S2_FRACDIV, "mclk_i2s2_fracdiv", "mclk_i2s2_div", 0,
COMPOSITE_FRACMUX(MCLK_I2S2_FRACDIV, "mclk_i2s2_fracdiv", "mclk_i2s2_div", CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(34), 0,
RV1126_CLKGATE_CON(10), 7, GFLAGS,
&rv1126_i2s2_fracmux, RV1126_FRAC_MAX_PRATE),
@@ -807,7 +807,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
COMPOSITE(SCLK_ADUPWM_DIV, "sclk_audpwm_div", mux_gpll_cpll_p, 0,
RV1126_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(10), 13, GFLAGS),
COMPOSITE_FRACMUX(SCLK_AUDPWM_FRACDIV, "sclk_audpwm_fracdiv", "sclk_audpwm_div", 0,
COMPOSITE_FRACMUX(SCLK_AUDPWM_FRACDIV, "sclk_audpwm_fracdiv", "sclk_audpwm_div", CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(37), 0,
RV1126_CLKGATE_CON(10), 14, GFLAGS,
&rv1126_audpwm_fracmux, RV1126_FRAC_MAX_PRATE),
@@ -921,7 +921,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
COMPOSITE(DCLK_VOP_DIV, "dclk_vop_div", mux_gpll_cpll_p, 0,
RV1126_CLKSEL_CON(47), 8, 1, MFLAGS, 0, 8, DFLAGS,
RV1126_CLKGATE_CON(14), 11, GFLAGS),
COMPOSITE_FRACMUX(DCLK_VOP_FRACDIV, "dclk_vop_fracdiv", "dclk_vop_div", 0,
COMPOSITE_FRACMUX(DCLK_VOP_FRACDIV, "dclk_vop_fracdiv", "dclk_vop_div", CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(48), 0,
RV1126_CLKGATE_CON(14), 12, GFLAGS,
&rv1126_dclk_vop_fracmux, RV1126_FRAC_MAX_PRATE),