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clk: rockchip: px30: Let npll only provide clock for vopl and gpu

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As npll rate may be changed according to vopl dclk rate on px30.

Change-Id: I4abc042b49ee06436ba5d69dc8adfa9460da37f7
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Finley Xiao
2018-08-15 15:29:07 +08:00
committed by Tao Huang
parent fdd1e215f5
commit c6edde69b3
1 changed files with 6 additions and 6 deletions
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12
drivers/clk/rockchip/clk-px30.c
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@@ -145,11 +145,11 @@ PNAME(mux_gpll_dmycpll_usb480m_dmynpll_p) = { "gpll", "dummy_cpll", "usb480m", "
PNAME(mux_cpll_npll_p) = { "cpll", "npll" };
PNAME(mux_npll_cpll_p) = { "npll", "cpll" };
PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" };
PNAME(mux_gpll_npll_p) = { "gpll", "npll" };
PNAME(mux_gpll_npll_p) = { "gpll", "dummy_npll" };
PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m"};
PNAME(mux_gpll_cpll_npll_p) = { "gpll", "dummy_cpll", "npll" };
PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "dummy_cpll", "npll", "xin24m" };
PNAME(mux_gpll_xin24m_npll_p) = { "gpll", "xin24m", "npll"};
PNAME(mux_gpll_cpll_npll_p) = { "gpll", "dummy_cpll", "dummy_npll" };
PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "dummy_cpll", "dummy_npll", "xin24m" };
PNAME(mux_gpll_xin24m_npll_p) = { "gpll", "xin24m", "dummy_npll"};
PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" };
PNAME(mux_i2s0_tx_p) = { "clk_i2s0_tx_src", "clk_i2s0_tx_frac", "mclk_i2s0_tx_in", "xin12m"};
PNAME(mux_i2s0_rx_p) = { "clk_i2s0_rx_src", "clk_i2s0_rx_frac", "mclk_i2s0_rx_in", "xin12m"};
@@ -161,13 +161,13 @@ PNAME(mux_i2s1_out_p) = { "clk_i2s1", "xin12m"};
PNAME(mux_i2s2_out_p) = { "clk_i2s2", "xin12m"};
PNAME(mux_i2s0_tx_rx_p) = { "clk_i2s0_tx_mux", "clk_i2s0_rx_mux"};
PNAME(mux_i2s0_rx_tx_p) = { "clk_i2s0_rx_mux", "clk_i2s0_tx_mux"};
PNAME(mux_uart_src_p) = { "gpll", "xin24m", "usb480m", "npll" };
PNAME(mux_uart_src_p) = { "gpll", "xin24m", "usb480m", "dummy_npll" };
PNAME(mux_uart1_p) = { "clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac" };
PNAME(mux_uart2_p) = { "clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac" };
PNAME(mux_uart3_p) = { "clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac" };
PNAME(mux_uart4_p) = { "clk_uart4_src", "clk_uart4_np5", "clk_uart4_frac" };
PNAME(mux_uart5_p) = { "clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac" };
PNAME(mux_cif_out_p) = { "xin24m", "dummy_cpll", "npll", "usb480m" };
PNAME(mux_cif_out_p) = { "xin24m", "dummy_cpll", "dummy_npll", "usb480m" };
PNAME(mux_dclk_vopb_p) = { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" };
PNAME(mux_dclk_vopl_p) = { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" };
PNAME(mux_nandc_p) = { "clk_nandc_div", "clk_nandc_div50" };