CHROMIUM: [media]: rockchip-vpu: add rk3288 h264e

Change-Id: Idf6697c107609f5ee80a39c08a5670bebe78c469 Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
2026-06-08 20:07:46 +09:00 · 2016-06-20 16:56:41 +08:00
parent 105d23b05f
commit c6f73493cc
8 changed files with 1679 additions and 8 deletions
--- a/drivers/media/platform/rockchip-vpu/Makefile
+++ b/drivers/media/platform/rockchip-vpu/Makefile
@@ -7,5 +7,6 @@ rockchip-vpu-y += rockchip_vpu.o \
 		rockchip_vpu_hw.o \
 		rk3288_vpu_hw.o \
 		rk3288_vpu_hw_h264d.o \
+		rk3288_vpu_hw_h264e.o \
 		rk3288_vpu_hw_vp8d.o \
-		rk3288_vpu_hw_vp8e.o
+		rk3288_vpu_hw_vp8e.o \
--- a/drivers/media/platform/rockchip-vpu/rk3288_vpu_hw_h264e.c
+++ b/drivers/media/platform/rockchip-vpu/rk3288_vpu_hw_h264e.c
--- a/drivers/media/platform/rockchip-vpu/rk3288_vpu_regs.h
+++ b/drivers/media/platform/rockchip-vpu/rk3288_vpu_regs.h
@@ -40,10 +40,13 @@
 #define VEPU_REG_ADDR_IN_CB			0x030
 #define VEPU_REG_ADDR_IN_CR			0x034
 #define VEPU_REG_ENC_CTRL			0x038
+#define     VEPU_REG_ENC_CTRL_TIMEOUT_EN	BIT(31)
 #define     VEPU_REG_ENC_CTRL_NAL_MODE_BIT	BIT(29)
 #define     VEPU_REG_ENC_CTRL_WIDTH(w)		((w) << 19)
 #define     VEPU_REG_ENC_CTRL_HEIGHT(h)		((h) << 10)
+#define     VEPU_REG_PIC_TYPE(x)		(((x) & 0x3) << 3)
 #define     VEPU_REG_ENC_CTRL_KEYFRAME_BIT	BIT(3)
+#define     VEPU_REG_ENC_CTRL_ENC_MODE_H264	(0x3 << 1)
 #define     VEPU_REG_ENC_CTRL_ENC_MODE_VP8	(0x1 << 1)
 #define     VEPU_REG_ENC_CTRL_EN_BIT		BIT(0)
 #define VEPU_REG_IN_IMG_CTRL			0x03c
@@ -52,27 +55,82 @@
 #define     VEPU_REG_IN_IMG_CTRL_OVRFLB_D4(x)	((x) << 6)
 #define     VEPU_REG_IN_IMG_CTRL_FMT(x)		((x) << 2)
 #define VEPU_REG_ENC_CTRL0			0x040
+#define    VEPU_REG_ENC_CTRL0_INIT_QP(x)		((x) << 26)
+#define    VEPU_REG_ENC_CTRL0_SLICE_ALPHA(x)		((x) << 22)
+#define    VEPU_REG_ENC_CTRL0_SLICE_BETA(x)		((x) << 18)
+#define    VEPU_REG_ENC_CTRL0_CHROMA_QP_OFFSET(x)	((x) << 13)
+#define    VEPU_REG_ENC_CTRL0_FILTER_DIS(x)		((x) << 5)
+#define    VEPU_REG_ENC_CTRL0_IDR_PICID(x)		((x) << 1)
+#define    VEPU_REG_ENC_CTRL0_CONSTR_INTRA_PRED	BIT(0)
 #define VEPU_REG_ENC_CTRL1			0x044
+#define    VEPU_REG_ENC_CTRL1_PPS_ID(x)			((x) << 24)
+#define    VEPU_REG_ENC_CTRL1_INTRA_PRED_MODE(x)	((x) << 16)
+#define    VEPU_REG_ENC_CTRL1_FRAME_NUM(x)		((x))
 #define VEPU_REG_ENC_CTRL2			0x048
+#define    VEPU_REG_ENC_CTRL2_DEBLOCKING_FILETER_MODE(x)	((x) << 30)
+#define    VEPU_REG_ENC_CTRL2_H264_SLICE_SIZE(x)		((x) << 23)
+#define    VEPU_REG_ENC_CTRL2_DISABLE_QUARTER_PIXMV		BIT(22)
+#define    VEPU_REG_ENC_CTRL2_TRANS8X8_MODE_EN			BIT(21)
+#define    VEPU_REG_ENC_CTRL2_CABAC_INIT_IDC(x)			((x) << 19)
+#define    VEPU_REG_ENC_CTRL2_ENTROPY_CODING_MODE		BIT(18)
+#define    VEPU_REG_ENC_CTRL2_H264_INTER4X4_MODE		BIT(17)
+#define    VEPU_REG_ENC_CTRL2_H264_STREAM_MODE			BIT(16)
+#define    VEPU_REG_ENC_CTRL2_INTRA16X16_MODE(x)		((x))
 #define VEPU_REG_ENC_CTRL3			0x04c
-#define VEPU_REG_ENC_CTRL5			0x050
-#define VEPU_REG_ENC_CTRL4			0x054
+#define    VEPU_REG_ENC_CTRL3_MUTIMV_EN			BIT(30)
+#define    VEPU_REG_ENC_CTRL3_MV_PENALTY_1_4P(x)	((x) << 20)
+#define    VEPU_REG_ENC_CTRL3_MV_PENALTY_4P(x)		((x) << 10)
+#define    VEPU_REG_ENC_CTRL3_MV_PENALTY_1P(x)		((x))
+#define VEPU_REG_ENC_CTRL4			0x050
+#define    VEPU_REG_ENC_CTRL4_MV_PENALTY_16X8_8X16(x)	((x) << 20)
+#define    VEPU_REG_ENC_CTRL4_MV_PENALTY_8X8(x)		((x) << 10)
+#define    VEPU_REG_ENC_CTRL4_8X4_4X8(x)		((x))
+#define VEPU_REG_ENC_CTRL5			0x054
+#define    VEPU_REG_ENC_CTRL5_MACROBLOCK_PENALTY(x)	((x) << 24)
+#define    VEPU_REG_ENC_CTRL5_COMPLETE_SLICES(x)	((x) << 16)
+#define    VEPU_REG_ENC_CTRL5_INTER_MODE(x)		((x))
 #define VEPU_REG_STR_HDR_REM_MSB		0x058
 #define VEPU_REG_STR_HDR_REM_LSB		0x05c
 #define VEPU_REG_STR_BUF_LIMIT			0x060
 #define VEPU_REG_MAD_CTRL			0x064
+#define    VEPU_REG_MAD_CTRL_QP_ADJUST(x)	((x) << 28)
+#define    VEPU_REG_MAD_CTRL_MAD_THREDHOLD(x)	((x) << 22)
+#define    VEPU_REG_MAD_CTRL_QP_SUM_DIV2(x)	((x))
 #define VEPU_REG_ADDR_VP8_PROB_CNT		0x068
 #define VEPU_REG_QP_VAL				0x06c
+#define    VEPU_REG_QP_VAL_LUM(x)		((x) << 26)
+#define    VEPU_REG_QP_VAL_MAX(x)		((x) << 20)
+#define    VEPU_REG_QP_VAL_MIN(x)		((x) << 14)
+#define    VEPU_REG_QP_VAL_CHECKPOINT_DISTAN(x)	((x))
 #define VEPU_REG_VP8_QP_VAL(i)			(0x06c + ((i) * 0x4))
 #define VEPU_REG_CHECKPOINT(i)			(0x070 + ((i) * 0x4))
+#define     VEPU_REG_CHECKPOINT_CHECK0(x)	(((x) & 0xffff))
+#define     VEPU_REG_CHECKPOINT_CHECK1(x)	(((x) & 0xffff) << 16)
+#define     VEPU_REG_CHECKPOINT_RESULT(x)	((((x) >> (16 - 16 \
+						 * (i & 1))) & 0xffff) \
+						 * 32)
 #define VEPU_REG_CHKPT_WORD_ERR(i)		(0x084 + ((i) * 0x4))
+#define     VEPU_REG_CHKPT_WORD_ERR_CHK0(x)	(((x) & 0xffff))
+#define     VEPU_REG_CHKPT_WORD_ERR_CHK1(x)	(((x) & 0xffff) << 16)
 #define VEPU_REG_VP8_BOOL_ENC			0x08c
 #define VEPU_REG_CHKPT_DELTA_QP			0x090
+#define     VEPU_REG_CHKPT_DELTA_QP_CHK0(x)	(((x) & 0x0f) << 0)
+#define     VEPU_REG_CHKPT_DELTA_QP_CHK1(x)	(((x) & 0x0f) << 4)
+#define     VEPU_REG_CHKPT_DELTA_QP_CHK2(x)	(((x) & 0x0f) << 8)
+#define     VEPU_REG_CHKPT_DELTA_QP_CHK3(x)	(((x) & 0x0f) << 12)
+#define     VEPU_REG_CHKPT_DELTA_QP_CHK4(x)	(((x) & 0x0f) << 16)
+#define     VEPU_REG_CHKPT_DELTA_QP_CHK5(x)	(((x) & 0x0f) << 20)
+#define     VEPU_REG_CHKPT_DELTA_QP_CHK6(x)	(((x) & 0x0f) << 24)
 #define VEPU_REG_VP8_CTRL0			0x090
 #define VEPU_REG_RLC_CTRL			0x094
 #define     VEPU_REG_RLC_CTRL_STR_OFFS_SHIFT	23
 #define     VEPU_REG_RLC_CTRL_STR_OFFS_MASK	(0x3f << 23)
+#define     VEPU_REG_RLC_CTRL_RLC_SUM(x)	((x))
 #define VEPU_REG_MB_CTRL			0x098
+#define     VEPU_REG_MB_CNT_OUT(x)		(((x) & 0xffff))
+#define     VEPU_REG_MB_CNT_SET(x)		(((x) & 0xffff) << 16)
+#define VEPU_REG_ADDR_NEXT_PIC			0x09c
+#define VEPU_REG_STABLILIZATION_OUTPUT		0x0A0
 #define VEPU_REG_ADDR_CABAC_TBL			0x0cc
 #define VEPU_REG_ADDR_MV_OUT			0x0d0
 #define VEPU_REG_RGB_YUV_COEFF(i)		(0x0d4 + ((i) * 0x4))
@@ -84,11 +142,14 @@
 #define VEPU_REG_FIRST_ROI_AREA			0x0f0
 #define VEPU_REG_SECOND_ROI_AREA		0x0f4
 #define VEPU_REG_MVC_CTRL			0x0f8
+#define	VEPU_REG_MVC_CTRL_MV16X16_FAVOR(x)	((x) << 28)
 #define VEPU_REG_VP8_INTRA_PENALTY(i)		(0x100 + ((i) * 0x4))
 #define VEPU_REG_ADDR_VP8_SEG_MAP		0x11c
 #define VEPU_REG_VP8_SEG_QP(i)			(0x120 + ((i) * 0x4))
 #define VEPU_REG_DMV_4P_1P_PENALTY(i)		(0x180 + ((i) * 0x4))
+#define     VEPU_REG_DMV_4P_1P_PENALTY_BIT(x, i)	(x << i * 8)
 #define VEPU_REG_DMV_QPEL_PENALTY(i)		(0x200 + ((i) * 0x4))
+#define     VEPU_REG_DMV_QPEL_PENALTY_BIT(x, i)	(x << i * 8)
 #define VEPU_REG_VP8_CTRL1			0x280
 #define VEPU_REG_VP8_BIT_COST_GOLDEN		0x284
 #define VEPU_REG_VP8_LOOP_FLT_DELTA(i)		(0x288 + ((i) * 0x4))
--- a/drivers/media/platform/rockchip-vpu/rockchip_vpu.c
+++ b/drivers/media/platform/rockchip-vpu/rockchip_vpu.c
@@ -224,6 +224,86 @@ void rockchip_vpu_try_context(struct rockchip_vpu_dev *dev,
 	vpu_debug_enter();
 }

+/*
+ * bit stream assembler
+ */
+
+static int stream_buffer_status(struct stream_s *stream)
+{
+	if (stream->byte_cnt + 5 > stream->size) {
+		stream->overflow = 1;
+		return -1;
+	}
+
+	return 0;
+}
+
+void stream_put_bits(struct stream_s *buffer, s32 value, s32 number,
+		     const char *name)
+{
+	s32 bits;
+	u32 byte_buffer = buffer->byte_buffer;
+	u8 *stream = buffer->stream;
+
+	if (stream_buffer_status(buffer) != 0)
+		return;
+
+	vpu_debug(0, "assemble %s value %x, bits %d\n", name, value, number);
+
+	BUG_ON(value >= (1 << number));
+	BUG_ON(number >= 25);
+
+	bits = number + buffer->buffered_bits;
+	value <<= (32 - bits);
+	byte_buffer = byte_buffer | value;
+
+	while (bits > 7) {
+		*stream = (u8)(byte_buffer >> 24);
+
+		bits -= 8;
+		byte_buffer <<= 8;
+		stream++;
+		buffer->byte_cnt++;
+	}
+
+	buffer->byte_buffer = byte_buffer;
+	buffer->buffered_bits = (u8)bits;
+	buffer->stream = stream;
+
+	return;
+}
+
+void stream_buffer_reset(struct stream_s *buffer)
+{
+	buffer->stream = buffer->buffer;
+	buffer->byte_cnt = 0;
+	buffer->overflow = 0;
+	buffer->byte_buffer = 0;
+	buffer->buffered_bits = 0;
+}
+
+int stream_buffer_init(struct stream_s *buffer, u8 *stream, s32 size)
+{
+	if (stream == NULL) {
+		buffer->stream = kzalloc(size, GFP_KERNEL);
+	}
+
+	if (buffer->stream == NULL) {
+		vpu_err("allocate stream buffer failed\n");
+		return -1;
+	}
+
+	buffer->buffer = buffer->stream;
+	buffer->size = size;
+
+	stream_buffer_reset(buffer);
+
+	if (stream_buffer_status(buffer) != 0)
+		return -1;
+
+	return 0;
+}
+
 /*
 * Control registration.
 */
--- a/drivers/media/platform/rockchip-vpu/rockchip_vpu_common.h
+++ b/drivers/media/platform/rockchip-vpu/rockchip_vpu_common.h
@@ -77,20 +77,22 @@ struct rockchip_vpu_variant {
 * enum rockchip_vpu_codec_mode - codec operating mode.
 * @RK_VPU_CODEC_NONE:		Used for RAW video formats.
 * @RK3288_VPU_CODEC_H264D:	Rk3288 H264 decoder.
+ * @RK3288_VPU_CODEC_H264E:	Rk3288 H264 encoder.
 * @RK3288_VPU_CODEC_VP8D:	Rk3288 VP8 decoder.
 * @RK3288_VPU_CODEC_VP8E:	Rk3288 VP8 encoder.
 */
 enum rockchip_vpu_codec_mode {
 	RK_VPU_CODEC_NONE	= (1 << 0),
 	RK3288_VPU_CODEC_H264D	= (1 << 1),
-	RK3288_VPU_CODEC_VP8D	= (1 << 2),
-	RK3288_VPU_CODEC_VP8E	= (1 << 3),
+	RK3288_VPU_CODEC_H264E	= (1 << 2),
+	RK3288_VPU_CODEC_VP8D	= (1 << 3),
+	RK3288_VPU_CODEC_VP8E	= (1 << 4),
 };

 #define ROCKCHIP_VPU_DECODERS	(RK3288_VPU_CODEC_H264D | RK3288_VPU_CODEC_VP8D)
-#define ROCKCHIP_VPU_ENCODERS	(RK3288_VPU_CODEC_VP8E)
+#define ROCKCHIP_VPU_ENCODERS	(RK3288_VPU_CODEC_H264E | RK3288_VPU_CODEC_VP8E)

-#define RK3288_CODECS		(RK_VPU_CODEC_NONE | RK3288_VPU_CODEC_H264D | RK3288_VPU_CODEC_VP8D | RK3288_VPU_CODEC_VP8E)
+#define RK3288_CODECS		(RK_VPU_CODEC_NONE | RK3288_VPU_CODEC_H264D | RK3288_VPU_CODEC_H264E | RK3288_VPU_CODEC_VP8D | RK3288_VPU_CODEC_VP8E)

 /**
 * enum rockchip_vpu_plane - indices of planes inside a VB2 buffer.
@@ -123,6 +125,18 @@ struct rockchip_vpu_vp8e_buf_data {
 	u8 header[ROCKCHIP_HEADER_SIZE];
 };

+/**
+ * struct rockchip_vpu_h264e_buf_data - mode-specific per-buffer data
+ * @sps_size:		Size of sps data in the buffer.
+ * @pps_size:		Size of pps data in the buffer.
+ * @slices_size:	Size of slices data in the buffer.
+ */
+struct rockchip_vpu_h264e_buf_data {
+	size_t sps_size;
+	size_t pps_size;
+	size_t slices_size;
+};
+
 /**
 * struct rockchip_vpu_buf - Private data related to each VB2 buffer.
 * @vb:			Pointer to related VB2 buffer.
@@ -134,6 +148,7 @@ struct rockchip_vpu_buf {

 	/* Mode-specific data. */
 	union {
+		struct rockchip_vpu_h264e_buf_data h264e;
 		struct rockchip_vpu_vp8e_buf_data vp8e;
 	};
 };
@@ -233,7 +248,7 @@ struct rockchip_vpu_run_ops {
 *		by user space.
 */
 struct rockchip_vpu_vp8e_run {
-		const struct rockchip_reg_params *reg_params;
+	const struct rockchip_reg_params *reg_params;
 };

 /**
@@ -266,6 +281,33 @@ struct rockchip_vpu_h264d_run {
 	u8 dpb_map[16];
 };

+/* struct for assemble bitstream */
+struct stream_s {
+	u8 *buffer; /* point to first byte of stream */
+	u8 *stream; /* Pointer to next byte of stream */
+	u32 size;   /* Byte size of stream buffer */
+	u32 byte_cnt;    /* Byte counter */
+	u32 bit_cnt; /* Bit counter */
+	u32 byte_buffer; /* Byte buffer */
+	u32 buffered_bits;   /* Amount of bits in byte buffer, [0-7] */
+	s32 overflow;    /* This will signal a buffer overflow */
+};
+
+void stream_put_bits(struct stream_s *buffer, s32 value, s32 number,
+		     const char *name);
+void stream_buffer_reset(struct stream_s *buffer);
+int stream_buffer_init(struct stream_s *buffer, u8 *stream, s32 size);
+
+/**
+ * struct rockchip_vpu_h264e_run - per-run data specific to H264 encoding.
+ */
+struct rockchip_vpu_h264e_run {
+	const struct rockchip_reg_params *reg_params;
+	struct stream_s sps;
+	struct stream_s pps;
+	u32 hw_write_offset;
+};
+
 /**
 * struct rockchip_vpu_run - per-run data for hardware code.
 * @src:		Source buffer to be processed.
@@ -286,6 +328,7 @@ struct rockchip_vpu_run {
 		struct rockchip_vpu_vp8e_run vp8e;
 		struct rockchip_vpu_vp8d_run vp8d;
 		struct rockchip_vpu_h264d_run h264d;
+		struct rockchip_vpu_h264e_run h264e;
 		/* Other modes will need different data. */
 	};
 };
--- a/drivers/media/platform/rockchip-vpu/rockchip_vpu_enc.c
+++ b/drivers/media/platform/rockchip-vpu/rockchip_vpu_enc.c
@@ -95,6 +95,12 @@ static struct rockchip_vpu_fmt formats[] = {
 		.codec_mode = RK3288_VPU_CODEC_VP8E,
 		.num_planes = 1,
 	},
+	{
+		.name = "H264 Encoded Stream",
+		.fourcc = V4L2_PIX_FMT_H264,
+		.codec_mode = RK3288_VPU_CODEC_H264E,
+		.num_planes = 1,
+	},
 };

 static struct rockchip_vpu_fmt *find_format(struct rockchip_vpu_dev *dev, u32 fourcc, bool bitstream)
@@ -1171,6 +1177,13 @@ static void rockchip_vpu_buf_finish(struct vb2_buffer *vb)

 		buf = vb_to_buf(vb);
 		rockchip_vpu_vp8e_assemble_bitstream(ctx, buf);
+	} else if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
+	    && vb->state == VB2_BUF_STATE_DONE
+	    && ctx->vpu_dst_fmt->fourcc == V4L2_PIX_FMT_H264) {
+		struct rockchip_vpu_buf *buf;
+
+		buf = vb_to_buf(vb);
+		rockchip_vpu_h264e_assemble_bitstream(ctx, buf);
 	}

 	vpu_debug_leave();
@@ -1330,6 +1343,9 @@ static void rockchip_vpu_enc_prepare_run(struct rockchip_vpu_ctx *ctx)
 		memcpy(ctx->run.priv_src.cpu,
 			get_ctrl_ptr(ctx, ROCKCHIP_VPU_ENC_CTRL_HW_PARAMS),
 			ROCKCHIP_HW_PARAMS_SIZE);
+	} else if (ctx->vpu_dst_fmt->fourcc == V4L2_PIX_FMT_H264) {
+		ctx->run.h264e.reg_params = get_ctrl_ptr(ctx,
+			ROCKCHIP_VPU_ENC_CTRL_REG_PARAMS);
 	}
 }

--- a/drivers/media/platform/rockchip-vpu/rockchip_vpu_hw.c
+++ b/drivers/media/platform/rockchip-vpu/rockchip_vpu_hw.c
@@ -330,6 +330,15 @@ static const struct rockchip_vpu_codec_ops mode_ops[] = {
 		.done = rockchip_vpu_run_done,
 		.reset = rk3288_vpu_dec_reset,
 	},
+	{
+		.codec_mode = RK3288_VPU_CODEC_H264E,
+		.init = rk3288_vpu_h264e_init,
+		.exit = rk3288_vpu_h264e_exit,
+		.irq = rk3288_vpu_enc_irq,
+		.run = rk3288_vpu_h264e_run,
+		.done = rk3288_vpu_h264e_done,
+		.reset = rk3288_vpu_enc_reset,
+	},
 	{
 		.codec_mode = RK3288_VPU_CODEC_H264D,
 		.init = rk3288_vpu_h264d_init,
@@ -429,3 +438,31 @@ void rockchip_vpu_vp8e_assemble_bitstream(struct rockchip_vpu_ctx *ctx,
 	vb2_set_plane_payload(&dst_buf->vb.vb2_buf, 0,
 				hdr_size + ext_hdr_size + dct_size);
 }
+
+void rockchip_vpu_h264e_assemble_bitstream(struct rockchip_vpu_ctx *ctx,
+					struct rockchip_vpu_buf *dst_buf)
+{
+	size_t sps_size = dst_buf->h264e.sps_size;
+	size_t pps_size = dst_buf->h264e.pps_size;
+	size_t slices_size = dst_buf->h264e.slices_size;
+	size_t dst_size;
+	void *dst;
+
+	struct stream_s *sps = &ctx->run.h264e.sps;
+	struct stream_s *pps = &ctx->run.h264e.pps;
+
+	dst_size = vb2_plane_size(&dst_buf->vb.vb2_buf, 0);
+	dst = vb2_plane_vaddr(&dst_buf->vb.vb2_buf, 0);
+
+	if (WARN_ON(sps_size + pps_size + slices_size > dst_size))
+		return;
+
+	vpu_debug(1, "%s: sps_size = %u, pps_size = %u, slices_size = %u\n",
+		__func__, sps_size, pps_size, slices_size);
+
+	memcpy(dst, sps->buffer, sps_size);
+	memcpy(dst + sps_size, pps->buffer, pps_size);
+
+	vb2_set_plane_payload(&dst_buf->vb.vb2_buf, 0,
+			      sps_size + pps_size + slices_size);
+}
--- a/drivers/media/platform/rockchip-vpu/rockchip_vpu_hw.h
+++ b/drivers/media/platform/rockchip-vpu/rockchip_vpu_hw.h
@@ -84,16 +84,57 @@ struct rk3288_vp8e_reg_params {
 	u32 loop_flt_delta[2];
 };

+/**
+ * struct rk3288_h264e_reg_params - low level encoding parameters
+ * TODO: Create abstract structures for more generic controls or just
+ *       remove unused fields.
+ */
+struct rk3288_h264e_reg_params {
+	u32 frame_coding_type;
+	s32 pic_init_qp;
+	s32 slice_alpha_offset;
+	s32 slice_beta_offset;
+	s32 chroma_qp_index_offset;
+	s32 filter_disable;
+	u16 idr_pic_id;
+	s32 pps_id;
+	s32 frame_num;
+	s32 slice_size_mb_rows;
+	s32 h264_inter4x4_disabled;
+	s32 enable_cabac;
+	s32 transform8x8_mode;
+	s32 cabac_init_idc;
+
+	/* rate control relevant */
+	s32 qp;
+	s32 mad_qp_delta;
+	s32 mad_threshold;
+	s32 qp_min;
+	s32 qp_max;
+	s32 cp_distance_mbs;
+	s32 cp_target[10];
+	s32 target_error[7];
+	s32 delta_qp[7];
+};
+
 /**
 * struct rockchip_reg_params - low level encoding parameters
 */
 struct rockchip_reg_params {
 	/* Mode-specific data. */
 	union {
+		const struct rk3288_h264e_reg_params rk3288_h264e;
 		const struct rk3288_vp8e_reg_params rk3288_vp8e;
 	};
 };

+struct rockchip_vpu_h264e_feedback {
+	s32 qp_sum;
+	s32 cp[10];
+	s32 mad_count;
+	s32 rlc_count;
+};
+
 /**
 * struct rockchip_vpu_aux_buf - auxiliary DMA buffer for hardware data
 * @cpu:	CPU pointer to the buffer.
@@ -138,6 +179,18 @@ struct rockchip_vpu_h264d_hw_ctx {
 	struct rockchip_vpu_aux_buf priv_tbl;
 };

+/**
+ * struct rockchip_vpu_h264e_hw_ctx - Context private data specific to codec mode.
+ * @ctrl_buf:		H264 control buffer.
+ * @ext_buf:		H264 ext data buffer.
+ * @ref_rec_ptr:	Bit flag for swapping ref and rec buffers every frame.
+ */
+struct rockchip_vpu_h264e_hw_ctx {
+	struct rockchip_vpu_aux_buf cabac_tbl[3];
+	struct rockchip_vpu_aux_buf ext_buf;
+	u8 ref_rec_ptr:1;
+};
+
 /**
 * struct rockchip_vpu_hw_ctx - Context private data of hardware code.
 * @codec_ops:		Set of operations associated with current codec mode.
@@ -149,6 +202,7 @@ struct rockchip_vpu_hw_ctx {
 	union {
 		struct rockchip_vpu_vp8e_hw_ctx vp8e;
 		struct rockchip_vpu_vp8d_hw_ctx vp8d;
+		struct rockchip_vpu_h264e_hw_ctx h264e;
 		struct rockchip_vpu_h264d_hw_ctx h264d;
 		/* Other modes will need different data. */
 	};
@@ -175,6 +229,13 @@ int rk3288_vpu_h264d_init(struct rockchip_vpu_ctx *ctx);
 void rk3288_vpu_h264d_exit(struct rockchip_vpu_ctx *ctx);
 void rk3288_vpu_h264d_run(struct rockchip_vpu_ctx *ctx);

+/* Run ops for rk3288 h264 encoder */
+int rk3288_vpu_h264e_init(struct rockchip_vpu_ctx *ctx);
+void rk3288_vpu_h264e_exit(struct rockchip_vpu_ctx *ctx);
+void rk3288_vpu_h264e_run(struct rockchip_vpu_ctx *ctx);
+void rk3288_vpu_h264e_done(struct rockchip_vpu_ctx *ctx,
+			  enum vb2_buffer_state result);
+
 /* Run ops for rk3288 VP8 decoder */
 int rk3288_vpu_vp8d_init(struct rockchip_vpu_ctx *ctx);
 void rk3288_vpu_vp8d_exit(struct rockchip_vpu_ctx *ctx);
@@ -186,9 +247,12 @@ void rk3288_vpu_vp8e_exit(struct rockchip_vpu_ctx *ctx);
 void rk3288_vpu_vp8e_run(struct rockchip_vpu_ctx *ctx);
 void rk3288_vpu_vp8e_done(struct rockchip_vpu_ctx *ctx,
 			  enum vb2_buffer_state result);
+
 const struct rockchip_reg_params *rk3288_vpu_vp8e_get_dummy_params(void);

 void rockchip_vpu_vp8e_assemble_bitstream(struct rockchip_vpu_ctx *ctx,
 					struct rockchip_vpu_buf *dst_buf);
+void rockchip_vpu_h264e_assemble_bitstream(struct rockchip_vpu_ctx *ctx,
+					struct rockchip_vpu_buf *dst_buf);

 #endif /* ROCKCHIP_VPU_HW_H_ */