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drm/bridge: dw-mipi-dsi: make lane byte clock cycles more accurate

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Change-Id: Ic510ef14161fdd1aa5441220520df50bb371ade4
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
This commit is contained in:
Guochun Huang
2021-09-01 08:54:51 +08:00
committed by Tao Huang
parent 494a1a53f2
commit c7a13590bd
1 changed files with 6 additions and 6 deletions
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12
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
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@@ -710,16 +710,16 @@ static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
const struct drm_display_mode *mode,
u32 hcomponent)
{
u32 frac, lbcc;
u32 lbcc;
lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
frac = lbcc % mode->clock;
lbcc = lbcc / mode->clock;
if (frac)
lbcc++;
if (mode->clock == 0) {
DRM_ERROR("dsi mode clock is 0!\n");
return 0;
}
return lbcc;
return DIV_ROUND_CLOSEST_ULL(lbcc, mode->clock);
}
static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,