shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-10 12:57:06 +09:00
Code Issues Packages Projects Releases Wiki Activity

vpp: refresh the vd/osd blend ctrl when enable/disable video [1/1]

Browse Source 
PD#SWPL-4932

Problem:
The vd/osd blend ctrl is not correct when disable video

Solution:
Refresh the vd/osd blend ctrl for that case

Verify:
Verified on tl1

Change-Id: I6a7bfc58c810279cdfbf55f3d6a51e94890b4899
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>
This commit is contained in:
Brian Zhu
2019-03-02 20:52:35 +08:00
committed by Jianxin Pan
parent 8cf5a4d254
commit c7d92b9f02
1 changed files with 6 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/amlogic/media/video_sink/video.c
View File

@@ -5949,6 +5949,7 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
int video2_off_req = 0;
struct vframe_s *cur_dispbuf_back = cur_dispbuf;
static struct vframe_s *pause_vf;
int force_flush = 0;
if (debug_flag & DEBUG_FLAG_VSYNC_DONONE)
return IRQ_HANDLED;
@@ -7349,6 +7350,7 @@ SET_FILTER:
pr_info("VsyncEnableVideoLayer\n");
vpu_delay_work_flag |=
VPU_VIDEO_LAYER1_CHANGED;
force_flush = 1;
} else if (video_onoff_state == VIDEO_ENABLE_STATE_OFF_REQ) {
vpp_misc_set &= ~(VPP_VD1_PREBLEND |
VPP_VD1_POSTBLEND);
@@ -7368,6 +7370,7 @@ SET_FILTER:
if (debug_flag & DEBUG_FLAG_BLACKOUT)
pr_info("VsyncDisableVideoLayer\n");
video1_off_req = 1;
force_flush = 1;
}
spin_unlock_irqrestore(&video_onoff_lock, flags);
@@ -7418,6 +7421,7 @@ SET_FILTER:
if (debug_flag & DEBUG_FLAG_BLACKOUT)
pr_info("VsyncEnableVideoLayer2\n");
force_flush = 1;
} else if (video2_onoff_state == VIDEO_ENABLE_STATE_OFF_REQ) {
vpp_misc_set &= ~(VPP_VD2_PREBLEND |
VPP_VD2_POSTBLEND | VPP_PREBLEND_EN
@@ -7428,6 +7432,7 @@ SET_FILTER:
if (debug_flag & DEBUG_FLAG_BLACKOUT)
pr_info("VsyncDisableVideoLayer2\n");
video2_off_req = 1;
force_flush = 1;
}
spin_unlock_irqrestore(&video2_onoff_lock, flags);
}
@@ -7471,7 +7476,7 @@ SET_FILTER:
if (!legacy_vpp) {
u32 set_value = 0;
int force_flush = vpp_zorder_check();
force_flush |= vpp_zorder_check();
/* for sr core0, put it between prebld & pps as default */
if (cur_frame_par &&