shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-08 03:40:35 +09:00
Code Issues Packages Projects Releases Wiki Activity

3036: start secondary_startup

Browse Source
This commit is contained in:
wdc
2014-07-09 15:19:47 +08:00
parent b365f68f64
commit c81930b2d7
1 changed files with 90 additions and 69 deletions
Download Patch File Download Diff File Expand all files Collapse all files

159
arch/arm/mach-rockchip/rk3036.c
View File

@@ -53,45 +53,45 @@
static struct map_desc rk3036_io_desc[] __initdata = {
RK3036_DEVICE(CRU),
RK3036_DEVICE(GRF),
RK3036_DEVICE(ROM),
RK3036_DEVICE(EFUSE),
RK_DEVICE(RK_DDR_VIRT, RK3036_DDR_PCTL_PHYS, RK3036_DDR_PCTL_SIZE),
RK_DEVICE(RK_DDR_VIRT + RK3036_DDR_PCTL_SIZE, RK3036_DDR_PHY_PHYS, RK3036_DDR_PHY_SIZE),
RK_DEVICE(RK_GPIO_VIRT(0), RK3036_GPIO0_PHYS, RK3036_GPIO_SIZE),
RK_DEVICE(RK_GPIO_VIRT(1), RK3036_GPIO1_PHYS, RK3036_GPIO_SIZE),
RK_DEVICE(RK_GPIO_VIRT(2), RK3036_GPIO2_PHYS, RK3036_GPIO_SIZE),
RK_DEVICE(RK_DEBUG_UART_VIRT, RK3036_UART2_PHYS, RK3036_UART_SIZE),
RK_DEVICE(RK_GIC_VIRT, RK3036_GIC_DIST_PHYS, RK3036_GIC_DIST_SIZE),
RK_DEVICE(RK_GIC_VIRT + RK3036_GIC_DIST_SIZE,RK3036_GIC_CPU_PHYS, RK3036_GIC_CPU_SIZE),
RK_DEVICE(RK3036_IMEM_VIRT, RK3036_IMEM_PHYS, SZ_4K),
RK_DEVICE(RK_TIMER_VIRT, RK3036_TIMER_PHYS, RK3036_TIMER_SIZE),
RK3036_DEVICE(CRU),
RK3036_DEVICE(GRF),
RK3036_DEVICE(ROM),
RK3036_DEVICE(EFUSE),
RK_DEVICE(RK_DDR_VIRT, RK3036_DDR_PCTL_PHYS, RK3036_DDR_PCTL_SIZE),
RK_DEVICE(RK_DDR_VIRT + RK3036_DDR_PCTL_SIZE, RK3036_DDR_PHY_PHYS, RK3036_DDR_PHY_SIZE),
RK_DEVICE(RK_GPIO_VIRT(0), RK3036_GPIO0_PHYS, RK3036_GPIO_SIZE),
RK_DEVICE(RK_GPIO_VIRT(1), RK3036_GPIO1_PHYS, RK3036_GPIO_SIZE),
RK_DEVICE(RK_GPIO_VIRT(2), RK3036_GPIO2_PHYS, RK3036_GPIO_SIZE),
RK_DEVICE(RK_DEBUG_UART_VIRT, RK3036_UART2_PHYS, RK3036_UART_SIZE),
RK_DEVICE(RK_GIC_VIRT, RK3036_GIC_DIST_PHYS, RK3036_GIC_DIST_SIZE),
RK_DEVICE(RK_GIC_VIRT + RK3036_GIC_DIST_SIZE,RK3036_GIC_CPU_PHYS, RK3036_GIC_CPU_SIZE),
RK_DEVICE(RK3036_IMEM_VIRT, RK3036_IMEM_PHYS, SZ_4K),
RK_DEVICE(RK_TIMER_VIRT, RK3036_TIMER_PHYS, RK3036_TIMER_SIZE),
};
static void __init rk3036_boot_mode_init(void)
{
u32 flag = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_OS_REG0);
u32 mode = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_OS_REG1);
u32 rst_st = readl_relaxed(RK_CRU_VIRT + RK3036_CRU_RST_ST);
u32 flag = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_OS_REG0);
u32 mode = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_OS_REG1);
u32 rst_st = readl_relaxed(RK_CRU_VIRT + RK3036_CRU_RST_ST);
if (flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER))
mode = BOOT_MODE_RECOVERY;
if (rst_st & ((1 << 2) | (1 << 3)))
mode = BOOT_MODE_WATCHDOG;
rockchip_boot_mode_init(flag, mode);
if (flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER))
mode = BOOT_MODE_RECOVERY;
if (rst_st & ((1 << 2) | (1 << 3)))
mode = BOOT_MODE_WATCHDOG;
rockchip_boot_mode_init(flag, mode);
}
static void usb_uart_init(void)
{
u32 soc_status0 = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_STATUS0);
writel_relaxed(0x34000000, RK_GRF_VIRT + RK3036_GRF_UOC1_CON4);
u32 soc_status0 = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_STATUS0);
writel_relaxed(0x34000000, RK_GRF_VIRT + RK3036_GRF_UOC1_CON4);
#ifdef CONFIG_RK_USB_UART
if (!(soc_status0 & (1 << 14)) && (soc_status0 & (1 << 17))) {
/* software control usb phy enable */
writel_relaxed(0x007f0055, RK_GRF_VIRT + RK3036_GRF_UOC0_CON5);
writel_relaxed(0x34003000, RK_GRF_VIRT + RK3036_GRF_UOC1_CON4);
}
if (!(soc_status0 & (1 << 14)) && (soc_status0 & (1 << 17))) {
/* software control usb phy enable */
writel_relaxed(0x007f0055, RK_GRF_VIRT + RK3036_GRF_UOC0_CON5);
writel_relaxed(0x34003000, RK_GRF_VIRT + RK3036_GRF_UOC1_CON4);
}
#endif
#ifdef RK_DEBUG_UART_VIRT
writel_relaxed(0x07, RK_DEBUG_UART_VIRT + 0x88);
@@ -106,26 +106,47 @@ static void usb_uart_init(void)
static void __init rk3036_dt_map_io(void)
{
rockchip_soc_id = ROCKCHIP_SOC_RK3036;
rockchip_soc_id = ROCKCHIP_SOC_RK3036;
iotable_init(rk3036_io_desc, ARRAY_SIZE(rk3036_io_desc));
debug_ll_io_init();
usb_uart_init();
iotable_init(rk3036_io_desc, ARRAY_SIZE(rk3036_io_desc));
debug_ll_io_init();
usb_uart_init();
/* enable timer5 for core */
writel_relaxed(0, RK3036_TIMER5_VIRT + 0x10);
dsb();
writel_relaxed(0xFFFFFFFF, RK3036_TIMER5_VIRT + 0x00);
writel_relaxed(0xFFFFFFFF, RK3036_TIMER5_VIRT + 0x04);
dsb();
writel_relaxed(1, RK3036_TIMER5_VIRT + 0x10);
dsb();
/* enable timer5 for core */
writel_relaxed(0, RK3036_TIMER5_VIRT + 0x10);
dsb();
writel_relaxed(0xFFFFFFFF, RK3036_TIMER5_VIRT + 0x00);
writel_relaxed(0xFFFFFFFF, RK3036_TIMER5_VIRT + 0x04);
dsb();
writel_relaxed(1, RK3036_TIMER5_VIRT + 0x10);
dsb();
rk3036_boot_mode_init();
rk3036_boot_mode_init();
}
extern void secondary_startup(void);
static int rk3036_sys_set_power_domain(enum pmu_power_domain pd, bool on)
{
if (on) {
#ifdef CONFIG_SMP
if(PD_CPU_1 == pd) {
writel_relaxed(0x20000, RK_CRU_VIRT + RK3036_CRU_SOFTRST0_CON);
dsb();
udelay(10);
writel_relaxed(virt_to_phys(secondary_startup), RK3036_IMEM_VIRT + 8);
writel_relaxed(0xDEADBEAF, RK3036_IMEM_VIRT + 4);
dsb_sev();
}
#endif
} else {
#ifdef CONFIG_SMP
if(PD_CPU_1 == pd) {
writel_relaxed(0x20002, RK_CRU_VIRT + RK3036_CRU_SOFTRST0_CON);
dsb();
}
#endif
}
return 0;
}
@@ -141,11 +162,11 @@ static int rk3036_pmu_set_idle_request(enum pmu_idle_req req, bool idle)
static void __init rk3036_dt_init_timer(void)
{
rockchip_pmu_ops.set_power_domain = rk3036_sys_set_power_domain;
rockchip_pmu_ops.power_domain_is_on = rk3036_pmu_power_domain_is_on;
rockchip_pmu_ops.set_idle_request = rk3036_pmu_set_idle_request;
of_clk_init(NULL);
clocksource_of_init();
rockchip_pmu_ops.set_power_domain = rk3036_sys_set_power_domain;
rockchip_pmu_ops.power_domain_is_on = rk3036_pmu_power_domain_is_on;
rockchip_pmu_ops.set_idle_request = rk3036_pmu_set_idle_request;
of_clk_init(NULL);
clocksource_of_init();
}
static void __init rk3036_init_late(void)
@@ -155,41 +176,41 @@ static void __init rk3036_init_late(void)
static void __init rk3036_reserve(void)
{
/* reserve memory for ION */
//rockchip_ion_reserve();
/* reserve memory for ION */
//rockchip_ion_reserve();
return;
}
static void rk3036_restart(char mode, const char *cmd)
{
u32 boot_flag, boot_mode;
u32 boot_flag, boot_mode;
rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode);
rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode);
writel_relaxed(boot_flag, RK_GRF_VIRT + RK3036_GRF_OS_REG0); // for loader
writel_relaxed(boot_mode, RK_GRF_VIRT + RK3036_GRF_OS_REG1); // for linux
dsb();
writel_relaxed(boot_flag, RK_GRF_VIRT + RK3036_GRF_OS_REG0); // for loader
writel_relaxed(boot_mode, RK_GRF_VIRT + RK3036_GRF_OS_REG1); // for linux
dsb();
/* pll enter slow mode */
writel_relaxed(0x30110000, RK_CRU_VIRT + RK3036_CRU_MODE_CON);
dsb();
writel_relaxed(0xeca8, RK_CRU_VIRT + RK3036_CRU_GLB_SRST_SND_VALUE);
dsb();
/* pll enter slow mode */
writel_relaxed(0x30110000, RK_CRU_VIRT + RK3036_CRU_MODE_CON);
dsb();
writel_relaxed(0xeca8, RK_CRU_VIRT + RK3036_CRU_GLB_SRST_SND_VALUE);
dsb();
}
static const char * const rk3036_dt_compat[] __initconst = {
"rockchip,rk3036",
NULL,
"rockchip,rk3036",
NULL,
};
DT_MACHINE_START(RK3036_DT, "Rockchip RK3036")
.dt_compat = rk3036_dt_compat,
.smp = smp_ops(rockchip_smp_ops),
.reserve = rk3036_reserve,
.map_io = rk3036_dt_map_io,
.init_time = rk3036_dt_init_timer,
.init_late = rk3036_init_late,
.reserve = rk3036_reserve,
.restart = rk3036_restart,
.dt_compat = rk3036_dt_compat,
.smp = smp_ops(rockchip_smp_ops),
.reserve = rk3036_reserve,
.map_io = rk3036_dt_map_io,
.init_time = rk3036_dt_init_timer,
.init_late = rk3036_init_late,
.reserve = rk3036_reserve,
.restart = rk3036_restart,
MACHINE_END