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drm/rockchip: vop2: Add uv_mst and ymirror register for Esmart/Smart win

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Smart and Esmart support yuv and ymirror, But all the multi area in
one windows share the same ymirror bits. This give a strict limitation
on compositor: the compositor must enable DRM_MODE_REFLECT_Y for all
the multi area plane or disable all of them, otherwise will cause
a iommu pagefault as multie area don't know how to fetch data
from framebuffer.

Change-Id: I52d6f0766f023b6b71ad3a8aace78f38d285c10c
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
This commit is contained in:
Andy Yan
2020-11-14 11:44:39 +08:00
committed by Tao Huang
parent 113273a924
commit c83df779fd
2 changed files with 6 additions and 2 deletions
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5
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -1599,8 +1599,8 @@ static void vop2_plane_atomic_update(struct drm_plane *plane, struct drm_plane_s
VOP_AFBC_SET(vop2, win, rotate_90, vpstate->rotate_90_en);
} else {
VOP_AFBC_SET(vop2, win, enable, 0);
VOP_WIN_SET(vop2, win, ymirror, vpstate->xmirror_en);
VOP_WIN_SET(vop2, win, xmirror, vpstate->ymirror_en);
VOP_WIN_SET(vop2, win, ymirror, vpstate->ymirror_en);
VOP_WIN_SET(vop2, win, xmirror, vpstate->xmirror_en);
}
if (vpstate->rotate_90_en || vpstate->rotate_270_en) {
@@ -3833,6 +3833,7 @@ static int vop2_win_init(struct vop2 *vop2)
area->nformats = win->nformats;
area->max_upscale_factor = win_data->max_upscale_factor;
area->max_downscale_factor = win_data->max_downscale_factor;
area->supported_rotations = win_data->supported_rotations;
area->vop2 = vop2;
area->win_id = i;
area->phys_id = win->phys_id;

3
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -675,6 +675,7 @@ static const struct vop2_win_regs rk3568_area2_data = {
.dsp_info = VOP_REG(RK3568_ESMART0_REGION2_DSP_INFO, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3568_ESMART0_REGION2_DSP_ST, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3568_ESMART0_REGION2_YRGB_MST, 0xffffffff, 0),
.uv_mst = VOP_REG(RK3568_ESMART0_REGION2_CBR_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3568_ESMART0_REGION2_VIR, 0xffff, 0),
.uv_vir = VOP_REG(RK3568_ESMART0_REGION2_VIR, 0xffff, 16),
};
@@ -688,6 +689,7 @@ static const struct vop2_win_regs rk3568_area3_data = {
.dsp_info = VOP_REG(RK3568_ESMART0_REGION3_DSP_INFO, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3568_ESMART0_REGION3_DSP_ST, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3568_ESMART0_REGION3_YRGB_MST, 0xffffffff, 0),
.uv_mst = VOP_REG(RK3568_ESMART0_REGION3_CBR_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3568_ESMART0_REGION3_VIR, 0xffff, 0),
.uv_vir = VOP_REG(RK3568_ESMART0_REGION3_VIR, 0xffff, 16),
};
@@ -733,6 +735,7 @@ static const struct vop2_win_regs rk3568_esmart_win_data = {
.y2r_en = VOP_REG(RK3568_ESMART0_CTRL0, 0x1, 0),
.r2y_en = VOP_REG(RK3568_ESMART0_CTRL0, 0x1, 1),
.csc_mode = VOP_REG(RK3568_ESMART0_CTRL0, 0x3, 2),
.ymirror = VOP_REG(RK3568_ESMART0_CTRL1, 0x1, 31),
};
/*