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drm/rockchip: dsi: fix phy power-on sequence
Change-Id: I0ceaedb71776747e8951a75409bcc2521252dd18 Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
@@ -155,6 +155,8 @@
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#define PHY_STOPSTATE0LANE BIT(4)
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#define PHY_STOPSTATECLKLANE BIT(2)
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#define PHY_LOCK BIT(0)
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#define PHY_STOPSTATELANE (PHY_STOPSTATE0LANE | \
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PHY_STOPSTATECLKLANE)
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#define DSI_PHY_TST_CTRL0 0x0b4
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#define PHY_TESTCLK BIT(1)
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#define PHY_TESTCLR BIT(0)
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@@ -169,72 +171,21 @@
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#define DSI_INT_MSK1 0x0c8
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#define DSI_MAX_REGISGER DSI_INT_MSK1
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/* control/test codes for DWC MIPI D-PHY Bidir 4L */
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/* Test Code: 0x44 (HS RX Control of Lane 0) */
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#define HSFREQRANGE(x) UPDATE(x, 6, 1)
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/* Test Code: 0x17 (PLL Input Divider Ratio) */
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#define INPUT_DIV(x) UPDATE(x, 6, 0)
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/* Test Code: 0x18 (PLL Loop Divider Ratio) */
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#define FEEDBACK_DIV_LO(x) UPDATE(x, 4, 0)
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#define FEEDBACK_DIV_HI(x) (BIT(7) | UPDATE(x, 3, 0))
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/* Test Code: 0x19 (PLL Input and Loop Divider Ratios Control) */
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#define FEEDBACK_DIV_DEF_VAL_BYPASS BIT(5)
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#define INPUT_DIV_DEF_VAL_BYPASS BIT(4)
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#define PHY_STATUS_TIMEOUT_US 10000
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#define CMD_PKT_STATUS_TIMEOUT_US 20000
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#define BYPASS_VCO_RANGE BIT(7)
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#define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
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#define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
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#define VCO_IN_CAP_CON_LOW (0x1 << 1)
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#define VCO_IN_CAP_CON_HIGH (0x2 << 1)
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#define REF_BIAS_CUR_SEL BIT(0)
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#define CP_CURRENT_3MA BIT(3)
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#define CP_PROGRAM_EN BIT(7)
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#define LPF_PROGRAM_EN BIT(6)
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#define LPF_RESISTORS_20_KOHM 0
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#define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
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#define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
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#define LOW_PROGRAM_EN 0
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#define HIGH_PROGRAM_EN BIT(7)
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#define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
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#define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0x1f)
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#define PLL_LOOP_DIV_EN BIT(5)
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#define PLL_INPUT_DIV_EN BIT(4)
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#define POWER_CONTROL BIT(6)
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#define INTERNAL_REG_CURRENT BIT(3)
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#define BIAS_BLOCK_ON BIT(2)
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#define BANDGAP_ON BIT(0)
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#define TER_RESISTOR_HIGH BIT(7)
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#define TER_RESISTOR_LOW 0
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#define LEVEL_SHIFTERS_ON BIT(6)
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#define TER_CAL_DONE BIT(5)
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#define SETRD_MAX (0x7 << 2)
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#define POWER_MANAGE BIT(1)
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#define TER_RESISTORS_ON BIT(0)
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#define BIASEXTR_SEL(val) ((val) & 0x7)
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#define BANDGAP_SEL(val) ((val) & 0x7)
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#define TLP_PROGRAM_EN BIT(7)
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#define THS_PRE_PROGRAM_EN BIT(7)
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#define THS_ZERO_PROGRAM_EN BIT(6)
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enum {
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BANDGAP_97_07,
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BANDGAP_98_05,
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BANDGAP_99_02,
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BANDGAP_100_00,
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BANDGAP_93_17,
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BANDGAP_94_15,
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BANDGAP_95_12,
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BANDGAP_96_10,
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};
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enum {
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BIASEXTR_87_1,
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BIASEXTR_91_5,
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BIASEXTR_95_9,
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BIASEXTR_100,
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BIASEXTR_105_94,
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BIASEXTR_111_88,
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BIASEXTR_118_8,
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BIASEXTR_127_7,
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};
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enum dpi_color_coding {
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DPI_COLOR_CODING_16BIT_1,
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DPI_COLOR_CODING_16BIT_2,
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@@ -309,36 +260,6 @@ struct dw_mipi_dsi {
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const struct dw_mipi_dsi_plat_data *pdata;
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};
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struct dphy_pll_testdin_map {
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unsigned int max_mbps;
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u8 testdin;
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};
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/* The table is based on 27MHz DPHY pll reference clock. */
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static const struct dphy_pll_testdin_map dptdin_map[] = {
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{ 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
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{ 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
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{ 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
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{ 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
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{ 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
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{ 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
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{ 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
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{1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
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{1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
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{1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
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};
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static int max_mbps_to_testdin(unsigned int max_mbps)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
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if (dptdin_map[i].max_mbps > max_mbps)
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return dptdin_map[i].testdin;
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return -EINVAL;
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}
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static void grf_field_write(struct dw_mipi_dsi *dsi, enum grf_reg_fields index,
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unsigned int val)
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{
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@@ -386,22 +307,6 @@ static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
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return container_of(encoder, struct dw_mipi_dsi, encoder);
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}
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/**
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* ns2bc - Nanoseconds to byte clock cycles
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*/
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static inline unsigned int ns2bc(struct dw_mipi_dsi *dsi, int ns)
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{
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return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
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}
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/**
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* ns2ui - Nanoseconds to UI time periods
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*/
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static inline unsigned int ns2ui(struct dw_mipi_dsi *dsi, int ns)
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{
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return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
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}
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static inline void testif_testclk_assert(struct dw_mipi_dsi *dsi)
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{
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regmap_update_bits(dsi->regmap, DSI_PHY_TST_CTRL0,
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@@ -500,92 +405,76 @@ static int testif_read(void *context, unsigned int reg, unsigned int *value)
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return 0;
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}
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static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
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static inline void mipi_dphy_enableclk_assert(struct dw_mipi_dsi *dsi)
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{
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struct mipi_dphy *dphy = &dsi->dphy;
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int ret, testdin, vco, val;
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regmap_update_bits(dsi->regmap, DSI_PHY_RSTZ,
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PHY_ENABLECLK, PHY_ENABLECLK);
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udelay(1);
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}
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vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
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static inline void mipi_dphy_enableclk_deassert(struct dw_mipi_dsi *dsi)
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{
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regmap_update_bits(dsi->regmap, DSI_PHY_RSTZ, PHY_ENABLECLK, 0);
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udelay(1);
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}
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testdin = max_mbps_to_testdin(dsi->lane_mbps);
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if (testdin < 0) {
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DRM_DEV_ERROR(dsi->dev,
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"failed to get testdin for %dmbps lane clock\n",
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dsi->lane_mbps);
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return testdin;
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}
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static inline void mipi_dphy_shutdownz_assert(struct dw_mipi_dsi *dsi)
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{
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regmap_update_bits(dsi->regmap, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0);
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udelay(1);
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}
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/* Start by clearing PHY state */
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regmap_write(dsi->regmap, DSI_PHY_TST_CTRL0, 0);
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regmap_write(dsi->regmap, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
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regmap_write(dsi->regmap, DSI_PHY_TST_CTRL0, 0);
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static inline void mipi_dphy_shutdownz_deassert(struct dw_mipi_dsi *dsi)
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{
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regmap_update_bits(dsi->regmap, DSI_PHY_RSTZ,
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PHY_SHUTDOWNZ, PHY_SHUTDOWNZ);
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udelay(1);
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}
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regmap_write(dphy->regmap, 0x10, BYPASS_VCO_RANGE |
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VCO_RANGE_CON_SEL(vco) | VCO_IN_CAP_CON_LOW |
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REF_BIAS_CUR_SEL);
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regmap_write(dphy->regmap, 0x11, CP_CURRENT_3MA);
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regmap_write(dphy->regmap, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
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LPF_RESISTORS_20_KOHM);
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regmap_write(dphy->regmap, 0x44, HSFREQRANGE_SEL(testdin));
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regmap_write(dphy->regmap, 0x17, INPUT_DIVIDER(dphy->input_div));
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regmap_write(dphy->regmap, 0x18, LOOP_DIV_LOW_SEL(dphy->feedback_div) |
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LOW_PROGRAM_EN);
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regmap_write(dphy->regmap, 0x18, LOOP_DIV_HIGH_SEL(dphy->feedback_div) |
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HIGH_PROGRAM_EN);
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regmap_write(dphy->regmap, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
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regmap_write(dphy->regmap, 0x22, LOW_PROGRAM_EN |
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BIASEXTR_SEL(BIASEXTR_127_7));
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regmap_write(dphy->regmap, 0x22, HIGH_PROGRAM_EN |
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BANDGAP_SEL(BANDGAP_96_10));
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regmap_write(dphy->regmap, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
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BIAS_BLOCK_ON | BANDGAP_ON);
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regmap_write(dphy->regmap, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
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SETRD_MAX | TER_RESISTORS_ON);
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regmap_write(dphy->regmap, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
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SETRD_MAX | POWER_MANAGE | TER_RESISTORS_ON);
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regmap_write(dphy->regmap, 0x60, TLP_PROGRAM_EN | ns2bc(dsi, 500));
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regmap_write(dphy->regmap, 0x61, THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
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regmap_write(dphy->regmap, 0x62, THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
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regmap_write(dphy->regmap, 0x63, THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
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regmap_write(dphy->regmap, 0x64, BIT(5) | ns2bc(dsi, 100));
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regmap_write(dphy->regmap, 0x65, BIT(5) | (ns2bc(dsi, 60) + 7));
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regmap_write(dphy->regmap, 0x70, TLP_PROGRAM_EN | ns2bc(dsi, 500));
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regmap_write(dphy->regmap, 0x71,
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THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 5));
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regmap_write(dphy->regmap, 0x72,
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THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
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regmap_write(dphy->regmap, 0x73,
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THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
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regmap_write(dphy->regmap, 0x74, BIT(5) | ns2bc(dsi, 100));
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static inline void mipi_dphy_rstz_assert(struct dw_mipi_dsi *dsi)
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{
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regmap_update_bits(dsi->regmap, DSI_PHY_RSTZ, PHY_RSTZ, 0);
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udelay(1);
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}
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regmap_write(dsi->regmap, DSI_PHY_RSTZ,
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PHY_FORCEPLL | PHY_ENABLECLK | PHY_RSTZ | PHY_SHUTDOWNZ);
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ret = regmap_read_poll_timeout(dsi->regmap, DSI_PHY_STATUS,
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val, val & PHY_LOCK, 1000,
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PHY_STATUS_TIMEOUT_US);
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if (ret < 0) {
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DRM_DEV_ERROR(dsi->dev, "failed to wait for phy lock state\n");
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return ret;
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}
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ret = regmap_read_poll_timeout(dsi->regmap, DSI_PHY_STATUS,
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val, val & PHY_STOPSTATECLKLANE, 1000,
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PHY_STATUS_TIMEOUT_US);
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if (ret < 0)
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DRM_DEV_ERROR(dsi->dev,
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"failed to wait for phy clk lane stop state\n");
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return ret;
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static inline void mipi_dphy_rstz_deassert(struct dw_mipi_dsi *dsi)
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{
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regmap_update_bits(dsi->regmap, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ);
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udelay(1);
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}
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static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi)
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{
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struct mipi_dphy *dphy = &dsi->dphy;
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const struct {
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unsigned long max_lane_mbps;
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u8 hsfreqrange;
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} hsfreqrange_table[] = {
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{ 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
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{ 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
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{ 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
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{ 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
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{ 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
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{ 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
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{ 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
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{1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
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{1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
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{1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
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};
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u8 hsfreqrange, counter;
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unsigned int index, txbyteclkhs;
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u16 n, m;
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unsigned int val, mask;
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int ret;
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clk_prepare_enable(dphy->ref_clk);
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clk_prepare_enable(dphy->cfg_clk);
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mipi_dphy_enableclk_deassert(dsi);
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mipi_dphy_shutdownz_assert(dsi);
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mipi_dphy_rstz_assert(dsi);
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testif_testclr_assert(dsi);
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/* Configures DPHY to work as a Master */
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grf_field_write(dsi, MASTERSLAVEZ, 1);
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@@ -599,13 +488,61 @@ static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi)
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grf_field_write(dsi, FORCERXMODE, 0);
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udelay(1);
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testif_testclr_deassert(dsi);
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for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++)
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if (dsi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps)
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break;
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if (index == ARRAY_SIZE(hsfreqrange_table))
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--index;
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hsfreqrange = hsfreqrange_table[index].hsfreqrange;
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regmap_write(dphy->regmap, 0x44, HSFREQRANGE(hsfreqrange));
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txbyteclkhs = dsi->lane_mbps >> 3;
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counter = txbyteclkhs * 60 / NSEC_PER_USEC;
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regmap_write(dphy->regmap, 0x60, 0x80 | counter);
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regmap_write(dphy->regmap, 0x70, 0x80 | counter);
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n = dphy->input_div - 1;
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m = dphy->feedback_div - 1;
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regmap_write(dphy->regmap, 0x19,
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FEEDBACK_DIV_DEF_VAL_BYPASS | INPUT_DIV_DEF_VAL_BYPASS);
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regmap_write(dphy->regmap, 0x17, INPUT_DIV(n));
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regmap_write(dphy->regmap, 0x18, FEEDBACK_DIV_LO(m));
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regmap_write(dphy->regmap, 0x18, FEEDBACK_DIV_HI(m >> 5));
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/* Enable Data Lane Module */
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grf_field_write(dsi, ENABLE_N, GENMASK(dsi->lanes - 1, 0));
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/* Enable Clock Lane Module */
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grf_field_write(dsi, ENABLECLK, 1);
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dw_mipi_dsi_phy_init(dsi);
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mipi_dphy_enableclk_assert(dsi);
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mipi_dphy_shutdownz_deassert(dsi);
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mipi_dphy_rstz_deassert(dsi);
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usleep_range(1500, 2000);
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ret = regmap_read_poll_timeout(dsi->regmap, DSI_PHY_STATUS,
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val, val & PHY_LOCK, 0, 1000);
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if (ret < 0) {
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DRM_DEV_ERROR(dsi->dev, "PHY is not locked\n");
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return ret;
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}
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usleep_range(100, 200);
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mask = PHY_STOPSTATELANE;
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ret = regmap_read_poll_timeout(dsi->regmap, DSI_PHY_STATUS,
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val, (val & mask) == mask,
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0, 1000);
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if (ret < 0) {
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DRM_DEV_ERROR(dsi->dev, "lane module is not in stop state\n");
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return ret;
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}
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udelay(10);
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return 0;
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}
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@@ -614,6 +551,8 @@ static void mipi_dphy_power_off(struct dw_mipi_dsi *dsi)
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||||
{
|
||||
struct mipi_dphy *dphy = &dsi->dphy;
|
||||
|
||||
regmap_write(dsi->regmap, DSI_PHY_RSTZ, 0);
|
||||
|
||||
clk_disable_unprepare(dphy->cfg_clk);
|
||||
clk_disable_unprepare(dphy->ref_clk);
|
||||
}
|
||||
@@ -670,10 +609,11 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
|
||||
struct mipi_dphy *dphy = &dsi->dphy;
|
||||
unsigned int i, pre;
|
||||
unsigned long mpclk, pllref, tmp;
|
||||
unsigned int m = 1, n = 1, target_mbps = 1000;
|
||||
unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
|
||||
unsigned int m = 1, n = 1, target_mbps = 1000, max_mbps;
|
||||
int bpp;
|
||||
|
||||
max_mbps = dsi->pdata->max_bit_rate_per_lane / USEC_PER_SEC;
|
||||
|
||||
bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
|
||||
if (bpp < 0) {
|
||||
DRM_DEV_ERROR(dsi->dev,
|
||||
@@ -940,7 +880,6 @@ static void dw_mipi_dsi_set_cmd_mode(struct dw_mipi_dsi *dsi)
|
||||
static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
|
||||
{
|
||||
regmap_write(dsi->regmap, DSI_PWR_UP, RESET);
|
||||
regmap_write(dsi->regmap, DSI_PHY_RSTZ, 0);
|
||||
}
|
||||
|
||||
static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
|
||||
@@ -956,7 +895,6 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
|
||||
u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
|
||||
|
||||
regmap_write(dsi->regmap, DSI_PWR_UP, RESET);
|
||||
regmap_write(dsi->regmap, DSI_PHY_RSTZ, 0);
|
||||
regmap_write(dsi->regmap, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
|
||||
TX_ESC_CLK_DIVISION(esc_clk_division));
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user