shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 19:30:30 +09:00
Code Issues Packages Projects Releases Wiki Activity

ASoC: rockchip: i2s-tdm: Simplify macro code

Browse Source 
Change-Id: I1d18b18f878dea44428c374727fe6e03df09973b
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This commit is contained in:
Sugar Zhang
2020-03-05 11:00:30 +08:00
parent 6b1b956d81
commit c8c52ddc10
1 changed files with 30 additions and 68 deletions
Download Patch File Download Diff File Expand all files Collapse all files

98
sound/soc/rockchip/rockchip_i2s_tdm.h
View File

@@ -280,102 +280,64 @@ enum {
#define I2S_TDM_RXCR (0x0034)
#define I2S_CLKDIV (0x0038)
/* PX30 GRF CONFIGS*/
#define PX30_I2S0_CLK_IN_SRC_MASK GENMASK(13, 12)
#define PX30_I2S0_CLK_IN_SRC_FROM_TX (0x1 << 12)
#define PX30_I2S0_CLK_IN_SRC_FROM_RX (0x2 << 12)
#define PX30_I2S0_MCLK_OUT_SRC_MSK BIT(5)
#define PX30_I2S0_MCLK_OUT_SRC_FROM_TX BIT(5)
#define PX30_I2S0_MCLK_OUT_SRC_FROM_RX 0
#define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16))
#define PX30_I2S0_CLK_MSK \
(PX30_I2S0_MCLK_OUT_SRC_MSK | \
PX30_I2S0_CLK_IN_SRC_MASK)
/* PX30 GRF CONFIGS*/
#define PX30_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 13, 12)
#define PX30_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 13, 12)
#define PX30_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 5, 5)
#define PX30_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 5, 5)
#define PX30_I2S0_CLK_TXONLY \
(PX30_I2S0_MCLK_OUT_SRC_FROM_TX | \
PX30_I2S0_CLK_IN_SRC_FROM_TX | \
(PX30_I2S0_CLK_MSK << 16))
(PX30_I2S0_MCLK_OUT_SRC_FROM_TX | PX30_I2S0_CLK_IN_SRC_FROM_TX)
#define PX30_I2S0_CLK_RXONLY \
(PX30_I2S0_MCLK_OUT_SRC_FROM_RX | \
PX30_I2S0_CLK_IN_SRC_FROM_RX | \
(PX30_I2S0_CLK_MSK << 16))
(PX30_I2S0_MCLK_OUT_SRC_FROM_RX | PX30_I2S0_CLK_IN_SRC_FROM_RX)
/* RK1808 GRF CONFIGS*/
#define RK1808_I2S0_MCLK_OUT_SRC_MSK BIT(2)
#define RK1808_I2S0_MCLK_OUT_SRC_FROM_RX BIT(2)
#define RK1808_I2S0_MCLK_OUT_SRC_FROM_TX 0
#define RK1808_I2S0_CLK_IN_SRC_MASK GENMASK(1, 0)
#define RK1808_I2S0_CLK_IN_SRC_FROM_TX (0x1 << 0)
#define RK1808_I2S0_CLK_IN_SRC_FROM_RX (0x2 << 0)
#define RK1808_I2S0_CLK_MSK \
(RK1808_I2S0_MCLK_OUT_SRC_MSK | \
RK1808_I2S0_CLK_IN_SRC_MASK)
#define RK1808_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 2, 2)
#define RK1808_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 2, 2)
#define RK1808_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 1, 0)
#define RK1808_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 1, 0)
#define RK1808_I2S0_CLK_TXONLY \
(RK1808_I2S0_MCLK_OUT_SRC_FROM_TX | \
RK1808_I2S0_CLK_IN_SRC_FROM_TX | \
(RK1808_I2S0_CLK_MSK << 16))
(RK1808_I2S0_MCLK_OUT_SRC_FROM_TX | RK1808_I2S0_CLK_IN_SRC_FROM_TX)
#define RK1808_I2S0_CLK_RXONLY \
(RK1808_I2S0_MCLK_OUT_SRC_FROM_RX | \
RK1808_I2S0_CLK_IN_SRC_FROM_RX | \
(RK1808_I2S0_CLK_MSK << 16))
(RK1808_I2S0_MCLK_OUT_SRC_FROM_RX | RK1808_I2S0_CLK_IN_SRC_FROM_RX)
/* RK3308 GRF CONFIGS*/
#define RK3308_I2S0_8CH_MCLK_OUT_SRC_MSK BIT(10)
#define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX BIT(10)
#define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_TX 0
#define RK3308_I2S0_8CH_CLK_IN_RX_SRC_MSK BIT(9)
#define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_TX BIT(9)
#define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_RX 0
#define RK3308_I2S0_8CH_CLK_IN_TX_SRC_MSK BIT(8)
#define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_RX BIT(8)
#define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_TX 0
#define RK3308_I2S1_8CH_MCLK_OUT_SRC_MSK BIT(2)
#define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_RX BIT(2)
#define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_TX 0
#define RK3308_I2S1_8CH_CLK_IN_RX_SRC_MSK BIT(1)
#define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_TX BIT(1)
#define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_RX 0
#define RK3308_I2S1_8CH_CLK_IN_TX_SRC_MSK BIT(0)
#define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_RX BIT(0)
#define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_TX 0
#define RK3308_I2S0_CLK_MSK \
(RK3308_I2S0_8CH_MCLK_OUT_SRC_MSK | \
RK3308_I2S0_8CH_CLK_IN_RX_SRC_MSK | \
RK3308_I2S0_8CH_CLK_IN_TX_SRC_MSK)
#define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 10, 10)
#define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 10, 10)
#define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_TX HIWORD_UPDATE(1, 9, 9)
#define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_RX HIWORD_UPDATE(0, 9, 9)
#define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_RX HIWORD_UPDATE(1, 8, 8)
#define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_TX HIWORD_UPDATE(0, 8, 8)
#define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 2, 2)
#define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 2, 2)
#define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_TX HIWORD_UPDATE(1, 1, 1)
#define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_RX HIWORD_UPDATE(0, 1, 1)
#define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_RX HIWORD_UPDATE(1, 0, 0)
#define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_TX HIWORD_UPDATE(0, 0, 0)
#define RK3308_I2S0_CLK_TXONLY \
(RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_TX | \
RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_TX | \
RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_TX | \
(RK3308_I2S0_CLK_MSK << 16))
RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_TX)
#define RK3308_I2S0_CLK_RXONLY \
(RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX | \
RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_RX | \
RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_RX | \
(RK3308_I2S0_CLK_MSK << 16))
#define RK3308_I2S1_CLK_MSK \
(RK3308_I2S1_8CH_MCLK_OUT_SRC_MSK | \
RK3308_I2S1_8CH_CLK_IN_RX_SRC_MSK | \
RK3308_I2S1_8CH_CLK_IN_TX_SRC_MSK)
RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_RX)
#define RK3308_I2S1_CLK_TXONLY \
(RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_TX | \
RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_TX | \
RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_TX | \
(RK3308_I2S1_CLK_MSK << 16))
RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_TX)
#define RK3308_I2S1_CLK_RXONLY \
(RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_RX | \
RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_RX | \
RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_RX | \
(RK3308_I2S1_CLK_MSK << 16))
RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_RX)
#endif /* _ROCKCHIP_I2S_TDM_H */