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clk: rockchip: add new pll type pll_rk3588_ddr

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Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ia38a7b5d95a9d5b4c4f27c1adaa310ba4308afbd
This commit is contained in:
Elaine Zhang
2024-01-30 09:17:32 +08:00
committed by Tao Huang
parent 096f12b891
commit c99648df60
2 changed files with 6 additions and 1 deletions
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6
drivers/clk/rockchip/clk-pll.c
View File

@@ -1409,7 +1409,10 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw,
}
rate64 = rate64 >> cur.s;
return (unsigned long)rate64;
if (pll->type == pll_rk3588_ddr)
return (unsigned long)rate64 * 2;
else
return (unsigned long)rate64;
}
static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
@@ -1845,6 +1848,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
#ifdef CONFIG_ROCKCHIP_PLL_RK3588
case pll_rk3588:
case pll_rk3588_core:
case pll_rk3588_ddr:
if (!pll->rate_table)
init.ops = &rockchip_rk3588_pll_clk_norate_ops;
else

1
drivers/clk/rockchip/clk.h
View File

@@ -452,6 +452,7 @@ enum rockchip_pll_type {
pll_rk3399,
pll_rk3588,
pll_rk3588_core,
pll_rk3588_ddr,
};
#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \